Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Timestamp:
- Dec 19, 2008, 4:34:00 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r88 r97 97 97 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); 98 98 //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); 99 99 //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); 100 100 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) 101 101 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) … … 106 106 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); 107 107 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); 108 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",T general_data_t,_param->_nb_inst_memory);108 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_memory); 109 109 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); 110 110 ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); … … 169 169 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 170 170 //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 171 171 //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 172 172 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 173 173 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); … … 520 520 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); 521 521 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); 522 TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY );522 // TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); 523 523 524 524 if (is_operation_memory_load (tab_request[packet_id]._operation)) … … 730 730 DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 731 731 //DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 732 732 //DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 733 733 DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 734 734 DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r88 r97 118 118 public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] 119 119 //public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] 120 120 //public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] 121 121 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 122 122 public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) … … 127 127 public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] 128 128 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] 129 public : SC_OUT(T general_data_t) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory]129 public : SC_OUT(Taddress_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] 130 130 131 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r81 r97 235 235 }; 236 236 237 238 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tstore_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tstore_queue_state_t& x) 239 { 240 switch (x) 241 { 242 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_EMPTY : return "empty" ; break; 243 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_NO_VALID_NO_SPECULATIVE : return "no_valid_no_speculative"; break; 244 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_SPECULATIVE : return "valid_speculative" ; break; 245 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_NO_SPECULATIVE : return "valid_no_speculative" ; break; 246 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_COMMIT : return "commit" ; break; 247 default : return "" ; break; 248 } 249 }; 250 251 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_access_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_access_queue_state_t& x) 252 { 253 switch (x) 254 { 255 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_EMPTY : return "empty" ; break; 256 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE : return "wait_cache" ; break; 257 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE : return "wait_load_queue"; break; 258 default : return "" ; break; 259 } 260 }; 261 262 template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tload_queue_state_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tload_queue_state_t& x) 263 { 264 switch (x) 265 { 266 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_EMPTY : return "empty" ; break; 267 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT_CHECK : return "wait_check" ; break; 268 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT : return "wait" ; break; 269 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT_CHECK : return "commit_check"; break; 270 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_CHECK : return "check" ; break; 271 case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT : return "commit" ; break; 272 default : return "" ; break; 273 } 274 }; 275 237 276 }; // end namespace morpheo 238 277 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r88 r97 72 72 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 73 73 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t, 1);74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 75 75 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t, 1);76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); 77 77 } 78 78 … … 88 88 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 89 89 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 90 90 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 91 91 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 92 92 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 93 93 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); 94 94 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_ general_register );96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_ general_data );95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); 96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); 97 97 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 98 98 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,T general_data_t ,_param->_size_general_data);99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 100 100 } 101 101 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r88 r97 63 63 DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 64 64 // DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 65 65 // DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 66 66 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); 67 67 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r88 r97 121 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); 122 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); 123 123 // PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); 124 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); 125 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r88 r97 23 23 void Load_store_unit::function_speculative_load_commit_transition (void) 24 24 { 25 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 25 log_begin(Load_store_unit,FUNCTION); 26 log_function(Load_store_unit,FUNCTION,_name.c_str()); 26 27 27 28 if (PORT_READ(in_NRESET) == 0) … … 53 54 54 55 // solution 1) 55 log_printf(TRACE,Load_store_unit,FUNCTION," CHECK");56 log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK"); 56 57 for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) 57 58 { … … 63 64 is_operation_memory_load(_load_queue[index_load]._operation)) 64 65 { 65 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load);66 log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); 66 67 67 68 nb_check++; // use one port … … 283 284 // - second is the information of re order buffer : the store become not speculative and can access at the data cache 284 285 285 log_printf(TRACE,Load_store_unit,FUNCTION," store_queue");286 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");286 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue"); 287 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); 287 288 288 289 // Write pointer is define in rename stage : 289 290 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 290 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);291 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 291 292 292 293 // Need read : state and exception. … … 373 374 if (update_info == true) 374 375 { 375 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information");376 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); 376 377 377 378 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); … … 395 396 396 397 // In speculative access queue, they are many type's request 397 log_printf(TRACE,Load_store_unit,FUNCTION," speculative_access_queue");398 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");398 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); 399 log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); 399 400 400 401 // Write in reservation station 401 402 uint32_t index = _speculative_access_queue_control->push(); 402 403 403 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index);404 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); 404 405 405 406 Texception_t exception; … … 428 429 _speculative_access_queue [index]._exception = exception; 429 430 430 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);431 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 431 432 } 432 433 } … … 439 440 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 440 441 { 441 log_printf(TRACE,Load_store_unit,FUNCTION," MEMORY_OUT transaction");442 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction"); 442 443 443 444 switch (internal_MEMORY_OUT_SELECT_QUEUE) … … 449 450 // ======================= 450 451 451 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);452 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); 452 453 453 454 // Entry flush and increase the read pointer … … 464 465 // ====================== 465 466 466 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR);467 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); 467 468 468 469 // Entry flush and increase the read pointer … … 476 477 case SELECT_LOAD_QUEUE_SPECULATIVE : 477 478 { 478 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR);479 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); 479 480 480 481 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; … … 497 498 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 498 499 { 499 log_printf(TRACE,Load_store_unit,FUNCTION," DCACHE_REQ");500 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ"); 500 501 501 502 switch (internal_DCACHE_REQ_SELECT_QUEUE) … … 587 588 _load_queue [ptr_write]._rdata = address; // to the exception 588 589 589 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue");590 log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]);590 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); 591 log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); 591 592 592 593 _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; … … 601 602 ( internal_DCACHE_RSP_ACK == 1)) 602 603 { 603 log_printf(TRACE,Load_store_unit,FUNCTION," DCACHE_RSP");604 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP"); 604 605 605 606 // don't use context_id : because there are one queue for all thread … … 609 610 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 610 611 611 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id);612 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); 612 613 613 614 if (DCACHE_RSP_IS_LOAD(packet_id) == 1) … … 615 616 packet_id >>= 1; 616 617 617 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id);618 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); 618 619 619 620 … … 626 627 if (error != DCACHE_ERROR_NONE) 627 628 { 628 log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!");629 log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); 629 630 630 631 _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; … … 633 634 else 634 635 { 635 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error.");636 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state);636 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); 637 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); 637 638 638 639 // FIXME : convention : if bus error, the cache return the fautive address ! … … 650 651 else 651 652 { 652 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE");653 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); 653 654 654 655 // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! … … 664 665 #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) 665 666 // ***** dump store queue 666 std::cout << "Dump STORE_QUEUE :" << std::endl 667 << "ptr_read : " << toString(static_cast<uint32_t>(reg_STORE_QUEUE_PTR_READ)) << std::endl;667 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE"); 668 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); 668 669 669 670 for (uint32_t i=0; i<_param->_size_store_queue; i++) 670 671 { 671 672 uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 672 std::cout << "{" << j << "}" << std::endl 673 << _store_queue[j] << std::endl; 673 674 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %s", 675 j, 676 _store_queue[j]._context_id , 677 _store_queue[j]._front_end_id , 678 _store_queue[j]._ooo_engine_id , 679 _store_queue[j]._packet_id , 680 _store_queue[j]._operation , 681 _store_queue[j]._load_queue_ptr_write, 682 _store_queue[j]._address , 683 _store_queue[j]._wdata , 684 //_store_queue[j]._write_rd , 685 //_store_queue[j]._num_reg_rd , 686 _store_queue[j]._exception , 687 toString(_store_queue[j]._state).c_str()); 674 688 } 675 689 676 690 // ***** dump speculative_access queue 677 std::cout << "Dump SPECULATIVE_ACCESS_QUEUE :" << std::endl;691 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE"); 678 692 679 693 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 680 694 { 681 695 uint32_t j = (*_speculative_access_queue_control)[i]; 682 std::cout << "{" << j << "}" << std::endl 683 << _speculative_access_queue[j] << std::endl; 696 697 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s", 698 j, 699 _speculative_access_queue[j]._context_id , 700 _speculative_access_queue[j]._front_end_id , 701 _speculative_access_queue[j]._ooo_engine_id , 702 _speculative_access_queue[j]._packet_id , 703 _speculative_access_queue[j]._operation , 704 _speculative_access_queue[j]._load_queue_ptr_write, 705 _speculative_access_queue[j]._store_queue_ptr_write, 706 _speculative_access_queue[j]._address , 707 _speculative_access_queue[j]._write_rd , 708 _speculative_access_queue[j]._num_reg_rd , 709 _speculative_access_queue[j]._exception , 710 toString(_speculative_access_queue[j]._state).c_str()); 684 711 } 685 712 686 713 // ***** dump load queue 687 std::cout << "Dump LOAD_QUEUE :" << std::endl688 << "ptr_read_check_priority : " << toString(static_cast<uint32_t>(reg_LOAD_QUEUE_CHECK_PRIORITY)) << std::endl;714 log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE"); 715 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY); 689 716 690 717 for (uint32_t i=0; i<_param->_size_load_queue; i++) 691 718 { 692 719 uint32_t j = i; 693 std::cout << "{" << j << "}" << std::endl 694 << _load_queue[j] << std::endl; 720 721 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s", 722 j, 723 _load_queue[j]._context_id , 724 _load_queue[j]._front_end_id , 725 _load_queue[j]._ooo_engine_id , 726 _load_queue[j]._packet_id , 727 _load_queue[j]._operation , 728 _load_queue[j]._store_queue_ptr_write, 729 _load_queue[j]._address , 730 _load_queue[j]._check_hit_byte , 731 _load_queue[j]._check_hit , 732 _load_queue[j]._shift , 733 _load_queue[j]._is_load_signed , 734 _load_queue[j]._access_size , 735 _load_queue[j]._rdata , 736 _load_queue[j]._write_rd , 737 _load_queue[j]._num_reg_rd , 738 _load_queue[j]._exception , 739 toString(_load_queue[j]._state).c_str()); 695 740 } 696 741 #endif … … 712 757 } 713 758 714 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");759 log_end(Load_store_unit,FUNCTION); 715 760 }; 716 761 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r88 r97 69 69 if (is_toplevel) 70 70 { 71 _size_instruction_address = size_general_data-2; 71 72 _size_context_id = log2(nb_context ); 72 73 _size_front_end_id = log2(nb_front_end );
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