- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 2 deleted
- 8 edited
- 57 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r120 r145 32 32 CONTEXT_STATE_KO_MISS_BRANCH_ADDR , // update address manager 33 33 CONTEXT_STATE_KO_MISS_BRANCH_WAITEND , // wait end of event (miss branch) 34 CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE , // wait end of event (miss branch) 34 35 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 35 36 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) … … 69 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 70 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend" ; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : return "context_state_ko_miss_branch_inaccurate" ; break; 71 73 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : return "context_state_ko_miss_load_and_branch_wait_update"; break; 72 74 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : return "context_state_ko_miss_load_and_branch_addr" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_statistics_allocation.cpp
r120 r145 40 40 for (uint32_t i=0; i<_param->_nb_context; ++i) 41 41 { 42 _stat_nb_cycle_state_ok [i] = _stat->create_counter("nb_cycle_state_ok_" +toString(i),"",toString(_("Number of cycle in state ok (context %d)"),i)); 43 _stat_nb_cycle_state_ko_excep [i] = _stat->create_counter("nb_cycle_state_ko_excep_" +toString(i),"",toString(_("Number of cycle in state ko_excep (context %d)"),i)); 44 _stat_nb_cycle_state_ko_miss_branch [i] = _stat->create_counter("nb_cycle_state_ko_miss_branch_" +toString(i),"",toString(_("Number of cycle in state ko_miss_branch (context %d)"),i)); 45 _stat_nb_cycle_state_ko_miss_load [i] = _stat->create_counter("nb_cycle_state_ko_miss_load_" +toString(i),"",toString(_("Number of cycle in state ko_miss_load (context %d)"),i)); 46 _stat_nb_cycle_state_ko_miss_load_and_branch [i] = _stat->create_counter("nb_cycle_state_ko_miss_load_and_branch_"+toString(i),"",toString(_("Number of cycle in state ko_miss_load_and_branch (context %d)"),i)); 47 _stat_nb_cycle_state_ko_msync [i] = _stat->create_counter("nb_cycle_state_ko_msync_" +toString(i),"",toString(_("Number of cycle in state ko_msync (context %d)"),i)); 48 _stat_nb_cycle_state_ko_psync [i] = _stat->create_counter("nb_cycle_state_ko_psync_" +toString(i),"",toString(_("Number of cycle in state ko_psync (context %d)"),i)); 49 _stat_nb_cycle_state_ko_csync [i] = _stat->create_counter("nb_cycle_state_ko_csync_" +toString(i),"",toString(_("Number of cycle in state ko_csync (context %d)"),i)); 50 _stat_nb_cycle_state_ko_spr [i] = _stat->create_counter("nb_cycle_state_ko_spr_" +toString(i),"",toString(_("Number of cycle in state ko_spr (context %d)"),i)); 51 42 _stat_nb_cycle_state_ok [i] = _stat->create_variable("nb_cycle_state_ok_" +toString(i)); 43 _stat_nb_cycle_state_ko_excep [i] = _stat->create_variable("nb_cycle_state_ko_excep_" +toString(i)); 44 _stat_nb_cycle_state_ko_miss_branch [i] = _stat->create_variable("nb_cycle_state_ko_miss_branch_" +toString(i)); 45 _stat_nb_cycle_state_ko_miss_load [i] = _stat->create_variable("nb_cycle_state_ko_miss_load_" +toString(i)); 46 _stat_nb_cycle_state_ko_miss_load_and_branch [i] = _stat->create_variable("nb_cycle_state_ko_miss_load_and_branch_"+toString(i)); 47 _stat_nb_cycle_state_ko_msync [i] = _stat->create_variable("nb_cycle_state_ko_msync_" +toString(i)); 48 _stat_nb_cycle_state_ko_psync [i] = _stat->create_variable("nb_cycle_state_ko_psync_" +toString(i)); 49 _stat_nb_cycle_state_ko_csync [i] = _stat->create_variable("nb_cycle_state_ko_csync_" +toString(i)); 50 _stat_nb_cycle_state_ko_spr [i] = _stat->create_variable("nb_cycle_state_ko_spr_" +toString(i)); 52 51 53 52 _stat->create_expr_percent("percent_state_ok_" +toString(i),"nb_cycle_state_ok_" +toString(i),"cycle",toString(_("Percent of cycle in state ok (context %d)"),i)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r128 r145 33 33 (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ 34 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ 35 (state == CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE ) or \ 35 36 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?PRIORITY_MISS_BRANCH: \ 36 37 ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION: \ … … 112 113 // state = CONTEXT_STATE_OK; 113 114 state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 115 break; 116 } 117 case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : 118 { 119 if (inst_all == 0) 120 // state = CONTEXT_STATE_OK; 121 state = CONTEXT_STATE_OK; 114 122 break; 115 123 } … … 321 329 if (can_continue) 322 330 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 323 else 324 { 325 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) 326 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 327 // #else 328 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; 329 // #endif 330 } 331 else 332 // cf UPT : dest_val = direction, accurate depend of jump type (e.g. jr is inacurate) 333 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; 334 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE; 331 335 332 336 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot … … 647 651 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 648 652 case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : 653 case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : 649 654 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : 650 655 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : … … 752 757 case CONTEXT_STATE_KO_EXCEP_SPR : (*_stat_nb_cycle_state_ko_excep [i])++; break; 753 758 759 case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : 754 760 case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : 755 761 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r139 r145 71 71 std::list<generic::priority::select_t> * select = _priority->select(); 72 72 std::list<generic::priority::select_t>::iterator it=select->begin(); 73 73 74 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 74 75 { … … 76 77 77 78 bool ifetch_val = false; 78 while ((it != select->end()) and // have a no scanned "slot_in" ? 79 80 while ((it != select->end()) and // have a no scanned instruction from ifetch_unit ? 79 81 // (decod_val [i] == false) and // have not a previous selected entry? 80 82 (ifetch_val == false) and // not find ifetch instruction valid 81 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) 83 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy)) 82 84 { 83 85 // predict_val [i] = false; 84 86 85 Tcontext_t x = it->grp; 86 uint32_t y = it->elt; 87 Tcontext_t x = it->grp; // num_front_end 88 uint32_t y = it->elt; // num_instruction 87 89 88 90 log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); … … 102 104 Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]); 103 105 106 // Read instruction and set default value 104 107 _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); 105 108 _decod_instruction->_context_id = x; … … 132 135 _decod_instruction->_branch_direction = 0; // not necessary 133 136 _decod_instruction->_event_type = EVENT_TYPE_NONE; // not necessary 134 135 136 137 // Test IFetch exception 137 138 // Test if ifetch_unit have an exception (per example : IBERR) 138 139 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]); 139 140 140 141 if (ifetch_exception == EXCEPTION_IFETCH_NONE) 141 142 { 142 // Decod !143 // No exception, can Decod ! 143 144 log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); 144 145 log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); … … 150 151 else 151 152 { 152 // No decod : nop 153 // Exception : transform this instruction in a nop 154 // * INSTRUCTION_TLB 155 // * INSTRUCTION_PAGE 156 // * BUS_ERROR 157 158 log_printf(TRACE,Decod,FUNCTION," * exception -> change instruction in a l.nop"); 159 153 160 instruction_l_nop (_decod_instruction, _decod_param[x]); 154 161 … … 156 163 _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); 157 164 158 // INSTRUCTION_TLB159 // INSTRUCTION_PAGE160 // BUS_ERROR161 165 if (_decod_instruction->_is_delay_slot) 162 166 _decod_instruction->_address_next = _decod_instruction->_address_previous; … … 167 171 } 168 172 169 Ttype_t type = _decod_instruction->_type; 170 // Depth current. If have decod a branch and i can continue : depth = depth_next 171 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; 172 // Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x]; 173 Tcontrol_t no_execute = _decod_instruction->_no_execute; 174 173 Ttype_t type = _decod_instruction->_type; 174 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; 175 Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition; 176 177 // Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal) 178 179 //Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x]; 180 // Tcontrol_t save_rat = ((type == TYPE_BRANCH) and 181 // not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or 182 // (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK))); 183 184 Tcontrol_t save_rat = ((type == TYPE_BRANCH) and 185 not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK)); 186 187 // FIXME : depth+1 valid ??????? 175 188 if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x]) 176 189 depth = (depth+1)%_param->_nb_branch_speculated[x]; 177 190 191 // Write output 178 192 if (_param->_have_port_context_id) 179 193 PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); … … 185 199 PORT_WRITE(out_DECOD_TYPE [i], type); 186 200 PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); 187 PORT_WRITE(out_DECOD_NO_EXECUTE [i], no_execute);201 PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); 188 202 PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); 189 // PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat); 190 PORT_WRITE(out_DECOD_SAVE_RAT [i], ((type == TYPE_BRANCH) and not no_execute)); 203 PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat); 191 204 #ifdef DEBUG 192 205 PORT_WRITE(out_DECOD_ADDRESS [i], addr); 193 206 #endif 194 // if ((type == TYPE_BRANCH) and195 // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or196 // (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET)))197 // PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address+2);198 // else199 207 PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); 200 208 PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); … … 206 214 PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); 207 215 PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); 208 PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); 216 PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0 209 217 PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); 210 218 PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); … … 224 232 log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); 225 233 log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); 226 227 234 log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); 228 235 log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); 229 236 230 // test if have already decod an branch : one branch per context 231 predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y] // and decod_val [i] 232 ; 237 // test if have already decod an branch : ONCE BRANCH PER CONTEXT 238 predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y]; // and decod_val [i] 233 239 decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable 234 240 ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack … … 252 258 if (_param->_have_port_depth) 253 259 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y])); 254 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i], _decod_instruction->_branch_condition);260 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],branch_condition); 255 261 // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); 256 262 PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); … … 266 272 // speculative jump at the exception handler 267 273 // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE 268 context_event_val = ifetch_ack [x][y] // and decod_val [i] 269 ; 274 context_event_val = ifetch_ack [x][y]; // and decod_val [i] 270 275 decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable 271 276 ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack … … 277 282 CONTEXT_EVENT_ADDRESS = _decod_instruction->_address; 278 283 CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ; 279 280 284 } 281 285 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_full_assoc_transition.cpp
r141 r145 205 205 for (uint32_t i=0; i<_param->_size_queue; i++) 206 206 { 207 uint32_t index=(i+reg_PTR_READ)%_param->_size_queue; 208 207 209 log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", 208 i ,209 _queue [i ]->_address,210 _queue [i ]->_address<<2,211 _queue [i ]->_inst_ifetch_ptr,212 _queue [i ]->_branch_state,213 _queue [i ]->_branch_update_prediction_id,214 _queue [i ]->_exception,215 toString(_queue [i ]->_state).c_str()210 index, 211 _queue [index]->_address, 212 _queue [index]->_address<<2, 213 _queue [index]->_inst_ifetch_ptr, 214 _queue [index]->_branch_state, 215 _queue [index]->_branch_update_prediction_id, 216 _queue [index]->_exception, 217 toString(_queue [index]->_state).c_str() 216 218 ); 217 219 218 for (uint32_t j=0; j<_param->_nb_instruction; j++) 219 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); 220 if (_queue [index]->_state != IFETCH_QUEUE_STATE_EMPTY) 221 for (uint32_t j=0; j<_param->_nb_instruction; j++) 222 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x (0x%.8x)", _queue [index]->_instruction_enable[j], _queue [index]->_instruction[j],(_queue [index]->_address+j)<<2); 220 223 } 221 224 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_function_no_assoc_transition.cpp
r141 r145 173 173 for (uint32_t i=0; i<_param->_size_queue; i++) 174 174 { 175 uint32_t index=(i+reg_PTR_READ)%_param->_size_queue; 175 176 log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", 176 i ,177 _queue [i ]->_address,178 _queue [i ]->_address<<2,179 _queue [i ]->_inst_ifetch_ptr,180 _queue [i ]->_branch_state,181 _queue [i ]->_branch_update_prediction_id,182 _queue [i ]->_exception,183 toString(_queue [i ]->_state).c_str()177 index, 178 _queue [index]->_address, 179 _queue [index]->_address<<2, 180 _queue [index]->_inst_ifetch_ptr, 181 _queue [index]->_branch_state, 182 _queue [index]->_branch_update_prediction_id, 183 _queue [index]->_exception, 184 toString(_queue [index]->_state).c_str() 184 185 ); 185 186 186 for (uint32_t j=0; j<_param->_nb_instruction; j++) 187 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); 187 if (_queue [index]->_state != IFETCH_QUEUE_STATE_EMPTY) 188 for (uint32_t j=0; j<_param->_nb_instruction; j++) 189 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x (0x%.8x)", _queue [index]->_instruction_enable[j], _queue [index]->_instruction[j],(_queue [index]->_address+j)<<2); 188 190 } 189 191 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp
r123 r145 78 78 // * branch was not detected 79 79 Tcontrol_t miss_decod = (branch_state == BRANCH_STATE_NONE); 80 Tcontrol_t can_continue = false;80 Tcontrol_t can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]); 81 81 82 82 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d] : valid",decod_unit,i); … … 212 212 } 213 213 214 can_continue = false; // need update upt 214 // can_continue = false; // need update upt 215 can_continue &= not take; 215 216 } 216 217 else … … 218 219 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit"); 219 220 220 if (branch_state == BRANCH_STATE_SPEC_NTAKE) 221 can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]); 222 else 223 // BRANCH_STATE_NONE -> miss 224 // BRANCH_STATE_NSPEC_TAKE -> take 225 // BRANCH_STATE_SPEC_TAKE -> take 226 can_continue = false; 227 221 // can_continue = PORT_READ(in_DECOD_UPT_CAN_CONTINUE [port]); 228 222 // miss_decod = false; 229 223 // // Hit speculation -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r134 r145 90 90 reg_EVENT_ADDRESS_DEST [i] = 0; // not necessary 91 91 reg_EVENT_CAN_CONTINUE [i] = 0; // not necessary 92 93 92 } 94 93 } … … 328 327 { 329 328 // Have a miss !!! 330 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!");329 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!"); 331 330 332 331 condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); … … 350 349 bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch)); 351 350 352 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue);353 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction );354 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch );355 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt );351 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue); 352 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction ); 353 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch ); 354 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt ); 356 355 357 356 // Test if can continue without flushing the ufpt (and ifetch_queue) … … 378 377 379 378 reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT; 380 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());379 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str()); 381 380 382 381 // Need Flush UPFT … … 820 819 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 821 820 reg_EVENT_ADDRESS_DEST [context] = good_addr; 822 reg_EVENT_CAN_CONTINUE [context] = false;823 821 reg_EVENT_CAN_CONTINUE [context] = true; 822 // reg_EVENT_CAN_CONTINUE [context] = false; 824 823 } 825 824 … … 1184 1183 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UFPT_STATE : %s" ,toString(reg_UFPT_EVENT_STATE [i]).c_str()); 1185 1184 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_STATE : %s" ,toString(reg_UPT_EVENT_STATE [i]).c_str()); 1186 // 1185 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); 1187 1186 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 1188 1187 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]); 1189 // 1188 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]); 1190 1189 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 1191 1190 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
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