Changeset 15 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src
- Timestamp:
- Apr 5, 2007, 4:17:30 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Parameters.cpp
r2 r15 30 30 _param_counter = new morpheo::behavioural::generic::counter::Parameters (size_counter , 31 31 nb_branch_complete ); 32 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (nb_prediction ,33 34 35 32 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (nb_prediction , 33 nb_branch_complete , 34 nb_counter , 35 size_counter ); 36 36 37 37 … … 51 51 param._nb_branch_complete ); 52 52 53 _param_registerfile = new morpheo::behavioural::generic::registerfile:: Parameters (param._nb_prediction ,54 55 56 57 53 _param_registerfile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters (param._nb_prediction , 54 param._nb_branch_complete , 55 param._nb_counter , 56 param._size_counter ); 57 58 58 test(); 59 59 log_printf(FUNC,Pattern_History_Table,"Parameters","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp
r2 r15 58 58 allocation (); 59 59 60 // Constant61 for (uint32_t i=0; i<_param._nb_prediction ; i++)62 PORT_WRITE(out_PREDICT_ACK [i],1);63 for (uint32_t i=0; i<_param._nb_branch_complete; i++)64 PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1);60 // // Constant 61 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 62 // PORT_WRITE(out_PREDICT_ACK [i],1); 63 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 64 // PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],1); 65 65 66 66 #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp
r3 r15 25 25 26 26 in_CLOCK = new SC_CLOCK ("in_CLOCK"); 27 in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET"); 27 28 28 29 in_PREDICT_VAL = new SC_IN (Tcontrol_t) * [_param._nb_prediction]; … … 104 105 name_component = _name+"_RegisterFile"; 105 106 106 component_RegisterFile = new morpheo::behavioural::generic::registerfile:: RegisterFile(name_component.c_str(),107 component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic (name_component.c_str(), 107 108 #ifdef STATISTICS 108 109 _param_statistics , 109 110 #endif 110 111 111 *(_param._param_registerfile)); 112 112 113 // Instantiation 113 114 (*(component_RegisterFile->in_CLOCK)) (*(in_CLOCK)); 114 115 (*(component_RegisterFile->in_NRESET)) (*(in_NRESET)); 116 115 117 for (uint32_t i=0; i<_param._nb_prediction; i++) 116 118 { 117 (*(component_RegisterFile-> in_READ_ENABLE [i])) (*( in_PREDICT_VAL [i])); 119 (*(component_RegisterFile-> in_READ_VAL [i])) (*( in_PREDICT_VAL [i])); 120 (*(component_RegisterFile->out_READ_ACK [i])) (*(out_PREDICT_ACK [i])); 118 121 (*(component_RegisterFile-> in_READ_ADDRESS [i])) (*( in_PREDICT_ADDRESS [i])); 119 122 (*(component_RegisterFile->out_READ_DATA [i])) (*(out_PREDICT_HISTORY [i])); … … 122 125 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 123 126 { 124 (*(component_RegisterFile-> in_WRITE_ENABLE [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 127 (*(component_RegisterFile-> in_WRITE_VAL [i])) (*( in_BRANCH_COMPLETE_VAL [i])); 128 (*(component_RegisterFile->out_WRITE_ACK [i])) (*( out_BRANCH_COMPLETE_ACK [i])); 125 129 (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*( in_BRANCH_COMPLETE_ADDRESS [i])); 126 130 (*(component_RegisterFile-> in_WRITE_DATA [i])) (*(signal_BRANCH_COMPLETE_HISTORY [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp
r3 r15 23 23 24 24 delete in_CLOCK; 25 delete in_NRESET; 25 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp
r3 r15 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); 23 23 24 vhdl.set_body ("-- Output : always at '1'");25 for (uint32_t i=0; i<_param._nb_branch_complete; i++)26 vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");27 for (uint32_t i=0; i<_param._nb_prediction ; i++)28 vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';");29 vhdl.set_body ("");24 // vhdl.set_body ("-- Output : always at '1'"); 25 // for (uint32_t i=0; i<_param._nb_branch_complete; i++) 26 // vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); 27 // for (uint32_t i=0; i<_param._nb_prediction ; i++) 28 // vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); 29 // vhdl.set_body (""); 30 30 31 31 list<string> list_port_map; … … 41 41 42 42 list_port_map.clear(); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); 43 vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); 44 vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); 45 44 46 for (uint32_t i=0; i<_param._nb_prediction; i++) 45 47 { 46 vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 48 vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); 49 vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+" ","out_PREDICT_ACK_"+toString(i)); 47 50 vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); 48 51 vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); … … 51 54 for (uint32_t i=0; i<_param._nb_branch_complete; i++) 52 55 { 53 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 56 vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); 57 vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+" "," out_BRANCH_COMPLETE_ACK_"+toString(i)+""); 54 58 vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); 55 59 vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp
r3 r15 23 23 24 24 vhdl.set_port (" in_CLOCK" , IN, 1); 25 vhdl.set_port (" in_NRESET", IN, 1); 25 26 26 27 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_port.cpp
r3 r15 21 21 { 22 22 log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_port","Begin"); 23 24 _vhdl_testbench->set_port (" in_NRESET", IN, 1); 23 25 24 26 for (uint32_t i=0; i<_param._nb_prediction; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp
r3 r15 30 30 // (because we have no control on the ordonnancer's policy) 31 31 32 _vhdl_testbench->add_input (PORT_READ( in_NRESET)); 33 32 34 for (uint32_t i=0; i<_param._nb_prediction; i++) 33 35 { 34 36 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_VAL [i])); 35 _vhdl_testbench->add_output (PORT_READ( out_PREDICT_ACK[i]));37 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK [i])); 36 38 _vhdl_testbench->add_input (PORT_READ( in_PREDICT_ADDRESS [i])); 37 39 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i])); … … 42 44 { 43 45 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); 44 _vhdl_testbench->add_output (PORT_READ( out_BRANCH_COMPLETE_ACK[i]));46 _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i])); 45 47 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_ADDRESS [i])); 46 48 _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i]));
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