Ignore:
Timestamp:
Jul 5, 2007, 5:50:19 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp

    r15 r42  
    1818
    1919
    20   void Pattern_History_Table::vhdl_body (Vhdl & vhdl)
     20  void Pattern_History_Table::vhdl_body (Vhdl * & vhdl)
    2121  {
    2222    log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin");
    2323
    24 //     vhdl.set_body ("-- Output : always at '1'");
     24//     vhdl->set_body ("-- Output : always at '1'");
    2525//     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    26 //       vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
     26//       vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
    2727//     for (uint32_t i=0; i<_param._nb_prediction     ; i++)
    28 //       vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
    29 //     vhdl.set_body ("");
    30 
    31     list<string> list_port_map;
    32 
    33     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    34       {
    35         vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+"     ","    in_BRANCH_COMPLETE_HISTORY_"+toString(i));
    36         vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+"   ","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i)    );
    37         vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+"     ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
    38       }
    39     vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map);
    40 
    41 
    42     list_port_map.clear();
    43     vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK ");
    44     vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");
    45 
    46     for (uint32_t i=0; i<_param._nb_prediction; i++)
    47       {
    48         vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+"     "," in_PREDICT_VAL_"+toString(i));
    49         vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+"     ","out_PREDICT_ACK_"+toString(i));
    50         vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));
    51         vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+"    ","out_PREDICT_HISTORY_"+toString(i));   
    52       }
    53    
    54     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    55       {
    56         vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+"    ","    in_BRANCH_COMPLETE_VAL_"+toString(i)+"");
    57         vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+"    ","   out_BRANCH_COMPLETE_ACK_"+toString(i)+"");
    58         vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+"","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
    59         vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+"   ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
    60       }
    61     vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);
     28//       vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
     29//     vhdl->set_body ("");
    6230
    6331    log_printf(FUNC,Pattern_History_Table,"vhdl_body","End");
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