Ignore:
Timestamp:
Jul 5, 2007, 5:50:19 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp

    r15 r42  
    2222    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin");
    2323
    24 #ifndef SYSTEMCASS_SPECIFIC
    25     sc_cycle(0);
    26 #endif   
     24    sc_start(0);
    2725
    28     // In order with file Pattern_History_Table_vhdl_testbench_port.cpp
    29     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    30     // (because we have no control on the ordonnancer's policy)
    31 
    32     _vhdl_testbench->add_input  (PORT_READ( in_NRESET));
    33 
    34     for (uint32_t i=0; i<_param._nb_prediction; i++)
    35       {
    36         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_VAL     [i]));
    37         _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK  [i]));
    38         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS [i]));
    39         _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i]));
    40       //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i]));
    41       }
    42 
    43      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    44        {
    45          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_VAL      [i]));
    46          _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i]));
    47          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS  [i]));
    48          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_HISTORY  [i]));
    49          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i]));
    50        }
    51        
    52     // add_test :
    53     //  - True  : the cycle must be compare with the output of systemC
    54     //  - False : no test
    55     _vhdl_testbench->add_test(true);
    56 
    57     _vhdl_testbench->new_cycle (); // always at the end
     26    _interfaces->testbench();
    5827
    5928    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End");
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