- Timestamp:
- Sep 28, 2007, 2:58:08 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile
- Files:
-
- 2 added
- 26 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/mkf.info
r55 r57 20 20 target_dep RegisterFile_Monolithic_3.prj RegisterFile_Monolithic_3_Pack.vhdl RegisterFile_Monolithic_3.vhdl 21 21 22 # RegisterFile_Monolithic_4 23 target_dep all RegisterFile_Monolithic_4.ngc 24 target_dep RegisterFile_Monolithic_4.ngc RegisterFile_Monolithic_4.prj 25 target_dep RegisterFile_Monolithic_4.prj RegisterFile_Monolithic_4_Pack.vhdl RegisterFile_Monolithic_4.vhdl 26 27 # RegisterFile_Monolithic_5 28 target_dep all RegisterFile_Monolithic_5.ngc 29 target_dep RegisterFile_Monolithic_5.ngc RegisterFile_Monolithic_5.prj 30 target_dep RegisterFile_Monolithic_5.prj RegisterFile_Monolithic_5_Pack.vhdl RegisterFile_Monolithic_5.vhdl 31 32 # RegisterFile_Monolithic_6 33 target_dep all RegisterFile_Monolithic_6.ngc 34 target_dep RegisterFile_Monolithic_6.ngc RegisterFile_Monolithic_6.prj 35 target_dep RegisterFile_Monolithic_6.prj RegisterFile_Monolithic_6_Pack.vhdl RegisterFile_Monolithic_6.vhdl 36 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r55 r57 7 7 */ 8 8 9 #define NB_ITERATION 29 #define NB_ITERATION 1 10 10 11 11 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h
r55 r57 27 27 #include "Behavioural/include/Vhdl.h" 28 28 #endif 29 #include "Behavioural/include/Usage.h" 29 30 30 31 using namespace std; … … 46 47 // Parameters 47 48 protected : const string _name; 49 protected : const Parameters * _param; 50 private : const Tusage_t _usage; 48 51 49 protected : const Parameters * _param;50 52 #ifdef STATISTICS 51 53 private : Statistics * _stat; … … 95 97 SC_HAS_PROCESS (RegisterFile_Monolithic); 96 98 #endif 97 98 public : RegisterFile_Monolithic(99 public : RegisterFile_Monolithic 100 ( 99 101 #ifdef SYSTEMC 100 sc_module_name name, 102 sc_module_name name 101 103 #else 102 string name, 104 string name 103 105 #endif 104 106 #ifdef STATISTICS 105 morpheo::behavioural::Parameters_Statistics * param_statistics, 107 ,morpheo::behavioural::Parameters_Statistics * param_statistics 106 108 #endif 107 Parameters * param ); 109 ,Parameters * param 110 ,morpheo::behavioural::Tusage_t usage=USE_ALL 111 ); 112 108 113 public : ~RegisterFile_Monolithic (void); 109 114 110 #ifdef SYSTEMC111 115 private : void allocation (void); 112 116 private : void deallocation (void); 113 117 118 #ifdef SYSTEMC 114 119 public : void transition (void); 115 120 //public : void genMoore (void) {/* empty */}; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Types.h
r53 r57 9 9 */ 10 10 11 #include " Common/include/Types.h"11 #include "Behavioural/include/Types.h" 12 12 13 13 namespace morpheo { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp
r55 r57 14 14 namespace registerfile_monolithic { 15 15 16 RegisterFile_Monolithic::RegisterFile_Monolithic ( 16 RegisterFile_Monolithic::RegisterFile_Monolithic 17 ( 17 18 #ifdef SYSTEMC 18 19 sc_module_name name, 19 20 #else 20 21 string name , 21 22 #endif 22 23 #ifdef STATISTICS 23 24 morpheo::behavioural::Parameters_Statistics * param_statistics, 24 25 #endif 25 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param ): 26 _name (name), 27 _param (param) 26 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param, 27 morpheo::behavioural::Tusage_t usage 28 ): 29 _name (name), 30 _param (param), 31 _usage (usage) 28 32 { 29 33 log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","Begin"); 30 34 31 #ifdef SYSTEMC32 35 log_printf(INFO,RegisterFile_Monolithic,"RegisterFile_Monolithic","Allocation"); 33 34 36 allocation (); 35 #endif36 37 37 38 #ifdef STATISTICS … … 47 48 48 49 #ifdef SYSTEMC 49 SC_METHOD (transition); 50 dont_initialize (); 51 sensitive_pos << *(in_CLOCK); 50 if (_usage & USE_SYSTEMC) 51 { 52 SC_METHOD (transition); 53 dont_initialize (); 54 sensitive_pos << *(in_CLOCK); 55 56 SC_METHOD (genMealy_read); 57 dont_initialize (); 58 sensitive_neg << *(in_CLOCK); 59 for (uint32_t i=0; i<_param->_nb_port_read; i++) 60 sensitive << *(in_READ_VAL [i]) 61 << *(in_READ_ADDRESS [i]); 62 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 63 sensitive << *(in_READ_WRITE_VAL [i]) 64 << *(in_READ_WRITE_RW [i]) 65 << *(in_READ_WRITE_ADDRESS [i]); 66 67 # ifdef SYSTEMCASS_SPECIFIC 68 // List dependency information 69 for (uint32_t i=0; i<_param->_nb_port_read; i++) 70 { 71 (*(out_READ_DATA [i])) (*( in_READ_VAL [i])); 72 (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i])); 73 } 74 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 75 { 76 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i])); 77 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i])); 78 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i])); 79 } 80 # endif 81 82 for (uint32_t i=0; i<_param->_nb_port_read ; i++) 83 PORT_WRITE(out_READ_ACK [i], 1); 84 for (uint32_t i=0; i<_param->_nb_port_write ; i++) 85 PORT_WRITE(out_WRITE_ACK [i], 1); 86 for (uint32_t i=0; i<_param->_nb_port_read_write ; i++) 87 PORT_WRITE(out_READ_WRITE_ACK [i], 1); 88 } 89 #endif 52 90 53 SC_METHOD (genMealy_read);54 dont_initialize ();55 sensitive_neg << *(in_CLOCK);56 for (uint32_t i=0; i<_param->_nb_port_read; i++)57 sensitive << *(in_READ_VAL [i])58 << *(in_READ_ADDRESS [i]);59 for (uint32_t i=0; i<_param->_nb_port_read_write; i++)60 sensitive << *(in_READ_WRITE_VAL [i])61 << *(in_READ_WRITE_RW [i])62 << *(in_READ_WRITE_ADDRESS [i]);63 64 #ifdef SYSTEMCASS_SPECIFIC65 // List dependency information66 for (uint32_t i=0; i<_param->_nb_port_read; i++)67 {68 (*(out_READ_DATA [i])) (*( in_READ_VAL [i]));69 (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i]));70 }71 for (uint32_t i=0; i<_param->_nb_port_read_write; i++)72 {73 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i]));74 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i]));75 (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i]));76 }77 #endif78 79 for (uint32_t i=0; i<_param->_nb_port_read ; i++)80 PORT_WRITE(out_READ_ACK [i], 1);81 for (uint32_t i=0; i<_param->_nb_port_write ; i++)82 PORT_WRITE(out_WRITE_ACK [i], 1);83 for (uint32_t i=0; i<_param->_nb_port_read_write ; i++)84 PORT_WRITE(out_READ_WRITE_ACK [i], 1);85 #endif86 87 91 log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","End"); 88 92 }; … … 95 99 #endif 96 100 97 #ifdef SYSTEMC98 101 deallocation (); 99 #endif100 102 }; 101 103 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
r55 r57 1 #ifdef SYSTEMC2 1 /* 3 2 * $Id$ … … 17 16 void RegisterFile_Monolithic::allocation (void) 18 17 { 19 _component = new Component ( );18 _component = new Component (_usage); 20 19 21 20 Entity * entity = _component->set_entity (_name … … 133 132 }; // end namespace behavioural 134 133 }; // end namespace morpheo 135 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp
r55 r57 1 #ifdef SYSTEMC2 1 /* 3 2 * $Id$ … … 19 18 delete _component; 20 19 21 delete in_CLOCK; 22 delete in_NRESET; 23 // ----- Interface Read 24 delete [] in_READ_VAL ; 25 delete [] out_READ_ACK ; 26 delete [] in_READ_ADDRESS; 27 delete [] out_READ_DATA ; 28 29 // ----- Interface Write 30 delete [] in_WRITE_VAL ; 31 delete [] out_WRITE_ACK ; 32 delete [] in_WRITE_ADDRESS; 33 delete [] in_WRITE_DATA ; 34 35 // ----- Interface Read_Write 36 delete [] in_READ_WRITE_VAL ; 37 delete [] out_READ_WRITE_ACK ; 38 delete [] in_READ_WRITE_RW ; 39 delete [] in_READ_WRITE_ADDRESS; 40 delete [] in_READ_WRITE_WDATA ; 41 delete [] out_READ_WRITE_RDATA ; 42 43 // ----- Register 44 delete [] reg_DATA; 20 if (_usage & USE_SYSTEMC) 21 { 22 delete in_CLOCK; 23 delete in_NRESET; 24 // ----- Interface Read 25 delete [] in_READ_VAL ; 26 delete [] out_READ_ACK ; 27 delete [] in_READ_ADDRESS; 28 delete [] out_READ_DATA ; 29 30 // ----- Interface Write 31 delete [] in_WRITE_VAL ; 32 delete [] out_WRITE_ACK ; 33 delete [] in_WRITE_ADDRESS; 34 delete [] in_WRITE_DATA ; 35 36 // ----- Interface Read_Write 37 delete [] in_READ_WRITE_VAL ; 38 delete [] out_READ_WRITE_ACK ; 39 delete [] in_READ_WRITE_RW ; 40 delete [] in_READ_WRITE_ADDRESS; 41 delete [] in_READ_WRITE_WDATA ; 42 delete [] out_READ_WRITE_RDATA ; 43 44 // ----- Register 45 delete [] reg_DATA; 46 } 45 47 }; 46 48 … … 50 52 }; // end namespace behavioural 51 53 }; // end namespace morpheo 52 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/Makefile.deps
r53 r57 13 13 include $(DIR_MORPHEO)/Behavioural/Makefile.deps 14 14 endif 15 ifndef RegisterFile_Monolithic 16 include $(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/Makefile.deps 17 endif 18 ifndef Select_Priority_Fixed 19 include $(DIR_MORPHEO)/Behavioural/Generic/Select/Select_Priority_Fixed/Makefile.deps 20 endif 15 21 16 22 #-----[ Library ]------------------------------------------ 17 RegisterFile_Multi_Banked_LIBRARY = -lRegisterFile_Multi_Banked \ 18 $(Behavioural_LIBRARY) 23 RegisterFile_Multi_Banked_LIBRARY = -lRegisterFile_Multi_Banked \ 24 $(Behavioural_LIBRARY) \ 25 $(RegisterFile_Monolithic_LIBRARY) \ 26 $(Select_Priority_Fixed_LIBRARY) 19 27 20 28 RegisterFile_Multi_Banked_DIR_LIBRARY = -L$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/lib \ 21 $(Behavioural_DIR_LIBRARY) 29 $(Behavioural_DIR_LIBRARY) \ 30 $(RegisterFile_Monolithic_DIR_LIBRARY) \ 31 $(Select_Priority_Fixed_DIR_LIBRARY) 22 32 23 33 #-----[ Rules ]-------------------------------------------- … … 25 35 RegisterFile_Multi_Banked_library : 26 36 @\ 27 $(MAKE) Behavioural_library; \ 37 $(MAKE) Behavioural_library; \ 38 $(MAKE) RegisterFile_Monolithic_library; \ 39 $(MAKE) Select_Priority_Fixed_library; \ 28 40 $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked --makefile=Makefile; 29 41 30 42 RegisterFile_Multi_Banked_library_clean : 31 43 @\ 32 $(MAKE) Behavioural_library_clean; \ 44 $(MAKE) Behavioural_library_clean; \ 45 $(MAKE) RegisterFile_Monolithic_library_clean; \ 46 $(MAKE) Select_Priority_Fixed_library_clean; \ 33 47 $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked --makefile=Makefile clean; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp
r53 r57 7 7 */ 8 8 9 #define NB_ITERATION 1 02410 #define CYCLE_MAX ( 512*NB_ITERATION)9 #define NB_ITERATION 1 10 #define CYCLE_MAX (10240*NB_ITERATION) 11 11 12 12 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h" … … 34 34 cout << "<" << name << "> : Simulation SystemC" << endl; 35 35 36 37 #ifdef STATISTICS 38 morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); 39 #endif 40 36 41 RegisterFile_Multi_Banked * _RegisterFile_Multi_Banked = new RegisterFile_Multi_Banked (name.c_str(), 37 42 #ifdef STATISTICS 38 morpheo::behavioural::Parameters_Statistics(5,50),43 _param_stat, 39 44 #endif 40 *_param);45 _param); 41 46 42 47 #ifdef SYSTEMC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h
r53 r57 73 73 // A lot of table to the partial crossbar 74 74 public : uint32_t * _link_port_read_to_bank_read ; 75 // 75 //public : uint32_t * _link_port_read_to_num_bank ; 76 76 public : uint32_t * _link_port_write_to_bank_write; 77 // 77 //public : uint32_t * _link_port_write_to_num_bank ; 78 78 79 79 //-----[ methods ]----------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h
r53 r57 43 43 // -----[ fields ]---------------------------------------------------- 44 44 // Parameters 45 protected : const string _name;45 protected : const string _name; 46 46 47 protected : const Parameters _param;47 protected : const Parameters * _param; 48 48 //#ifdef STATISTICS 49 49 // protected : const morpheo::behavioural::Parameters_Statistics _param_statistics; … … 98 98 public : RegisterFile_Multi_Banked ( 99 99 #ifdef SYSTEMC 100 sc_module_name name,100 sc_module_name name, 101 101 #else 102 string name,102 string name, 103 103 #endif 104 104 #ifdef STATISTICS 105 morpheo::behavioural::Parameters_Statistics param_statistics,105 morpheo::behavioural::Parameters_Statistics * param_statistics, 106 106 #endif 107 Parameters param );107 Parameters * param ); 108 108 109 public : RegisterFile_Multi_Banked (Parameters param );110 109 public : ~RegisterFile_Multi_Banked (void); 111 110 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Statistics.h
r53 r57 28 28 { 29 29 // -----[ fields ]---------------------------------------------------- 30 private : const Parameters 30 private : const Parameters * _parameters; 31 31 32 32 // -----[ methods ]--------------------------------------------------- 33 public : Statistics (string name ,34 morpheo::behavioural::Parameters_Statistics parameters_statistics ,35 Parameters parameters33 public : Statistics (string name , 34 morpheo::behavioural::Parameters_Statistics * parameters_statistics , 35 Parameters * parameters 36 36 ); 37 37 //public : Statistics (Statistics & stat); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Types.h
r53 r57 9 9 */ 10 10 11 #include " Common/include/Types.h"11 #include "Behavioural/include/Types.h" 12 12 13 13 namespace morpheo { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp
r53 r57 53 53 54 54 _link_port_read_to_bank_read = new uint32_t [_nb_port_read ]; 55 // _link_port_read_to_num_bank = new uint32_t [_nb_port_read ];56 55 _link_port_write_to_bank_write = new uint32_t [_nb_port_write]; 57 // _link_port_write_to_num_bank = new uint32_t [_nb_port_write];58 56 59 // uint32_t _nb_port_bank_by_bank_read_port [_nb_port_read_by_bank ];60 // uint32_t _nb_port_bank_by_bank_write_port [_nb_port_write_by_bank];61 62 57 // init 63 // for (uint32_t i=0; i<_nb_port_read_by_bank ;i++) 64 // _nb_port_bank_by_bank_read_port [i] = 0; 65 66 for (uint32_t i=0; i<_nb_port_read ;i++) 58 for (uint32_t i=0; i<_nb_port_read ;i++) 67 59 { 68 60 uint32_t x = i%_nb_port_read_by_bank; 69 61 _link_port_read_to_bank_read [i] = x; 70 // _link_port_read_to_num_bank [i] = _nb_port_bank_by_bank_read_port [x];71 // _nb_port_bank_by_bank_read_port [x] ++;72 62 } 73 74 // init 75 // for (uint32_t i=0; i<_nb_port_write_by_bank ;i++) 76 // _nb_port_bank_by_bank_write_port [i] = 0; 77 78 for (uint32_t i=0; i<_nb_port_write ;i++) 63 for (uint32_t i=0; i<_nb_port_write;i++) 79 64 { 80 65 uint32_t x = i%_nb_port_write_by_bank; 81 66 _link_port_write_to_bank_write [i] = x; 82 // _link_port_write_to_num_bank [i] = _nb_port_bank_by_bank_write_port [x];83 // _nb_port_bank_by_bank_write_port [x] ++;84 67 } 85 68 … … 87 70 log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_bank_read"); 88 71 for (uint32_t i=0; i<_nb_port_read ;i++) 72 { 89 73 log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Read in [%d] to out [%d]",i,_link_port_read_to_bank_read [i]); 90 // log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_num_bank "); 91 // for (uint32_t i=0; i<_nb_port_read ;i++) 92 // log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Read in [%d] to bank [%d]",i,_link_port_read_to_num_bank [i]); 93 74 printf(" * Read in [%d] to out [%d]\n",i,_link_port_read_to_bank_read [i]); 75 } 94 76 log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_bank_write"); 95 77 for (uint32_t i=0; i<_nb_port_write ;i++) 96 log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to out [%d]",i,_link_port_write_to_bank_write [i]);97 // log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_num_bank ");98 // for (uint32_t i=0; i<_nb_port_write ;i++) 99 // log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to bank [%d]",i,_link_port_write_to_num_bank [i]); 78 { 79 log_printf(NONE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to out [%d]",i,_link_port_write_to_bank_write [i]); 80 printf(" * Write in [%d] to out [%d]\n",i,_link_port_write_to_bank_write [i]); 81 } 100 82 } 101 83 // else : don't allocate -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp
r53 r57 21 21 #endif 22 22 #ifdef STATISTICS 23 morpheo::behavioural::Parameters_Statistics 23 morpheo::behavioural::Parameters_Statistics * param_statistics, 24 24 #endif 25 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters param ):25 morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param ): 26 26 _name (name) 27 27 ,_param (param) … … 56 56 #ifdef SYSTEMC 57 57 // Function pointer 58 if (_param ._crossbar == FULL_CROSSBAR)58 if (_param->_crossbar == FULL_CROSSBAR) 59 59 { 60 60 function_transition = &morpheo::behavioural::generic::registerfile::registerfile_multi_banked::RegisterFile_Multi_Banked:: full_crossbar_transition; … … 84 84 dont_initialize (); 85 85 sensitive_neg << *(in_CLOCK); 86 for (uint32_t i=0; i<_param ._nb_port_read; i++)86 for (uint32_t i=0; i<_param->_nb_port_read; i++) 87 87 sensitive << *( in_READ_VAL [i]) 88 88 << *( in_READ_ADDRESS [i]); … … 90 90 #ifdef SYSTEMCASS_SPECIFIC 91 91 // List dependency information 92 for (uint32_t i=0; i<_param ._nb_port_read; i++)92 for (uint32_t i=0; i<_param->_nb_port_read; i++) 93 93 { 94 94 (*(out_READ_ACK [i])) (*( in_READ_VAL [i])); … … 97 97 (*(out_READ_DATA [i])) (*( in_READ_ADDRESS [i])); 98 98 } 99 // for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 100 // { 101 // (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_VAL [i])); 102 // (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_RW [i])); 103 // (*(out_READ_WRITE_RDATA [i])) (*( in_READ_WRITE_ADDRESS [i])); 104 // } 99 105 #endif 100 106 … … 102 108 dont_initialize (); 103 109 sensitive_neg << *(in_CLOCK); 104 for (uint32_t i=0; i<_param ._nb_port_write; i++)110 for (uint32_t i=0; i<_param->_nb_port_write; i++) 105 111 sensitive << *( in_WRITE_VAL [i]) 106 112 << *( in_WRITE_ADDRESS [i]) … … 109 115 #ifdef SYSTEMCASS_SPECIFIC 110 116 // List dependency information 111 for (uint32_t i=0; i<_param ._nb_port_write; i++)117 for (uint32_t i=0; i<_param->_nb_port_write; i++) 112 118 { 113 119 (*(out_WRITE_ACK [i])) (*( in_WRITE_VAL [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_address_xxx.cpp
r53 r57 20 20 log_printf(FUNC,RegisterFile_Multi_Banked,"address_bank","Begin"); 21 21 22 Taddress_t _return = _param ._bank_mask & (address >> _param._bank_shift);22 Taddress_t _return = _param->_bank_mask & (address >> _param->_bank_shift); 23 23 24 24 log_printf(FUNC,RegisterFile_Multi_Banked,"address_bank","End"); … … 31 31 log_printf(FUNC,RegisterFile_Multi_Banked,"address_num_reg","Begin"); 32 32 33 Taddress_t _return = _param ._num_reg_mask & (address >> _param._num_reg_shift);33 Taddress_t _return = _param->_num_reg_mask & (address >> _param->_num_reg_shift); 34 34 35 35 log_printf(FUNC,RegisterFile_Multi_Banked,"address_num_reg","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp
r53 r57 48 48 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 49 50 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param ._nb_port_read];51 out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param ._nb_port_read];52 in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param ._nb_port_read];53 out_READ_DATA = new SC_OUT(Tdata_t ) * [_param ._nb_port_read];50 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; 51 out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; 52 in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; 53 out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; 54 54 55 for (uint32_t i=0; i<_param ._nb_port_read; i++)55 for (uint32_t i=0; i<_param->_nb_port_read; i++) 56 56 { 57 57 Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) … … 65 65 in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 66 66 out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 67 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param ._nb_word)));68 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param ._size_word);67 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); 68 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word); 69 69 } 70 70 71 71 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 72 72 73 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param ._nb_port_write];74 out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param ._nb_port_write];75 in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param ._nb_port_write];76 in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param ._nb_port_write];73 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; 74 out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; 75 in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; 76 in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; 77 77 78 for (uint32_t i=0; i<_param ._nb_port_write; i++)78 for (uint32_t i=0; i<_param->_nb_port_write; i++) 79 79 { 80 80 Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) … … 88 88 in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 89 89 out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 90 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param ._nb_word)));91 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param ._size_word);90 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); 91 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word); 92 92 } 93 93 94 94 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 95 95 96 reg_DATA = new SC_REGISTER (Tdata_t) ** [_param ._nb_bank];96 reg_DATA = new SC_REGISTER (Tdata_t) ** [_param->_nb_bank]; 97 97 98 for (uint32_t i=0; i<_param ._nb_bank; i++)98 for (uint32_t i=0; i<_param->_nb_bank; i++) 99 99 { 100 reg_DATA [i] = new SC_REGISTER (Tdata_t) * [_param ._nb_word];100 reg_DATA [i] = new SC_REGISTER (Tdata_t) * [_param->_nb_word]; 101 101 102 for (uint32_t j=0; j<_param ._nb_word; j++)102 for (uint32_t j=0; j<_param->_nb_word; j++) 103 103 { 104 104 string rename = "reg_DATA_" + toString(i) + "_" + toString(j); … … 108 108 109 109 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 internal_WRITE_VAL = new bool [_param ._nb_port_write];111 internal_WRITE_BANK = new Taddress_t [_param ._nb_port_write];112 internal_WRITE_NUM_REG = new Taddress_t [_param ._nb_port_write];110 internal_WRITE_VAL = new bool [_param->_nb_port_write]; 111 internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; 112 internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; 113 113 114 114 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp
r53 r57 21 21 log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","Begin"); 22 22 23 bool read_port_use [_param ._nb_bank][_param._nb_port_read_by_bank];23 bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; 24 24 25 for (uint32_t i=0; i<_param ._nb_bank; i++)26 for (uint32_t j=0; j<_param ._nb_port_read_by_bank; j++)25 for (uint32_t i=0; i<_param->_nb_bank; i++) 26 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 27 27 read_port_use [i][j]=false; 28 28 29 for (uint32_t i=0; i<_param ._nb_port_read; i++)29 for (uint32_t i=0; i<_param->_nb_port_read; i++) 30 30 { 31 31 bool val = PORT_READ(in_READ_VAL [i]); … … 43 43 44 44 // Search loop 45 for (uint32_t j=0; j<_param ._nb_port_read_by_bank; j++)45 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 46 46 { 47 47 // find a unbusy port on this bank -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp
r53 r57 21 21 log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","Begin"); 22 22 23 bool write_port_use [_param ._nb_bank][_param._nb_port_write_by_bank];23 bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; 24 24 25 for (uint32_t i=0; i<_param ._nb_bank; i++)26 for (uint32_t j=0; j<_param ._nb_port_write_by_bank; j++)25 for (uint32_t i=0; i<_param->_nb_bank; i++) 26 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 27 27 write_port_use [i][j]=false; 28 28 29 for (uint32_t i=0; i<_param ._nb_port_write; i++)29 for (uint32_t i=0; i<_param->_nb_port_write; i++) 30 30 { 31 31 bool val = PORT_READ(in_WRITE_VAL [i]); … … 44 44 45 45 // Search loop 46 for (uint32_t j=0; j<_param ._nb_port_write_by_bank; j++)46 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 47 47 { 48 48 // find a unbusy port on this bank -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp
r53 r57 21 21 log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","Begin"); 22 22 23 bool read_port_use [_param ._nb_bank][_param._nb_port_read_by_bank];23 bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; 24 24 25 for (uint32_t i=0; i<_param ._nb_bank; i++)26 for (uint32_t j=0; j<_param ._nb_port_read_by_bank; j++)25 for (uint32_t i=0; i<_param->_nb_bank; i++) 26 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 27 27 read_port_use [i][j]=false; 28 28 29 for (uint32_t i=0; i<_param ._nb_port_read; i++)29 for (uint32_t i=0; i<_param->_nb_port_read; i++) 30 30 { 31 31 bool val = PORT_READ(in_READ_VAL [i]); … … 43 43 44 44 // // Search loop 45 // for (uint32_t j=0; j<_param ._nb_port_read_by_bank; j++)45 // for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 46 46 // { 47 47 48 uint32_t j = _param ._link_port_read_to_bank_read [i];48 uint32_t j = _param->_link_port_read_to_bank_read [i]; 49 49 50 50 // find a unbusy port on this bank -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp
r53 r57 21 21 log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","Begin"); 22 22 23 bool write_port_use [_param ._nb_bank][_param._nb_port_write_by_bank];24 for (uint32_t i=0; i<_param ._nb_bank; i++)25 for (uint32_t j=0; j<_param ._nb_port_write_by_bank; j++)23 bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; 24 for (uint32_t i=0; i<_param->_nb_bank; i++) 25 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 26 26 write_port_use [i][j]=false; 27 27 28 for (uint32_t i=0; i<_param ._nb_port_write; i++)28 for (uint32_t i=0; i<_param->_nb_port_write; i++) 29 29 { 30 30 bool val = PORT_READ(in_WRITE_VAL [i]); … … 43 43 44 44 // // Search loop 45 // for (uint32_t j=0; j<_param ._nb_port_write_by_bank; j++)45 // for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 46 46 // { 47 uint32_t j = _param ._link_port_write_to_bank_write [i];47 uint32_t j = _param->_link_port_write_to_bank_write [i]; 48 48 49 49 // find a unbusy port on this bank -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp
r53 r57 24 24 // (this->*function_transition) (); 25 25 26 for (uint32_t i=0; i<_param ._nb_port_write; i++)26 for (uint32_t i=0; i<_param->_nb_port_write; i++) 27 27 { 28 28 if (internal_WRITE_VAL [i] == 1) … … 34 34 } 35 35 } 36 37 38 36 39 37 #ifdef STATISTICS -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl.cpp
r53 r57 8 8 9 9 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" 10 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" 11 #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" 10 12 #include "Behavioural/include/Vhdl.h" 11 13 … … 16 18 namespace registerfile_multi_banked { 17 19 18 19 20 void RegisterFile_Multi_Banked::vhdl (void) 20 21 { 21 22 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl","Begin"); 22 23 24 //=================================== 25 //===== Component ===== 26 //=================================== 27 28 //----- RegisterFile_Monolithic ----- 29 30 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * param_bank; 31 morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic * bank; 32 33 // Create all bank. All bank is identical 34 param_bank = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters 35 (_param->_nb_port_read_by_bank 36 ,_param->_nb_port_write_by_bank 37 ,0 // mixte port 38 ,_param->_nb_word/_param->_nb_bank 39 ,_param->_size_word); 40 41 string bank_name = _name + "_bank"; 42 bank = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic 43 (bank_name.c_str() 44 #ifdef STATISTICS 45 ,NULL 46 #endif 47 ,param_bank 48 ,USE_VHDL); 49 50 _component->set_component(bank->_component 51 #ifdef POSITION 52 , 0, 0, 0, 0 53 #endif 54 , INSTANCE_LIBRARY 55 ); 56 57 58 //----- Select_Priority_Fixed ----- 59 60 // Create all select_unit : 61 // * 4 units : to the read port, "quotient" ports and "rest" ports. Idem to the write port. 62 // * for a FULL_CROSSBAR, there are no "rest" ports 63 uint32_t nb_select_port_1 ; 64 uint32_t nb_select_port_2 ; 65 uint32_t nb_select_port_3 ; 66 uint32_t nb_select_port_4 ; 67 68 if (_param->_crossbar == FULL_CROSSBAR) 69 { 70 nb_select_port_1 = _param->_nb_port_read ; 71 nb_select_port_3 = _param->_nb_port_write; 72 nb_select_port_2 = nb_select_port_4 = 0; 73 } 74 else 75 { 76 nb_select_port_2=(_param->_nb_port_read )/_param->_nb_port_read_by_bank; 77 nb_select_port_1=((_param->_nb_port_read%_param->_nb_port_read_by_bank)==0)?0:(nb_select_port_2+1); 78 nb_select_port_4=(_param->_nb_port_write )/_param->_nb_port_write_by_bank; 79 nb_select_port_3=((_param->_nb_port_write%_param->_nb_port_write_by_bank)==0)?0:(nb_select_port_4+1); 80 } 81 82 // cout << "nb_select_port_1 : " << nb_select_port_1 << endl; 83 // cout << "nb_select_port_2 : " << nb_select_port_2 << endl; 84 // cout << "nb_select_port_3 : " << nb_select_port_3 << endl; 85 // cout << "nb_select_port_4 : " << nb_select_port_4 << endl; 86 87 morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select1 = NULL; 88 morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select2 = NULL; 89 morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select3 = NULL; 90 morpheo::behavioural::generic::select::select_priority_fixed::Parameters *param_select4 = NULL; 91 92 morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select1 = NULL; 93 morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select2 = NULL; 94 morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select3 = NULL; 95 morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed *select4 = NULL; 96 97 bool have_select1 = ((nb_select_port_1 != 0 )); 98 bool have_select2 = ((nb_select_port_2 != 0 ) and 99 (nb_select_port_2 != nb_select_port_1)); 100 bool have_select3 = ((nb_select_port_3 != 0 ) and 101 (nb_select_port_3 != nb_select_port_2) and 102 (nb_select_port_3 != nb_select_port_1)); 103 bool have_select4 = ((nb_select_port_4 != 0 ) and 104 (nb_select_port_4 != nb_select_port_3) and 105 (nb_select_port_4 != nb_select_port_2) and 106 (nb_select_port_4 != nb_select_port_1) ); 107 108 string select_name1; 109 string select_name2; 110 string select_name3; 111 string select_name4; 112 113 if (have_select1) 114 { 115 select_name1 = _name+"_select_"+toString(nb_select_port_1)+"_ports"; 116 param_select1 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_1,true, false); 117 select1 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed 118 (select_name1.c_str() 119 #ifdef STATISTICS 120 ,NULL 121 #endif 122 ,param_select1 123 ,USE_VHDL); 124 125 _component->set_component(select1->_component 126 #ifdef POSITION 127 , 0, 0, 0, 0 128 #endif 129 , INSTANCE_LIBRARY 130 ); 131 } 132 133 if (have_select2) 134 { 135 select_name2 = _name+"_select_"+toString(nb_select_port_2)+"_ports"; 136 137 param_select2 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_2,true, false); 138 select2 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed 139 (select_name2.c_str() 140 #ifdef STATISTICS 141 ,NULL 142 #endif 143 ,param_select2 144 ,USE_VHDL); 145 146 _component->set_component(select2->_component 147 #ifdef POSITION 148 , 0, 0, 0, 0 149 #endif 150 , INSTANCE_LIBRARY 151 ); 152 } 153 154 if (have_select3) 155 { 156 select_name3 = _name+"_select_"+toString(nb_select_port_3)+"_ports"; 157 158 param_select3 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_3,true, false); 159 select3 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed 160 (select_name3.c_str() 161 #ifdef STATISTICS 162 ,NULL 163 #endif 164 ,param_select3 165 ,USE_VHDL); 166 167 _component->set_component(select3->_component 168 #ifdef POSITION 169 , 0, 0, 0, 0 170 #endif 171 , INSTANCE_LIBRARY 172 ); 173 } 174 175 if (have_select4) 176 { 177 select_name4 = _name+"_select_"+toString(nb_select_port_4)+"_ports"; 178 179 param_select4 = new morpheo::behavioural::generic::select::select_priority_fixed::Parameters (nb_select_port_4,true, false); 180 select4 = new morpheo::behavioural::generic::select::select_priority_fixed::Select_Priority_Fixed 181 (select_name4.c_str() 182 #ifdef STATISTICS 183 ,NULL 184 #endif 185 ,param_select4 186 ,USE_VHDL); 187 188 _component->set_component(select4->_component 189 #ifdef POSITION 190 , 0, 0, 0, 0 191 #endif 192 , INSTANCE_LIBRARY 193 ); 194 } 195 23 196 Vhdl * vhdl = new Vhdl (_name); 24 197 … … 32 205 33 206 delete vhdl; 207 delete bank; 208 delete param_bank; 209 if (have_select1) 210 { 211 delete select1; 212 delete param_select1; 213 } 214 if (have_select2) 215 { 216 delete select2; 217 delete param_select2; 218 } 219 if (have_select3) 220 { 221 delete select3; 222 delete param_select3; 223 } 224 if (have_select4) 225 { 226 delete select4; 227 delete param_select4; 228 } 34 229 35 230 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl","End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_body.cpp
r53 r57 20 20 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","Begin"); 21 21 22 uint32_t read_select_limit ; 23 uint32_t read_nb_select1 ; 24 uint32_t read_nb_select2 ; 25 uint32_t write_select_limit; 26 uint32_t write_nb_select1 ; 27 uint32_t write_nb_select2 ; 28 29 read_select_limit = _param->_nb_port_read%_param->_nb_port_read_by_bank; 30 read_nb_select2 = _param->_nb_port_read/_param->_nb_port_read_by_bank; 31 read_nb_select1 = (read_select_limit==0)?0:(read_nb_select2+1); 32 33 write_select_limit= _param->_nb_port_write%_param->_nb_port_write_by_bank; 34 write_nb_select2 = _param->_nb_port_write/_param->_nb_port_write_by_bank; 35 write_nb_select1 = (write_select_limit==0)?0:(write_nb_select2+1); 36 37 vhdl->set_body(""); 38 vhdl->set_body("-----------------------------------"); 39 vhdl->set_body("-- Instance bank "); 40 vhdl->set_body("-----------------------------------"); 41 vhdl->set_body(""); 42 43 for (uint32_t i=0; i<_param->_nb_bank; i++) 44 { 45 vhdl->set_body(_name+"_bank_"+toString(i)+" : "+_name+"_bank"); 46 vhdl->set_body("port map ("); 47 vhdl->set_body("\t in_CLOCK \t=>\tin_CLOCK "); 48 vhdl->set_body("\t, in_NRESET\t=>\tin_NRESET"); 49 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 50 { 51 vhdl->set_body("\t, in_READ_"+toString(j)+"_VAL \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL"); 52 vhdl->set_body("\t,out_READ_"+toString(j)+"_ACK \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK"); 53 vhdl->set_body("\t, in_READ_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS"); 54 vhdl->set_body("\t,out_READ_"+toString(j)+"_DATA \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"); 55 } 56 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 57 { 58 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_VAL \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"); 59 vhdl->set_body("\t,out_WRITE_"+toString(j)+"_ACK \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK"); 60 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS"); 61 vhdl->set_body("\t, in_WRITE_"+toString(j)+"_DATA \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA"); 62 } 63 64 vhdl->set_body(");"); 65 vhdl->set_body(""); 66 } 67 68 vhdl->set_body(""); 69 vhdl->set_body("-----------------------------------"); 70 vhdl->set_body("-- Instance select"); 71 vhdl->set_body("-- (1 select by port)"); 72 vhdl->set_body("-----------------------------------"); 73 vhdl->set_body(""); 74 for (uint32_t i=0; i<_param->_nb_bank; i++) 75 { 76 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 77 { 78 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 79 80 vhdl->set_body(_name+"_read_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); 81 vhdl->set_body("port map ("); 82 for (uint32_t k=0; k<nb_port; k++) 83 { 84 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 85 string separator = ((k==0)?" ":","); 86 87 vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 88 vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 89 } 90 vhdl->set_body(");"); 91 vhdl->set_body(""); 92 } 93 94 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 95 { 96 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 97 98 vhdl->set_body(_name+"_write_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); 99 vhdl->set_body("port map ("); 100 for (uint32_t k=0; k<nb_port; k++) 101 { 102 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 103 string separator = ((k==0)?" ":","); 104 105 vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 106 vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 107 } 108 vhdl->set_body(");"); 109 vhdl->set_body(""); 110 } 111 } 112 113 vhdl->set_body(""); 114 vhdl->set_body("-----------------------------------"); 115 vhdl->set_body("-- Bank Val"); 116 vhdl->set_body("-----------------------------------"); 117 vhdl->set_body(""); 118 for (uint32_t i=0; i<_param->_nb_bank; i++) 119 { 120 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 121 { 122 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 123 124 vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); 125 for (uint32_t k=0; k<nb_port; k++) 126 { 127 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 128 129 vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+"_VAL"); 130 } 131 vhdl->set_body(";"); 132 } 133 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 134 { 135 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 136 137 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); 138 for (uint32_t k=0; k<nb_port; k++) 139 { 140 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 141 142 vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL"); 143 } 144 vhdl->set_body(";"); 145 } 146 } 147 148 vhdl->set_body(""); 149 vhdl->set_body("-----------------------------------"); 150 vhdl->set_body("-- Bank Address"); 151 vhdl->set_body("-----------------------------------"); 152 vhdl->set_body(""); 153 for (uint32_t i=0; i<_param->_nb_bank; i++) 154 { 155 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) 156 { 157 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); 158 159 vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); 160 for (uint32_t k=1; k<nb_port; k++) 161 { 162 uint32_t num_port = _param->_nb_port_read_by_bank*k+j; 163 164 vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_READ_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 165 } 166 vhdl->set_body("\tin_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); 167 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 168 } 169 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 170 { 171 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 172 173 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); 174 for (uint32_t k=1; k<nb_port; k++) 175 { 176 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 177 178 vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 179 } 180 vhdl->set_body("\tin_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); 181 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 182 } 183 } 184 185 vhdl->set_body(""); 186 vhdl->set_body("-----------------------------------"); 187 vhdl->set_body("-- Bank Data"); 188 vhdl->set_body("-----------------------------------"); 189 vhdl->set_body(""); 190 for (uint32_t i=0; i<_param->_nb_bank; i++) 191 { 192 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) 193 { 194 uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); 195 196 vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_DATA <="); 197 for (uint32_t k=1; k<nb_port; k++) 198 { 199 uint32_t num_port = _param->_nb_port_write_by_bank*k+j; 200 201 vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_WRITE_"+toString(i)+"_"+toString(num_port)+"_VAL='1' else"); 202 } 203 vhdl->set_body("\tin_WRITE_"+toString(j)+"_DATA;"); 204 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 205 } 206 } 207 208 vhdl->set_body(""); 209 vhdl->set_body("-----------------------------------"); 210 vhdl->set_body("-- VAL (to Select)"); 211 vhdl->set_body("-----------------------------------"); 212 vhdl->set_body(""); 213 214 for (uint32_t i=0; i<_param->_nb_bank; i++) 215 { 216 for (uint32_t j=0; j<_param->_nb_port_read; j ++) 217 { 218 string address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); 219 220 vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_READ_"+toString(j)+"_VAL='1') "+address+"else '0';"); 221 } 222 for (uint32_t j=0; j<_param->_nb_port_write; j ++) 223 { 224 string address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+")"); 225 vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+address+" else '0';"); 226 } 227 } 228 229 vhdl->set_body(""); 230 vhdl->set_body("-----------------------------------"); 231 vhdl->set_body("-- OUTPUT"); 232 vhdl->set_body("-----------------------------------"); 233 vhdl->set_body(""); 234 235 if (_param->_crossbar == FULL_CROSSBAR) 236 { 237 for (uint32_t i=0; i<_param->_nb_port_read; i ++) 238 { 239 vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); 240 for (uint32_t j=0; j<_param->_nb_bank; j ++) 241 { 242 for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) 243 { 244 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 245 } 246 } 247 vhdl->set_body("\t'0';"); 248 vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); 249 for (uint32_t j=0; j<_param->_nb_bank; j ++) 250 { 251 for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) 252 { 253 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 254 } 255 } 256 vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 257 } 258 for (uint32_t i=0; i<_param->_nb_port_write; i ++) 259 { 260 vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); 261 for (uint32_t j=0; j<_param->_nb_bank; j ++) 262 { 263 for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k ++) 264 { 265 vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(k)+"_VAL = '1' else"); 266 } 267 } 268 vhdl->set_body("\t'0';"); 269 } 270 } 271 else 272 { 273 for (uint32_t i=0; i<_param->_nb_port_read; i ++) 274 { 275 uint32_t link = _param->_link_port_read_to_bank_read[i]; 276 277 vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); 278 for (uint32_t j=0; j<_param->_nb_bank; j ++) 279 { 280 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(link)+"_VAL = '1' else"); 281 } 282 // vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_ACK;"); 283 vhdl->set_body("\t'0';"); 284 285 vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); 286 for (uint32_t j=1; j<_param->_nb_bank; j ++) 287 { 288 vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); 289 } 290 vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_DATA;"); 291 // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); 292 } 293 for (uint32_t i=0; i<_param->_nb_port_write; i ++) 294 { 295 uint32_t link = _param->_link_port_write_to_bank_write[i]; 296 297 vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); 298 for (uint32_t j=0; j<_param->_nb_bank; j ++) 299 { 300 vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); 301 } 302 // vhdl->set_body("\tinternal_BANK_WRITE_"+toString(0)+"_"+toString(link)+"_ACK;"); 303 vhdl->set_body("\t'0';"); 304 } 305 } 306 22 307 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","End"); 23 308 }; … … 26 311 }; // end namespace registerfile 27 312 }; // end namespace generic 28 29 313 }; // end namespace behavioural 30 314 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp
r53 r57 20 20 log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","Begin"); 21 21 22 vhdl->set_type ("Tregfile", "array (" + toString(_param._nb_word_by_bank-1) + " downto 0) of " + std_logic(_param._size_word)); 22 for (uint32_t i=0; i<_param->_nb_bank; i++) 23 { 24 for (uint32_t j=0; j<_param->_nb_port_read; j ++) 25 { 26 vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 27 vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); 28 vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 23 29 24 vhdl->set_type ("Tbank" , "array (" + toString(_param._nb_bank) + " downto 0) of Tregfile"); 25 26 vhdl->set_signal ("reg_DATA", "Tbank"); 27 28 for (uint32_t i=0; i<_param._nb_bank; i++) 29 { 30 for (uint32_t j=0; j<_param._nb_port_read_by_bank; j ++) 30 } 31 for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j ++) 31 32 { 32 vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 33 vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_PORT" ,static_cast<uint32_t>(ceil(log2(_param._nb_port_read)))); 33 vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 34 vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); 35 vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); 36 vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); 34 37 } 35 for (uint32_t j=0; j<_param ._nb_port_write_by_bank; j ++)38 for (uint32_t j=0; j<_param->_nb_port_write; j ++) 36 39 { 37 40 vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 38 vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_PORT",static_cast<uint32_t>(ceil(log2(_param._nb_port_write)))); 41 vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); 42 vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 43 } 44 for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j ++) 45 { 46 vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); 47 vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); 48 vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); 49 vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); 39 50 } 40 51 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Statistics.cpp
r53 r57 17 17 18 18 Statistics::Statistics (string name , 19 morpheo::behavioural::Parameters_Statistics parameters_statistics ,20 Parameters parameters19 morpheo::behavioural::Parameters_Statistics * parameters_statistics , 20 Parameters * parameters 21 21 ) : 22 22 morpheo::behavioural::Statistics(name ,
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