Ignore:
Timestamp:
Mar 27, 2008, 11:04:49 AM (16 years ago)
Author:
rosiere
Message:

Add :

  • Execute_loop (must be test systemC)
  • Prediction
    • Direction : predifined scheme
    • Branch Target Buffer
  • iFetch_unit
    • ifetch_queue
    • pc management
  • Decod_unit
    • coming soon : support for custom operation
  • Rename_unit
    • RAT
    • Free_list
    • Dependence RAW check
    • Load store unit pointer
  • New Environnement (hierarchy_memory will remove in a next version)


Modif :

  • Manage Custom Operation
  • All component in execute_loop to use the new statistics management

Not Finish :

  • Return Address Stack
  • Environnement
Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp

    r71 r78  
    6969      case NO_SPECULATIVE_LOAD     :
    7070      case SPECULATIVE_LOAD_ACCESS :
    71       case SPECULATIVE_LOAD_BYPASS :
     71        //case SPECULATIVE_LOAD_BYPASS :
    7272      default                      :
    7373        {

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp

    r75 r78  
    7272   in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"    ,_param->_size_packet_id       );
    7373   in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
     74   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
    7475   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage
     76   if (_param->_have_port_load_queue_ptr)
    7577   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
    76 // in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
     78  in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
    7779   in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
    7880   in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
    7981   in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
    80 // in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
    81 //    in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
     82  in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
     83   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
    8284   in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
    83 // in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
    84 // in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
     85  in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
     86  in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
    8587    }
    8688
    … …  
    105107      if (_param->_have_port_packet_id)       
    106108      out_MEMORY_OUT_PACKET_ID     = interface->set_signal_out <Tpacket_t         > ("packet_id"     ,_param->_size_packet_id        );
     109//    out_MEMORY_OUT_OPERATION     = interface->set_signal_out <Toperation_t      > ("operation"     ,_param->_size_operation        );
     110      out_MEMORY_OUT_TYPE          = interface->set_signal_out <Ttype_t           > ("type"          ,_param->_size_type             );
    107111      out_MEMORY_OUT_WRITE_RD      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
    108112      out_MEMORY_OUT_NUM_REG_RD    = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"    ,_param->_size_general_register );
    109113      out_MEMORY_OUT_DATA_RD       = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"       ,_param->_size_general_data     );
    110 //    out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
    111 //    out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
    112 //    out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
     114      out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_re"      ,1                              );
     115      out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
     116      out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
    113117      out_MEMORY_OUT_EXCEPTION     = interface->set_signal_out <Texception_t      > ("exception"     ,_param->_size_exception        );
     118      out_MEMORY_OUT_NO_SEQUENCE   = interface->set_signal_out <Tcontrol_t        > ("no_sequence"   ,1                              );
     119      out_MEMORY_OUT_ADDRESS       = interface->set_signal_out <Tgeneral_data_t   > ("address"       ,_param->_size_general_data     );
    114120    }
    115121
    … …  
    153159    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    154160
    155     if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
     161//  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
    156162      {
    157         out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_size_load_queue];
     163        out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_nb_bypass_memory];
    158164        if (_param->_have_port_ooo_engine_id)   
    159         out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_size_load_queue];
    160         out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_size_load_queue];
    161         out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_size_load_queue];
     165        out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_nb_bypass_memory];
     166        out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory];
     167        out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_nb_bypass_memory];
    162168       
    163         for (uint32_t i=0; i<_param->_size_load_queue; i++)
     169        for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
    164170          {
    165171            Interface_fifo * interface = _interfaces->set_interface("memory_out"

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp

    r71 r78  
    4444    delete     in_MEMORY_IN_PACKET_ID   ;
    4545    delete     in_MEMORY_IN_OPERATION   ;
     46    delete     in_MEMORY_IN_TYPE        ;
    4647    delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
     48    if (_param->_have_port_load_queue_ptr)
    4749    delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
    48 //  delete     in_MEMORY_IN_HAS_IMMEDIAT;
     50    delete     in_MEMORY_IN_HAS_IMMEDIAT;
    4951    delete     in_MEMORY_IN_IMMEDIAT    ;
    5052    delete     in_MEMORY_IN_DATA_RA     ;
    5153    delete     in_MEMORY_IN_DATA_RB     ;
    52 //  delete     in_MEMORY_IN_DATA_RC     ;
    53 //  delete     in_MEMORY_IN_WRITE_RD    ;
     54    delete     in_MEMORY_IN_DATA_RC     ;
     55    delete     in_MEMORY_IN_WRITE_RD    ;
    5456    delete     in_MEMORY_IN_NUM_REG_RD  ;
    55 //  delete     in_MEMORY_IN_WRITE_RE    ;
    56 //  delete     in_MEMORY_IN_NUM_REG_RE  ;
     57    delete     in_MEMORY_IN_WRITE_RE    ;
     58    delete     in_MEMORY_IN_NUM_REG_RE  ;
    5759   
    5860    delete    out_MEMORY_OUT_VAL       ;
    … …  
    6668    if (_param->_have_port_packet_id)
    6769    delete    out_MEMORY_OUT_PACKET_ID ;
     70//  delete    out_MEMORY_OUT_OPERATION ;
     71    delete    out_MEMORY_OUT_TYPE      ;
    6872    delete    out_MEMORY_OUT_WRITE_RD  ;
    6973    delete    out_MEMORY_OUT_NUM_REG_RD;
    7074    delete    out_MEMORY_OUT_DATA_RD   ;
    71 //  delete    out_MEMORY_OUT_WRITE_RE  ;
    72 //  delete    out_MEMORY_OUT_NUM_REG_RE;
    73 //  delete    out_MEMORY_OUT_DATA_RE   ;
     75    delete    out_MEMORY_OUT_WRITE_RE  ;
     76    delete    out_MEMORY_OUT_NUM_REG_RE;
     77    delete    out_MEMORY_OUT_DATA_RE   ;
    7478    delete    out_MEMORY_OUT_EXCEPTION ;
     79    delete    out_MEMORY_OUT_NO_SEQUENCE;
     80    delete    out_MEMORY_OUT_ADDRESS   ;
    7581   
    7682    delete    out_DCACHE_REQ_VAL       ;
    … …  
    9197    delete     in_DCACHE_RSP_ERROR     ;
    9298   
    93     if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
    94       {
    95         delete [] out_BYPASS_MEMORY_VAL       ;
    96         if (_param->_have_port_ooo_engine_id)   
    97         delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
    98         delete [] out_BYPASS_MEMORY_NUM_REG   ;
    99         delete [] out_BYPASS_MEMORY_DATA      ;
    100       }
     99    delete [] out_BYPASS_MEMORY_VAL       ;
     100    if (_param->_have_port_ooo_engine_id)   
     101    delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
     102    delete [] out_BYPASS_MEMORY_NUM_REG   ;
     103    delete [] out_BYPASS_MEMORY_DATA      ;
    101104    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    102105

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

    r71 r78  
    120120    if (_param->_have_port_packet_id)
    121121    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    , memory_out_packet_id    );
     122//  PORT_WRITE(out_MEMORY_OUT_OPERATION    , memory_out_operation    );
     123    PORT_WRITE(out_MEMORY_OUT_TYPE         , TYPE_MEMORY             );
    122124    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     , memory_out_write_rd     );
    123125    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   , memory_out_num_reg_rd   );
    … …  
    126128//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , memory_out_num_reg_re   );
    127129//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      , memory_out_data_re      );
     130    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , 0);
     131    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , 0);
     132    PORT_WRITE(out_MEMORY_OUT_DATA_RE      , 0);
    128133    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    , memory_out_exception    );
    129 
     134    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  , 0);
     135    PORT_WRITE(out_MEMORY_OUT_ADDRESS      , 0);
    130136    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    131137

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp

    r75 r78  
    265265            //  others in speculation_access_queue
    266266
     267#ifdef DEBUG_TEST
     268            if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY)
     269              throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
     270#endif
    267271            Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
    268272            Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
    … …  
    376380                    _store_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID   );
    377381                    _store_queue [index]._operation            = operation;
    378                     _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
     382                    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
    379383                    _store_queue [index]._address              = address;
    380384
    … …  
    415419
    416420                _speculative_access_queue [index]._operation            = operation;
    417                 _speculative_access_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
     421                _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
    418422                _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
    419423                _speculative_access_queue [index]._address              = address;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp

    r77 r78  
    2525                          uint32_t            nb_port_check          ,
    2626                          Tspeculative_load_t speculative_load       ,
     27                          uint32_t            nb_bypass_memory       ,
    2728                          uint32_t            nb_context             ,
    2829                          uint32_t            nb_front_end           ,
    … …  
    3031                          uint32_t            nb_packet              ,
    3132                          uint32_t            size_general_data      ,
    32                           uint32_t            nb_general_register    ):
     33                          uint32_t            size_special_data      ,
     34                          uint32_t            nb_general_register    ,
     35                          uint32_t            nb_special_register    ):
    3336    _size_store_queue        (size_store_queue       ),
    3437    _size_load_queue         (size_load_queue        ),
    … …  
    3639    _nb_port_check           (nb_port_check          ),
    3740    _speculative_load        (speculative_load       ),
     41    _nb_bypass_memory        (nb_bypass_memory       ),
    3842    _nb_context              (nb_context             ),
    3943    _nb_front_end            (nb_front_end           ),
    … …  
    4145    _nb_packet               (nb_packet              ),
    4246    _size_general_data       (size_general_data      ),
     47    _size_special_data       (size_special_data      ),
    4348    _nb_general_register     (nb_general_register    ),
     49    _nb_special_register     (nb_special_register    ),
    4450   
    4551    _size_address_store_queue              (log2(size_store_queue             )),
    … …  
    5258    _size_packet_id          (log2(nb_packet          )),
    5359    _size_general_register   (log2(nb_general_register)),
     60    _size_special_register   (log2(nb_special_register)),
    5461    _size_dcache_context_id  (_size_context_id + _size_front_end_id + _size_ooo_engine_id),
    5562    _size_dcache_packet_id   ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1),
    … …  
    6067    _have_port_packet_id         (_size_packet_id    >0),
    6168    _have_port_dcache_context_id (_size_dcache_context_id>0),
     69    _have_port_load_queue_ptr    (_size_load_queue>1),
    6270
    6371    _mask_address_lsb            (gen_mask<Tdcache_address_t>(log2(size_general_data/8))),
    … …  
    7785    _nb_port_check           (param._nb_port_check          ),
    7886    _speculative_load        (param._speculative_load       ),
     87    _nb_bypass_memory        (param._nb_bypass_memory       ),
    7988    _nb_context              (param._nb_context             ),
    8089    _nb_front_end            (param._nb_front_end           ),
    … …  
    8291    _nb_packet               (param._nb_packet              ),
    8392    _size_general_data       (param._size_general_data      ),
     93    _size_special_data       (param._size_special_data      ),
    8494    _nb_general_register     (param._nb_general_register    ),
     95    _nb_special_register     (param._nb_special_register    ),
    8596
    8697    _size_address_store_queue              (param._size_address_store_queue             ),
    … …  
    93104    _size_packet_id          (param._size_packet_id         ),
    94105    _size_general_register   (param._size_general_register  ),
     106    _size_special_register   (param._size_special_register  ),
    95107    _size_dcache_context_id  (param._size_dcache_context_id ),
    96108    _size_dcache_packet_id   (param._size_dcache_packet_id  ),
    … …  
    100112    _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
    101113    _have_port_packet_id     (param._have_port_packet_id    ),
    102 
    103114    _have_port_dcache_context_id(param._have_port_dcache_context_id),
     115    _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
    104116
    105117    _mask_address_lsb        (param._mask_address_lsb),

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp

    r71 r78  
    2121#undef  FUNCTION
    2222#define FUNCTION "Load_store_unit::msg_error"
    23   std::string Parameters::msg_error(void)
     23  Parameters_test Parameters::msg_error(void)
    2424  {
    2525    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
    2626   
    27     std::string msg = "";
     27    Parameters_test test("Load_store_unit");
    2828
    2929    switch (_speculative_load)
    … …  
    3131      case SPECULATIVE_LOAD_COMMIT :
    3232        {
     33          if (not (_nb_bypass_memory == 0))
     34            test.error("Bypass memory is not supported. Please wait a next revision.");
     35 
    3336          break;
    3437        }
    3538      case NO_SPECULATIVE_LOAD     :
    3639      case SPECULATIVE_LOAD_ACCESS :
    37       case SPECULATIVE_LOAD_BYPASS :
     40      // case SPECULATIVE_LOAD_BYPASS :
    3841      default                      :
    3942        {
    40           msg += "  - Speculative load scheme is not supported : " +toString(_speculative_load);
     43          if (not (_nb_bypass_memory == 0))
     44            test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");
     45
     46          test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");
    4147          break;
    4248        }
    4349      }
    4450
    45     return msg;
     51    if (not (_size_store_queue >= 2))
     52      test.error("Store queue must have at less two slot.");
     53
     54    if (not (_nb_bypass_memory <= _size_load_queue))
     55      test.error("Bypass number must be less than load_queue's size.");
    4656
    4757    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
     58
     59    return test;
     60
    4861  };
    4962

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp

    r77 r78  
    3333    xml.singleton_begin("nb_port_check                "); xml.attribut("value",toString(_nb_port_check                )); xml.singleton_end();
    3434    xml.singleton_begin("speculative_load             "); xml.attribut("value",toString(_speculative_load             )); xml.singleton_end();
     35    xml.singleton_begin("nb_bypass_memory             "); xml.attribut("value",toString(_nb_bypass_memory             )); xml.singleton_end();
    3536    xml.singleton_begin("nb_context                   "); xml.attribut("value",toString(_nb_context                   )); xml.singleton_end();
    3637    xml.singleton_begin("nb_front_end                 "); xml.attribut("value",toString(_nb_front_end                 )); xml.singleton_end();
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