Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Documentation
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Documentation/Source
- Files:
-
- 19 added
- 1 deleted
- 8 edited
-
Documents/presentation-morpheo-microarchitecture (added)
-
Documents/presentation-morpheo-microarchitecture/common (added)
-
Documents/presentation-morpheo-microarchitecture/en (added)
-
Documents/presentation-morpheo-microarchitecture/en/root.tex (added)
-
Documents/presentation_bull (added)
-
Documents/presentation_bull/common (added)
-
Documents/presentation_bull/fr (added)
-
Documents/presentation_bull/fr/root.tex (added)
-
Include/doc-style.sty (modified) (1 diff)
-
Info/presentation-morpheo-microarchitecture.lang (added)
-
Info/presentation-morpheo-microarchitecture.sty (added)
-
Info/presentation-morpheo-microarchitecture.tex (added)
-
Info/presentation-morpheo-microarchitecture.type (added)
-
Info/presentation_bull.lang (added)
-
Info/presentation_bull.sty (added)
-
Info/presentation_bull.tex (added)
-
Info/presentation_bull.type (added)
-
Link (deleted)
-
Makefile (modified) (5 diffs)
-
Schema/MORPHEO_micro_architecture-ex01.fig (modified) (5 diffs)
-
Schema/MORPHEO_micro_architecture-ex02.fig (modified) (4 diffs)
-
Schema/MORPHEO_micro_architecture-ex03.fig (modified) (5 diffs)
-
Schema/MORPHEO_micro_architecture-ex04.fig (modified) (5 diffs)
-
Schema/MORPHEO_micro_architecture-overview.fig (modified) (4 diffs)
-
Schema/VHDL_methodologie.fig (modified) (2 diffs)
-
presentation-morpheo-microarchitecture-fr.dvi (added)
-
presentation-morpheo-microarchitecture-fr.pdf (added)
-
presentation-morpheo-microarchitecture-fr.ps (added)
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty
r82 r88 14 14 \usepackage[latin1]{inputenc} % Pour utiliser les caractères accentués dans votre texte 15 15 \usepackage{openbib} 16 \usepackage[draft]{fixme}16 %\usepackage[draft]{fixme} 17 17 \bibliographystyle{plain} 18 18 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile
r84 r88 32 32 DIR_SCHEMA_PNG = Schema_png 33 33 DIR_TEX = Source 34 DIR_LINK = Link35 34 36 35 #-------------------------------------------------------------------------------- … … 103 102 $(DVIPS) -o $@ $<; 104 103 105 #$(DIR_LINK)/%/*106 104 %.dvi : $(DIR_TEX)/%.tex 107 105 @\ … … 170 168 $(MKDIR) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG); \ 171 169 \ 172 $(ECHO) "Create link : $(DIR_LINK)/$$FILENAME-$(DEFAULT_LANG)"; \173 $(LINK_SYMBOLIC) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG) $(DIR_LINK)/$$FILENAME-$(DEFAULT_LANG); \174 \175 170 $(ECHO) "Create file : $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex"; \ 176 171 $(TOUCH) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex … … 224 219 \ 225 220 $(ECHO) "Delete directory : $(DIR_DOCUMENTS)/$$FILENAME"; \ 226 $(RM) $(DIR_DOCUMENTS)/$$FILENAME; \ 227 $(ECHO) "Delete link : $(DIR_DOCUMENTS)/$$FILENAME"; \ 228 $(RM) $(DIR_LINK)/$$FILENAME-*; 221 $(RM) $(DIR_DOCUMENTS)/$$FILENAME; 229 222 230 223 rename : … … 282 275 \ 283 276 $(ECHO) "Rename directory : $(DIR_DOCUMENTS)/$$FILENAME_SRC"; \ 284 $(MV) $(DIR_DOCUMENTS)/$$FILENAME_SRC $(DIR_DOCUMENTS)/$$FILENAME_DEST; \ 285 $(ECHO) "Rename link : manually please"; 277 $(MV) $(DIR_DOCUMENTS)/$$FILENAME_SRC $(DIR_DOCUMENTS)/$$FILENAME_DEST; 286 278 287 279 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig
r81 r88 12 12 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 13 13 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 14 -615 6 4770 3240 5490 369016 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 517 5490 3690 4770 3690 4770 3240 5490 3240 5490 369018 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\00119 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\00120 14 -6 21 15 6 5850 3690 6570 4140 … … 40 34 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 41 35 -6 42 6 6570 3015 7290 346543 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 544 7290 3465 6570 3465 6570 3015 7290 3015 7290 346545 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\00146 -647 36 6 3825 3060 4635 3510 48 37 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 … … 60 49 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 61 50 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 51 -6 52 6 4770 3240 5490 3690 53 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 54 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 55 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 56 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 62 57 -6 63 58 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 … … 168 163 3 0 1.00 60.00 120.00 169 164 3690 4050 4770 4050 165 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 166 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 170 167 4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 171 168 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 … … 178 175 4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 179 176 4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 177 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig
r81 r88 29 29 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 30 30 -6 31 6 6570 3015 7290 346532 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 533 7290 3465 6570 3465 6570 3015 7290 3015 7290 346534 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\00135 -636 31 6 4770 3285 5490 3735 37 32 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 … … 39 34 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3555 decod\001 40 35 -6 36 6 3825 2655 4635 3105 37 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 38 4590 3105 3870 3105 3870 2655 4590 2655 4590 3105 39 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\001 40 -6 41 6 2970 3285 3690 3735 42 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 43 3690 3735 2970 3735 2970 3285 3690 3285 3690 3735 44 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\001 45 -6 46 6 1890 3690 2610 4140 47 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 48 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 49 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 50 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 51 -6 41 52 6 4770 2835 5490 3285 42 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 553 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 43 54 5490 3285 4770 3285 4770 2835 5490 2835 5490 3285 44 55 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3015 context\001 45 56 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3195 state\001 46 -647 6 3825 2655 4635 310548 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 549 4590 3105 3870 3105 3870 2655 4590 2655 4590 310550 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\00151 -652 6 2970 3285 3690 373553 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 554 3690 3735 2970 3735 2970 3285 3690 3285 3690 373555 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\00156 -657 6 1890 3690 2610 414058 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 559 2610 4140 1890 4140 1890 3690 2610 3690 2610 414060 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\00161 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\00162 57 -6 63 58 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 … … 204 199 1710 5535 12510 5535 12510 2295 1710 2295 1710 5535 205 200 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 201 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095 202 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 203 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725 204 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 205 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095 206 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 207 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 208 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 206 209 5490 4545 4770 4545 4770 4995 5490 4995 5490 4545 207 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5208 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095209 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5210 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725211 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5212 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095213 210 4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 214 211 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 … … 226 223 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4860 context\001 227 224 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4995 predictor\001 225 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig
r81 r88 128 128 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 7695 dcache\001 129 129 -6 130 6 1890 3600 7650 6660131 130 6 5850 4995 6570 5445 132 131 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 … … 134 133 4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 5265 rename\001 135 134 -6 136 6 6570 4320 7290 4770137 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5138 7290 4770 6570 4770 6570 4320 7290 4320 7290 4770139 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 4590 commit\001140 -6141 135 6 4770 4590 5490 5040 142 136 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 … … 144 138 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 4860 decod\001 145 139 -6 140 6 3825 3960 4635 4410 141 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 142 4590 4410 3870 4410 3870 3960 4590 3960 4590 4410 143 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4230 predictor\001 144 -6 145 6 2970 4590 3690 5040 146 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 147 3690 5040 2970 5040 2970 4590 3690 4590 3690 5040 148 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4860 fetch\001 149 -6 150 6 1890 4995 2610 5445 151 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 152 2610 5445 1890 5445 1890 4995 2610 4995 2610 5445 153 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 5355 port\001 154 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 5175 icache\001 155 -6 146 156 6 4770 4140 5490 4590 147 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5157 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 148 158 5490 4590 4770 4590 4770 4140 5490 4140 5490 4590 149 159 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4320 context\001 150 160 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 4500 state\001 151 161 -6 152 6 3825 3960 4635 4410 153 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 154 4590 4410 3870 4410 3870 3960 4590 3960 4590 4410 155 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4230 predictor\001 156 -6 157 6 2970 4590 3690 5040 158 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 159 3690 5040 2970 5040 2970 4590 3690 4590 3690 5040 160 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4860 fetch\001 161 -6 162 6 1890 4995 2610 5445 163 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 164 2610 5445 1890 5445 1890 4995 2610 4995 2610 5445 165 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 5355 port\001 166 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 5175 icache\001 167 -6 162 2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 163 3 0 1.00 60.00 120.00 164 8010 3915 8370 3915 165 2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 166 3 0 1.00 60.00 120.00 167 11970 3915 12150 3915 12150 3240 8010 3240 168 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 169 3 0 1.00 60.00 120.00 170 3 0 1.00 60.00 120.00 171 10170 2925 10170 3420 172 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 173 3 0 1.00 60.00 120.00 174 3 0 1.00 60.00 120.00 175 10170 7020 10170 7515 176 2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 177 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 178 2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 179 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 180 2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 181 3 0 1.00 60.00 120.00 182 8010 6525 8370 6525 183 2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 184 3 0 1.00 60.00 120.00 185 11970 6525 12150 6525 12150 7200 8010 7200 168 186 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 169 187 3 0 1.00 60.00 120.00 … … 256 274 6930 4320 6930 4095 6030 4095 5130 3645 5130 4140 257 275 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 276 5490 5400 4770 5400 4770 5850 5490 5850 5490 5400 277 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 278 4590 6030 3870 6030 3870 6480 4590 6480 4590 6030 279 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 280 3690 5400 2970 5400 2970 5850 3690 5850 3690 5400 281 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 282 7290 4770 6570 4770 6570 4320 7290 4320 7290 4770 283 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 258 284 5490 5850 4770 5850 4770 6300 5490 6300 5490 5850 259 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 260 5490 5400 4770 5400 4770 5850 5490 5850 5490 5400 261 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 262 4590 6030 3870 6030 3870 6480 4590 6480 4590 6030 263 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 264 3690 5400 2970 5400 2970 5850 3690 5850 3690 5400 285 4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 286 4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 287 4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 265 288 4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 3825 Out Of Order Engine\001 266 289 4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 3735 Front End\001 … … 270 293 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 6165 context\001 271 294 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 6300 predictor\001 272 -6 273 2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 274 3 0 1.00 60.00 120.00 275 8010 3915 8370 3915 276 2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 277 3 0 1.00 60.00 120.00 278 11970 3915 12150 3915 12150 3240 8010 3240 279 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 280 3 0 1.00 60.00 120.00 281 3 0 1.00 60.00 120.00 282 10170 2925 10170 3420 283 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 284 3 0 1.00 60.00 120.00 285 3 0 1.00 60.00 120.00 286 10170 7020 10170 7515 287 2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 288 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 289 2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 290 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 291 2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 292 3 0 1.00 60.00 120.00 293 8010 6525 8370 6525 294 2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 295 3 0 1.00 60.00 120.00 296 11970 6525 12150 6525 12150 7200 8010 7200 297 4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 298 4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 299 4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 295 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 4590 commit\001 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig
r81 r88 157 157 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 158 158 -6 159 6 2790 2880 5580 4320 159 6 1890 6300 2610 6750 160 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 161 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 162 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001 163 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001 164 -6 160 165 6 4770 3690 5490 4140 161 166 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 … … 163 168 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 164 169 -6 170 6 3825 3060 4635 3510 171 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 172 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 173 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 174 -6 175 6 2970 3690 3690 4140 176 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 177 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 178 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 179 -6 165 180 6 4770 3240 5490 3690 166 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5181 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 167 182 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 168 183 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 169 184 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 170 -6171 6 3825 3060 4635 3510172 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5173 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510174 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001175 -6176 6 2970 3690 3690 4140177 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5178 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140179 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001180 -6181 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3182 3 0 1.00 60.00 120.00183 3 0 1.00 60.00 120.00184 4410 3510 4410 3870 4770 3870185 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3186 3 0 1.00 60.00 120.00187 3 0 1.00 60.00 120.00188 4050 3510 4050 3870 3690 3870189 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2190 3 0 1.00 60.00 120.00191 3780 3960 4770 3960192 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5193 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050194 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3195 3 0 1.00 60.00 120.00196 3 0 1.00 60.00 120.00197 3960 3510 3960 3780 3780 3780198 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2199 3 0 1.00 60.00 120.00200 3690 4050 4770 4050201 2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5202 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880203 -6204 6 1890 6300 2610 6750205 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5206 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750207 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001208 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001209 185 -6 210 186 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 … … 292 268 3690 6390 4770 6390 293 269 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 294 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750295 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5296 270 5490 6300 4770 6300 4770 6750 5490 6750 5490 6300 297 271 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 … … 314 288 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 315 289 6570 6300 5850 6300 5850 6750 6570 6750 6570 6300 290 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 291 3 0 1.00 60.00 120.00 292 3 0 1.00 60.00 120.00 293 4410 3510 4410 3870 4770 3870 294 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 295 3 0 1.00 60.00 120.00 296 3 0 1.00 60.00 120.00 297 4050 3510 4050 3870 3690 3870 298 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 299 3 0 1.00 60.00 120.00 300 3780 3960 4770 3960 301 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 302 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 303 2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 304 3 0 1.00 60.00 120.00 305 3 0 1.00 60.00 120.00 306 3960 3510 3960 3780 3780 3780 307 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 308 3 0 1.00 60.00 120.00 309 3690 4050 4770 4050 310 2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 311 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 312 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 313 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 316 314 4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 317 315 4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 … … 324 322 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 7065 context\001 325 323 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 7200 predictor\001 326 4 1 0 50 -1 -1 12 6.28324 135 555 6930 7245 commit\001327 4 1 0 50 -1 -1 12 6.28324 90 555 6210 6525 rename\001324 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 7245 commit\001 325 4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 6525 rename\001 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig
r81 r88 1 #FIG 3.2 Produced by xfig version 3.2.51 #FIG 3.2 2 2 Landscape 3 3 Center … … 8 8 -2 9 9 1200 2 10 6 4770 3240 5490 369011 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 512 5490 3690 4770 3690 4770 3240 5490 3240 5490 369013 4 1 0 50 -1 -1 12 0.0000 4 120 645 5130 3420 context\00114 4 1 0 50 -1 -1 12 0.0000 4 120 420 5130 3600 state\00115 -616 10 6 8370 3690 9090 4140 17 11 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 18 12 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 19 4 1 0 50 -1 -1 12 0.0000 4 1 50 390 8730 3960 read\00113 4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 20 14 -6 21 15 6 11250 3690 11970 4140 22 16 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 23 17 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 24 4 1 0 50 -1 -1 12 0.0000 4 1 50 450 11610 3960 write\00118 4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 25 19 -6 26 20 6 9810 2475 10530 2925 27 21 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 28 22 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 29 4 1 0 50 -1 -1 12 0.0000 4 1 65 34510170 2835 port\00130 4 1 0 50 -1 -1 12 0.0000 4 1 50 630 10170 2655 dcache\00123 4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 24 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 31 25 -6 32 26 6 3825 3060 4635 3510 33 27 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 34 28 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 35 4 1 0 50 -1 -1 12 0.0000 4 195 780 4230 3330 predictor\001 36 -6 37 6 2970 3690 3690 4140 38 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 39 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 40 4 1 0 50 -1 -1 12 0.0000 4 150 435 3330 3960 fetch\001 29 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 41 30 -6 42 31 6 1890 3690 2610 4140 43 32 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 44 33 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 45 4 1 0 50 -1 -1 12 0.0000 4 1 65 3452250 4050 port\00146 4 1 0 50 -1 -1 12 0.0000 4 1 50 5702250 3870 icache\00134 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 35 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 47 36 -6 48 37 6 1800 4590 5265 5355 … … 53 42 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 54 43 2160 5310 1800 5310 1800 5130 2160 5130 2160 5310 55 4 0 0 50 -1 -1 12 0.0000 4 1 95 6602340 4770 Groupe\00156 4 0 0 50 -1 -1 12 0.0000 4 1 95 2610 2340 5310 Une occurence dans le groupe\00157 4 0 0 50 -1 -1 12 0.0000 4 1 95 3120 2340 5040 Plusieurs occurences dans le groupe\00144 4 0 0 50 -1 -1 12 0.0000 4 180 555 2340 4770 Groupe\001 45 4 0 0 50 -1 -1 12 0.0000 4 180 2280 2340 5310 Une occurence dans le groupe\001 46 4 0 0 50 -1 -1 12 0.0000 4 180 2760 2340 5040 Plusieurs occurences dans le groupe\001 58 47 -6 59 48 6 6570 3015 7290 3465 60 49 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 61 50 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 62 4 1 0 50 -1 -1 12 0.0000 4 150 645 6930 3285 commit\001 63 -6 64 6 4770 3690 5490 4140 65 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 66 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 67 4 1 0 50 -1 0 12 0.0000 4 150 525 5130 3960 decod\001 51 4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 68 52 -6 69 53 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 … … 165 149 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 166 150 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 151 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 152 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 153 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 154 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 167 155 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 156 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 157 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 168 158 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 169 4 1 0 50 -1 -1 12 0.0000 4 195 660 10170 4905 register\001 170 4 1 0 50 -1 -1 12 1.5708 4 150 510 10935 3915 select\001 171 4 1 0 50 -1 -1 12 1.5708 4 150 510 9495 3915 select\001 172 4 0 1 50 -1 -1 12 0.0000 4 150 435 1710 2205 Core\001 173 4 0 1 50 -1 -1 12 0.0000 4 150 855 2790 2790 Front End\001 174 4 0 1 50 -1 -1 12 0.0000 4 195 1365 8190 3015 Execution Loop\001 175 4 0 1 50 -1 -1 12 0.0000 4 195 1770 5760 2520 Out Of Order Engine\001 176 4 1 0 50 -1 -1 12 1.5708 4 150 510 7875 3600 select\001 177 4 1 0 50 -1 -1 12 0.0000 4 120 690 10170 4230 execute\001 178 4 1 0 50 -1 -1 12 0.0000 4 150 720 10170 3690 memory\001 179 4 1 0 50 -1 0 12 0.0000 4 105 660 6210 3960 rename\001 159 4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 160 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 161 4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 162 4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 163 4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 164 4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 165 4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 166 4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 167 4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 168 4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 169 4 1 0 50 -1 0 12 0.0000 4 90 555 6210 3960 rename\001 170 4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 171 4 1 0 50 -1 0 12 0.0000 4 135 450 5130 3960 decod\001 172 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 173 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 -
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig
r81 r88 8 8 -2 9 9 1200 2 10 6 -1425 -600 2850 4050 10 6 900 -1500 2100 -750 11 6 900 -1500 2100 -1200 12 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 13 2100 -1200 900 -1200 900 -1500 2100 -1500 2100 -1200 14 4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -1350 D\351but\001 15 -6 16 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 17 3 0 1.00 60.00 120.00 18 1500 -1200 1500 -750 19 -6 11 20 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525 21 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850 22 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 375 600 225 1500 375 2100 150 12 23 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950 13 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 285014 24 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 15 25 3 0 1.00 60.00 120.00 16 1650 600 2250 1050 17 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 18 3 0 1.00 60.00 120.00 19 1350 600 1050 1050 26 1500 825 2250 1050 20 27 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 21 28 3 0 1.00 60.00 120.00 … … 38 45 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 39 46 3 0 1.00 60.00 120.00 40 -750 525 -750 - 75 1200 -75 1200 15047 -750 525 -750 -975 1200 -975 1200 -750 41 48 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 42 49 3 0 1.00 60.00 120.00 43 50 900 3075 -750 3075 -750 975 44 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 245 3 0 1.00 60.00 120.0046 1500 -300 1500 15047 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 548 2100 -300 900 -300 900 -600 2100 -600 2100 -30049 51 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 50 52 2100 4050 900 4050 900 3750 2100 3750 2100 4050 51 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 552 2100 600 900 600 900 150 2100 150 2100 60053 53 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 54 54 1350 1500 150 1500 150 1050 1350 1050 1350 1500 55 55 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 56 56 2850 1500 1650 1500 1650 1050 2850 1050 2850 1500 57 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 58 4 1 0 50 -1 2 8 0.0000 0 90 990 2250 1275 TestBench VHDL\001 59 4 1 0 50 -1 2 8 0.0000 0 105 1005 750 1275 G\351n\351rateur VHDL\001 60 4 1 0 50 -1 2 8 0.0000 0 105 465 1500 375 SystemC\001 61 4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 62 4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 63 4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -450 D\351but\001 64 4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 65 4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 66 -6 57 2 1 0 1 0 7 50 -1 20 0.000 0 0 7 1 0 2 58 3 0 1.00 60.00 120.00 59 1500 825 1050 1050 60 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 2 61 1500 600 1500 825 62 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 63 3 0 1.00 60.00 120.00 64 2100 375 2250 375 2250 -900 1800 -900 1800 -750 65 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 66 3 0 1.00 60.00 120.00 67 1500 -300 1500 150 68 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 69 2100 -300 900 -300 900 -750 2100 -750 2100 -300 67 70 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001 68 71 4 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001 69 72 4 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001 70 73 4 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001 71 4 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001 74 4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 75 4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 76 4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 77 4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 78 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 750 ok\001 79 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 375 Test\001 80 4 0 0 51 -1 0 8 0.0000 0 75 120 2025 225 ko\001 72 81 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001 82 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 83 4 2 0 51 -1 0 8 0.0000 0 75 120 825 2025 ko\001 84 4 1 0 50 -1 2 8 0.0000 0 75 375 750 1425 VHDL\001 85 4 1 0 50 -1 2 8 0.0000 0 75 375 2250 1425 VHDL\001 86 4 1 0 50 -1 2 8 0.0000 0 90 615 2250 1200 TestBench \001 87 4 1 0 50 -1 2 8 0.0000 0 105 465 1500 -375 SystemC\001 88 4 1 0 50 -1 2 8 0.0000 0 105 450 750 1200 Mod\350le \001 89 4 1 0 50 -1 2 8 0.0000 0 105 450 1500 -600 Mod\350le \001
Note: See TracChangeset
for help on using the changeset viewer.
