Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit
- Files:
-
- 16 edited
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SelfTest/Makefile (modified) (1 diff)
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SelfTest/configuration.cfg (modified) (1 diff)
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SelfTest/include/Memory.h (modified) (1 diff)
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SelfTest/src/main.cpp (modified) (4 diffs)
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SelfTest/src/test2.cpp (modified) (23 diffs)
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include/Load_store_unit.h (modified) (2 diffs)
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include/Parameters.h (modified) (3 diffs)
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src/Load_store_unit.cpp (modified) (6 diffs)
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src/Load_store_unit_allocation.cpp (modified) (4 diffs)
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src/Load_store_unit_deallocation.cpp (modified) (3 diffs)
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src/Load_store_unit_end_cycle.cpp (modified) (2 diffs)
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src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (modified) (1 diff)
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src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (4 diffs)
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src/Load_store_unit_function_speculative_load_commit_transition.cpp (modified) (11 diffs)
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src/Parameters.cpp (modified) (2 diffs)
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src/Parameters_msg_error.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile
r81 r88 24 24 library_clean : Load_store_unit_library_clean 25 25 26 local_clean : 27 26 28 include ../Makefile.deps 27 29 include $(DIR_MORPHEO)/Behavioural/Makefile.flags -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
r81 r88 6 6 2 2 +1 # speculative_load {none,access,commit,bypass} 7 7 0 0 +1 # bypass_memory 8 1 1 +1 # nb_cache_port 9 1 1 +1 # nb_inst_memory 8 10 2 2 *2 # nb_context 1 1 *2 9 11 2 2 *2 # nb_front_end 1 1 *2 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
r81 r88 287 287 << i->_data_old << " -> " 288 288 << i->_data_new << std::endl 289 << std:: hex;289 << std::dec; 290 290 } 291 291 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp
r81 r88 22 22 << " - speculative_load (uint32_t)" << endl 23 23 << " - nb_bypass_memory (uint32_t)" << endl 24 << " - nb_cache_port (uint32_t)" << endl 25 << " - nb_inst_memory (uint32_t)" << endl 24 26 << " - nb_context (uint32_t)" << endl 25 27 << " - nb_front_end (uint32_t)" << endl … … 62 64 const Tspeculative_load_t _speculative_load = fromString<Tspeculative_load_t>(argv[x++]); 63 65 const uint32_t _nb_bypass_memory = atoi(argv[x++]); 66 const uint32_t _nb_cache_port = atoi(argv[x++]); 67 const uint32_t _nb_inst_memory = atoi(argv[x++]); 64 68 const uint32_t _nb_context = atoi(argv[x++]); 65 69 const uint32_t _nb_front_end = atoi(argv[x++]); … … 81 85 _speculative_load , 82 86 _nb_bypass_memory , 87 _nb_cache_port , 88 _nb_inst_memory , 83 89 _nb_context , 84 90 _nb_front_end , … … 88 94 _size_special_data , 89 95 _nb_general_register , 90 _nb_special_register ); 96 _nb_special_register , 97 true //is_toplevel 98 ); 91 99 92 100 cout << param->print(1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r82 r88 9 9 #include <queue> 10 10 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" 11 #include "Behavioural/include/Allocation.h" 11 12 12 13 //===================================================================={test} … … 26 27 SPECULATIVE_LOAD_COMMIT, //_speculative_load 27 28 0, //_nb_bypass_memory 29 1, //_nb_cache_port 30 1, //_nb_inst_memory 28 31 1, //_nb_context 29 32 1, //_nb_front_end … … 33 36 2 , //_size_special_data 34 37 64, //_nb_general_register 35 16 //_nb_special_register 38 16, //_nb_special_register 39 true //is_toplevel 36 40 ); 37 41 … … 39 43 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); 40 44 #endif 45 46 Tusage_t _usage = USE_ALL; 47 48 // _usage = usage_unset(_usage,USE_SYSTEMC ); 49 // _usage = usage_unset(_usage,USE_VHDL ); 50 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); 51 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 52 // _usage = usage_unset(_usage,USE_POSITION ); 53 // _usage = usage_unset(_usage,USE_STATISTICS ); 54 // _usage = usage_unset(_usage,USE_INFORMATION ); 41 55 42 56 Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), … … 45 59 #endif 46 60 _param, 47 USE_ALL);61 _usage); 48 62 49 63 #ifdef SYSTEMC … … 56 70 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 57 71 58 sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str()); 59 sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str()); 60 sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str()); 61 sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str()); 62 sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str()); 63 sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str()); 64 sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str()); 65 sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str()); 66 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 67 sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str()); 68 sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str()); 69 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str()); 70 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str()); 71 sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str()); 72 sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str()); 73 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str()); 74 sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str()); 75 sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str()); 76 sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str()); 77 78 sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); 79 sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); 80 sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); 81 sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str()); 82 sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str()); 83 sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 84 // sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str()); 85 sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str()); 86 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str()); 87 sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str()); 88 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str()); 89 sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str()); 90 sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str()); 91 sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str()); 92 sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str()); 93 sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str()); 94 sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str()); 95 96 sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); 97 sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); 98 sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); 99 sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 100 sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str()); 101 sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str()); 102 sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); 103 104 sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str()); 105 sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str()); 106 sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str()); 107 sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str()); 108 sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str()); 109 sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str()); 110 111 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; 112 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; 113 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; 114 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; 115 116 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 117 { 118 out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str()); 119 out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str()); 120 out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str()); 121 out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str()); 122 } 72 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory); 74 ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory); 75 ALLOC1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ," in_MEMORY_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); 76 ALLOC1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ," in_MEMORY_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); 77 ALLOC1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ," in_MEMORY_IN_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); 78 ALLOC1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ," in_MEMORY_IN_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); 79 ALLOC1_SC_SIGNAL( in_MEMORY_IN_OPERATION ," in_MEMORY_IN_OPERATION ",Toperation_t ,_param->_nb_inst_memory); 80 ALLOC1_SC_SIGNAL( in_MEMORY_IN_TYPE ," in_MEMORY_IN_TYPE ",Ttype_t ,_param->_nb_inst_memory); 81 ALLOC1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE," in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_memory); 82 ALLOC1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ," in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_memory); 83 ALLOC1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ," in_MEMORY_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_memory); 84 ALLOC1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ," in_MEMORY_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address 85 ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ," in_MEMORY_IN_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address 86 ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ," in_MEMORY_IN_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (store) 87 ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ," in_MEMORY_IN_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_memory); 88 ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ," in_MEMORY_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) 89 ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ," in_MEMORY_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) 90 ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ," in_MEMORY_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); 91 ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ," in_MEMORY_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); 92 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_VAL ,"out_MEMORY_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_memory); 93 ALLOC1_SC_SIGNAL( in_MEMORY_OUT_ACK ," in_MEMORY_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_memory); 94 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,"out_MEMORY_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); 95 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,"out_MEMORY_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); 96 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID ,"out_MEMORY_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); 97 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); 98 //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); 99 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); 100 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) 101 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) 102 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,"out_MEMORY_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (load) 103 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,"out_MEMORY_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); 104 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,"out_MEMORY_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); 105 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,"out_MEMORY_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_inst_memory); 106 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); 107 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); 108 ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_memory); 109 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); 110 ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); 111 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); 112 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); 113 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_cache_port); 114 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_cache_port); 115 ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_cache_port); 116 ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_cache_port); 117 ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_cache_port); 118 ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); 119 ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); 120 ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_cache_port); 121 ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_cache_port); 122 ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,"out_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory); 123 ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"out_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory); 124 ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,"out_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory); 125 ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,"out_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory); 123 126 124 127 /******************************************************** … … 131 134 (*(_Load_store_unit->in_NRESET)) (*(in_NRESET)); 132 135 133 (*(_Load_store_unit-> in_MEMORY_IN_VAL ))(*( in_MEMORY_IN_VAL ));134 (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK ));136 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_VAL ,_param->_nb_inst_memory); 137 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_IN_ACK ,_param->_nb_inst_memory); 135 138 if (_param->_have_port_context_id) 136 (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID ));139 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); 137 140 if (_param->_have_port_front_end_id) 138 (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); 139 if (_param->_have_port_ooo_engine_id) 140 (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); 141 if (_param->_have_port_packet_id) 142 (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); 143 (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); 144 (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); 145 (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); 146 if (_param->_have_port_load_queue_ptr) 147 (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); 148 (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); 149 (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); 150 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); 151 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); 152 (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); 153 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); 154 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); 155 (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); 156 (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); 157 158 (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); 159 (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); 141 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); 142 if (_param->_have_port_ooo_engine_id) 143 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); 144 if (_param->_have_port_rob_ptr) 145 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); 146 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); 147 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); 148 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); 149 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); 150 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); 151 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); 152 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); 153 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); 154 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); 155 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); 156 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); 157 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); 158 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); 159 160 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); 161 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); 160 162 if (_param->_have_port_context_id) 161 (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));163 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); 162 164 if (_param->_have_port_front_end_id) 163 (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID ));164 if (_param->_have_port_ooo_engine_id) 165 (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID ));166 if (_param->_have_port_ packet_id)167 (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID ));168 // (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION ));169 (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE ));170 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD ));171 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));172 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD ));173 (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE ));174 (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));175 (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE ));176 (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION ));177 (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE ));178 (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS ));179 180 (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL ));181 (*(_Load_store_unit-> in_DCACHE_REQ_ACK ))(*( in_DCACHE_REQ_ACK ));165 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); 166 if (_param->_have_port_ooo_engine_id) 167 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); 168 if (_param->_have_port_rob_ptr) 169 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 170 //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 171 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 172 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 173 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); 174 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); 175 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); 176 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); 177 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); 178 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); 179 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); 180 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); 181 182 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_VAL ,_param->_nb_cache_port); 183 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_REQ_ACK ,_param->_nb_cache_port); 182 184 if (_param->_have_port_dcache_context_id) 183 (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));184 (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));185 (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS ))(*(out_DCACHE_REQ_ADDRESS ));186 (*(_Load_store_unit->out_DCACHE_REQ_TYPE ))(*(out_DCACHE_REQ_TYPE ));187 (*(_Load_store_unit->out_DCACHE_REQ_WDATA ))(*(out_DCACHE_REQ_WDATA ));188 189 (*(_Load_store_unit-> in_DCACHE_RSP_VAL ))(*( in_DCACHE_RSP_VAL ));190 (*(_Load_store_unit->out_DCACHE_RSP_ACK ))(*(out_DCACHE_RSP_ACK ));185 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); 186 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); 187 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); 188 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); 189 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); 190 191 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_VAL ,_param->_nb_cache_port); 192 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_RSP_ACK ,_param->_nb_cache_port); 191 193 if (_param->_have_port_dcache_context_id) 192 (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); 193 (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID )); 194 (*(_Load_store_unit-> in_DCACHE_RSP_RDATA ))(*( in_DCACHE_RSP_RDATA )); 195 (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); 196 197 { 198 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 199 { 200 (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); 201 if (_param->_have_port_ooo_engine_id) 202 (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i])); 203 (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); 204 (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); 205 } 206 } 194 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); 195 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); 196 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); 197 INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); 198 199 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); 200 if (_param->_have_port_ooo_engine_id) 201 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); 202 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); 203 INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); 204 205 207 206 cout << "<" << name << "> Start Simulation ............" << endl; 208 207 Time * _time = new Time(); … … 238 237 LABEL("Initialisation"); 239 238 240 in_MEMORY_IN_VAL ->write(0);241 in_MEMORY_OUT_ACK ->write(0);242 in_DCACHE_REQ_ACK ->write(0);243 in_DCACHE_RSP_VAL ->write(0);239 in_MEMORY_IN_VAL [0]->write(0); 240 in_MEMORY_OUT_ACK[0]->write(0); 241 in_DCACHE_REQ_ACK[0]->write(0); 242 in_DCACHE_RSP_VAL[0]->write(0); 244 243 245 244 in_NRESET ->write(0); … … 419 418 can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write]; 420 419 } 421 in_MEMORY_IN_VAL ->write(can_execute);420 in_MEMORY_IN_VAL [0]->write(can_execute); 422 421 423 422 if (not fifo_request.empty()) 424 423 { 425 424 if (_param->_have_port_context_id) 426 in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );425 in_MEMORY_IN_CONTEXT_ID [0]->write (fifo_request.top()._context_id ); 427 426 if (_param->_have_port_front_end_id) 428 in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );427 in_MEMORY_IN_FRONT_END_ID [0]->write (fifo_request.top()._front_end_id ); 429 428 if (_param->_have_port_ooo_engine_id) 430 in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );431 if (_param->_have_port_ packet_id)432 in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );433 in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );434 in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );435 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE ->write (fifo_request.top()._store_queue_ptr_write);429 in_MEMORY_IN_OOO_ENGINE_ID [0]->write (fifo_request.top()._ooo_engine_id ); 430 if (_param->_have_port_rob_ptr) 431 in_MEMORY_IN_PACKET_ID [0]->write (fifo_request.top()._packet_id ); 432 in_MEMORY_IN_OPERATION [0]->write (fifo_request.top()._operation ); 433 in_MEMORY_IN_TYPE [0]->write (fifo_request.top()._type ); 434 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[0]->write (fifo_request.top()._store_queue_ptr_write); 436 435 if (_param->_have_port_load_queue_ptr) 437 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );438 in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );439 in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );440 in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );441 // in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );442 in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );436 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE [0]->write (fifo_request.top()._load_queue_ptr_write ); 437 in_MEMORY_IN_IMMEDIAT [0]->write (fifo_request.top()._immediat ); 438 in_MEMORY_IN_DATA_RA [0]->write (fifo_request.top()._data_ra ); 439 in_MEMORY_IN_DATA_RB [0]->write (fifo_request.top()._data_rb ); 440 // in_MEMORY_IN_WRITE_RD [0]->write (fifo_request.top()._write_rd ); 441 in_MEMORY_IN_NUM_REG_RD [0]->write (fifo_request.top()._num_reg_rd ); 443 442 } 444 in_MEMORY_OUT_ACK ->write((rand()%100)<percent_transaction_memory_out);443 in_MEMORY_OUT_ACK[0]->write((rand()%100)<percent_transaction_memory_out); 445 444 446 445 // ***** DCACHE_REQ ***** 447 in_DCACHE_REQ_ACK ->write((rand()%100)<percent_transaction_dcache);446 in_DCACHE_REQ_ACK[0]->write((rand()%100)<percent_transaction_dcache); 448 447 449 448 // ***** DCACHE_RSP ***** 450 449 bool have_rsp = _cache->have_rsp (); 451 in_DCACHE_RSP_VAL ->write(have_rsp);450 in_DCACHE_RSP_VAL[0]->write(have_rsp); 452 451 453 452 if (have_rsp) 454 453 { 455 in_DCACHE_RSP_CONTEXT_ID ->write(_cache->front()._context_id);456 in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );457 in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );458 in_DCACHE_RSP_ERROR ->write(_cache->front()._error );454 in_DCACHE_RSP_CONTEXT_ID[0]->write(_cache->front()._context_id); 455 in_DCACHE_RSP_PACKET_ID [0]->write(_cache->front()._packet_id ); 456 in_DCACHE_RSP_RDATA [0]->write(_cache->front()._rdata ); 457 in_DCACHE_RSP_ERROR [0]->write(_cache->front()._error ); 459 458 } 460 459 461 460 SC_START(0); 462 461 463 LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL ->read(),out_MEMORY_IN_ACK->read());464 if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK->read())462 LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL [0]->read(),out_MEMORY_IN_ACK [0]->read()); 463 if ( in_MEMORY_IN_VAL [0]->read() and out_MEMORY_IN_ACK [0]->read()) 465 464 { 466 Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID ->read();465 Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID[0]->read(); 467 466 468 467 LABEL(" * Accepted MEMORY_IN : %d",packet_id); … … 483 482 } 484 483 485 LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL ->read(),in_MEMORY_OUT_ACK->read());486 if (out_MEMORY_OUT_VAL ->read() and in_MEMORY_OUT_ACK->read())484 LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL[0]->read(),in_MEMORY_OUT_ACK [0]->read()); 485 if (out_MEMORY_OUT_VAL[0]->read() and in_MEMORY_OUT_ACK[0]->read()) 487 486 { 488 Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID ->read();487 Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID[0]->read(); 489 488 490 489 LABEL(" * Accepted MEMORY_OUT : %d",packet_id); … … 499 498 else 500 499 { 501 if (not (out_MEMORY_OUT_EXCEPTION ->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))500 if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) 502 501 { 503 502 nb_request_memory_out ++; … … 508 507 { 509 508 std::cout << "seth - have a load_speculative." << std::endl; 510 tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD ->read() != tab_request[packet_id]._data_wait);509 tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD[0]->read() != tab_request[packet_id]._data_wait); 511 510 tab_request[packet_id]._previous_load_speculative = 1; 512 511 } … … 516 515 517 516 // a lot of test 518 TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );519 TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );520 TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );521 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID ->read(), tab_request[packet_id]._ooo_engine_id);522 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation );523 TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY );517 TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID [0]->read(), tab_request[packet_id]._packet_id ); 518 TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID [0]->read(), tab_request[packet_id]._context_id ); 519 TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID [0]->read(), tab_request[packet_id]._front_end_id ); 520 TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); 521 // TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); 522 TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); 524 523 525 524 if (is_operation_memory_load (tab_request[packet_id]._operation)) 526 525 { 527 TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );526 TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD [0]->read(), tab_request[packet_id]._num_reg_rd ); 528 527 } 529 528 … … 532 531 bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))); 533 532 bool berr = (address >= size_memory); 534 Texception_t exception = out_MEMORY_OUT_EXCEPTION ->read();533 Texception_t exception = out_MEMORY_OUT_EXCEPTION[0]->read(); 535 534 536 535 if (is_operation_memory_store(tab_request[packet_id]._operation)) 537 536 { 538 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0);537 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 0); 539 538 540 539 // store. … … 568 567 if (test_result_ko) 569 568 { 570 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD ->read(), address);569 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); 571 570 } 572 571 } … … 578 577 bool is_load = is_operation_memory_load(tab_request[packet_id]._operation); 579 578 580 if (not (out_MEMORY_OUT_EXCEPTION ->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))579 if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) 581 580 { 582 581 bool test_result_ko = false; … … 586 585 // IS A LOAD :D 587 586 TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); 588 TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD ->read(), 1);587 TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), 1); 589 588 } 590 589 else … … 592 591 { 593 592 TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); 594 TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD ->read(), is_load);593 TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); 595 594 test_result_ko = true; 596 595 } … … 599 598 { 600 599 TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); 601 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), is_load);600 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); 602 601 test_result_ko = true; 603 602 } … … 605 604 { 606 605 TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); 607 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), is_load and not tab_request[packet_id]._previous_load_speculative);606 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load and not tab_request[packet_id]._previous_load_speculative); 608 607 } 609 608 // In all case : test data 610 609 if (test_result_ko) 611 610 { 612 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD ->read(), address);611 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); 613 612 } 614 613 else 615 614 { 616 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD ->read(), tab_request[packet_id]._data_wait);615 TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait); 617 616 } 618 617 } 619 618 else 620 619 { 621 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1);620 TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 1); 622 621 } 623 622 } 624 623 } 625 624 626 LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL ->read(),in_DCACHE_REQ_ACK->read());627 if (out_DCACHE_REQ_VAL ->read() and in_DCACHE_REQ_ACK->read())625 LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL[0]->read(),in_DCACHE_REQ_ACK [0]->read()); 626 if (out_DCACHE_REQ_VAL[0]->read() and in_DCACHE_REQ_ACK[0]->read()) 628 627 { 629 628 Tcontext_t context_id; 630 629 Tpacket_t packet_id ; 631 Tdcache_address_t address = out_DCACHE_REQ_ADDRESS ->read();630 Tdcache_address_t address = out_DCACHE_REQ_ADDRESS[0]->read(); 632 631 Tdcache_data_t rdata; 633 632 Tdcache_error_t error = 0; 634 633 if (_param->_have_port_dcache_context_id) 635 context_id = out_DCACHE_REQ_CONTEXT_ID ->read();634 context_id = out_DCACHE_REQ_CONTEXT_ID[0]->read(); 636 635 else 637 636 context_id = 0; 638 637 639 packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;638 packet_id = (out_DCACHE_REQ_PACKET_ID [0]->read())>>1; 640 639 641 640 LABEL(" * Accepted DCACHE_REQ : %d",packet_id); … … 649 648 else 650 649 { 651 rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE ->read(), out_DCACHE_REQ_WDATA->read());650 rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE[0]->read(), out_DCACHE_REQ_WDATA[0]->read()); 652 651 LABEL(" * rdata : 0x%x",rdata); 653 652 } 654 653 655 654 // test type : send or not a respons ! 656 if ((out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_SYNCHRONIZATION) or657 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_LOAD_8 ) or658 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_LOAD_16) or659 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_LOAD_32) or660 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_LOAD_64) or661 ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_STORE_8 ) or662 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_STORE_16) or663 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_STORE_32) or664 (out_DCACHE_REQ_TYPE ->read() == DCACHE_TYPE_STORE_64) )))655 if ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_SYNCHRONIZATION) or 656 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_8 ) or 657 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_16) or 658 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_32) or 659 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_64) or 660 ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_8 ) or 661 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_16) or 662 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_32) or 663 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_64) ))) 665 664 { 666 665 LABEL(" * have_dcache_rsp"); 667 666 668 667 _cache->push (context_id, 669 out_DCACHE_REQ_PACKET_ID ->read(),668 out_DCACHE_REQ_PACKET_ID [0]->read(), 670 669 rdata, 671 670 error); … … 673 672 } 674 673 675 LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL ->read(),out_DCACHE_RSP_ACK->read());676 if (in_DCACHE_RSP_VAL ->read() and out_DCACHE_RSP_ACK->read())674 LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL[0]->read(),out_DCACHE_RSP_ACK [0]->read()); 675 if (in_DCACHE_RSP_VAL[0]->read() and out_DCACHE_RSP_ACK[0]->read()) 677 676 { 678 677 _cache->pop(); … … 704 703 delete in_NRESET; 705 704 706 delete in_MEMORY_IN_VAL ; 707 delete out_MEMORY_IN_ACK ; 708 delete in_MEMORY_IN_CONTEXT_ID ; 709 delete in_MEMORY_IN_FRONT_END_ID ; 710 delete in_MEMORY_IN_OOO_ENGINE_ID ; 711 delete in_MEMORY_IN_PACKET_ID ; 712 delete in_MEMORY_IN_OPERATION ; 713 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 714 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 715 delete in_MEMORY_IN_HAS_IMMEDIAT; 716 delete in_MEMORY_IN_IMMEDIAT ; 717 delete in_MEMORY_IN_DATA_RA ; 718 delete in_MEMORY_IN_DATA_RB ; 719 delete in_MEMORY_IN_DATA_RC ; 720 delete in_MEMORY_IN_WRITE_RD ; 721 delete in_MEMORY_IN_NUM_REG_RD ; 722 delete in_MEMORY_IN_WRITE_RE ; 723 delete in_MEMORY_IN_NUM_REG_RE ; 724 725 delete out_MEMORY_OUT_VAL ; 726 delete in_MEMORY_OUT_ACK ; 727 delete out_MEMORY_OUT_CONTEXT_ID; 728 delete out_MEMORY_OUT_FRONT_END_ID; 729 delete out_MEMORY_OUT_OOO_ENGINE_ID; 730 delete out_MEMORY_OUT_PACKET_ID ; 731 // delete out_MEMORY_OUT_OPERATION ; 732 delete out_MEMORY_OUT_TYPE ; 733 delete out_MEMORY_OUT_WRITE_RD ; 734 delete out_MEMORY_OUT_NUM_REG_RD; 735 delete out_MEMORY_OUT_DATA_RD ; 736 delete out_MEMORY_OUT_WRITE_RE ; 737 delete out_MEMORY_OUT_NUM_REG_RE; 738 delete out_MEMORY_OUT_DATA_RE ; 739 delete out_MEMORY_OUT_EXCEPTION ; 740 delete out_MEMORY_OUT_NO_SEQUENCE; 741 delete out_MEMORY_OUT_ADDRESS ; 742 743 delete out_DCACHE_REQ_VAL ; 744 delete in_DCACHE_REQ_ACK ; 745 delete out_DCACHE_REQ_CONTEXT_ID; 746 delete out_DCACHE_REQ_PACKET_ID ; 747 delete out_DCACHE_REQ_ADDRESS ; 748 delete out_DCACHE_REQ_TYPE ; 749 delete out_DCACHE_REQ_WDATA ; 750 751 delete in_DCACHE_RSP_VAL ; 752 delete out_DCACHE_RSP_ACK ; 753 delete in_DCACHE_RSP_CONTEXT_ID; 754 delete in_DCACHE_RSP_PACKET_ID ; 755 delete in_DCACHE_RSP_RDATA ; 756 delete in_DCACHE_RSP_ERROR ; 757 758 { 759 delete [] out_BYPASS_MEMORY_VAL ; 760 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 761 delete [] out_BYPASS_MEMORY_NUM_REG ; 762 delete [] out_BYPASS_MEMORY_DATA ; 763 } 705 DELETE1_SC_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory); 706 DELETE1_SC_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory); 707 DELETE1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); 708 DELETE1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); 709 DELETE1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); 710 DELETE1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); 711 DELETE1_SC_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); 712 DELETE1_SC_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); 713 DELETE1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); 714 DELETE1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); 715 DELETE1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); 716 DELETE1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); 717 DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); 718 DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); 719 DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); 720 DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); 721 DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); 722 DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); 723 DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); 724 725 DELETE1_SC_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); 726 DELETE1_SC_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); 727 DELETE1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); 728 DELETE1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); 729 DELETE1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); 730 DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); 731 //DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); 732 DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); 733 DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); 734 DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); 735 DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); 736 DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); 737 DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); 738 DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); 739 DELETE1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); 740 DELETE1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); 741 DELETE1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); 742 743 DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port); 744 DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port); 745 DELETE1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); 746 DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); 747 DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); 748 DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); 749 DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); 750 751 DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port); 752 DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port); 753 DELETE1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); 754 DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); 755 DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); 756 DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); 757 758 DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); 759 DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); 760 DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); 761 DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); 764 762 #endif 765 763 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r82 r88 90 90 91 91 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 92 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ;93 public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ;94 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_CONTEXT_ID ;95 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_FRONT_END_ID;96 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_OOO_ENGINE_ID;97 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ;98 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ;99 public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ;100 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;101 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;102 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT;103 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ;// memory address104 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ;// memory address105 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ;// data (store)106 public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ;107 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ;// = (operation==load)108 public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ;// destination (load)109 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ;110 public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ;92 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_VAL ;//[nb_inst_memory] 93 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_IN_ACK ;//[nb_inst_memory] 94 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_CONTEXT_ID ;//[nb_inst_memory] 95 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_FRONT_END_ID ;//[nb_inst_memory] 96 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_OOO_ENGINE_ID ;//[nb_inst_memory] 97 public : SC_IN (Tpacket_t ) ** in_MEMORY_IN_PACKET_ID ;//[nb_inst_memory] 98 public : SC_IN (Toperation_t ) ** in_MEMORY_IN_OPERATION ;//[nb_inst_memory] 99 public : SC_IN (Ttype_t ) ** in_MEMORY_IN_TYPE ;//[nb_inst_memory] 100 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory] 101 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory] 102 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_HAS_IMMEDIAT ;//[nb_inst_memory] 103 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_IMMEDIAT ;//[nb_inst_memory] // memory address 104 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RA ;//[nb_inst_memory] // memory address 105 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RB ;//[nb_inst_memory] // data (store) 106 public : SC_IN (Tspecial_data_t ) ** in_MEMORY_IN_DATA_RC ;//[nb_inst_memory] 107 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 108 public : SC_IN (Tgeneral_address_t) ** in_MEMORY_IN_NUM_REG_RD ;//[nb_inst_memory] // destination (load) 109 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RE ;//[nb_inst_memory] 110 public : SC_IN (Tspecial_address_t) ** in_MEMORY_IN_NUM_REG_RE ;//[nb_inst_memory] 111 111 112 112 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ;114 public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ;115 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID;116 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_FRONT_END_ID;117 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID;118 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ;119 //public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ;120 public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ;121 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ;// = (operation==load)122 public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD;// destination (load)123 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ;// data (load)124 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ;125 public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE;126 public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ;127 public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ;128 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_NO_SEQUENCE;129 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_ADDRESS ;113 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_VAL ;//[nb_inst_memory] 114 public : SC_IN (Tcontrol_t ) ** in_MEMORY_OUT_ACK ;//[nb_inst_memory] 115 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_CONTEXT_ID ;//[nb_inst_memory] 116 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_FRONT_END_ID ;//[nb_inst_memory] 117 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_OOO_ENGINE_ID ;//[nb_inst_memory] 118 public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] 119 //public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] 120 public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] 121 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 122 public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) 123 public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_DATA_RD ;//[nb_inst_memory] // data (load) 124 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RE ;//[nb_inst_memory] 125 public : SC_OUT(Tspecial_address_t) ** out_MEMORY_OUT_NUM_REG_RE ;//[nb_inst_memory] 126 public : SC_OUT(Tspecial_data_t ) ** out_MEMORY_OUT_DATA_RE ;//[nb_inst_memory] 127 public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] 128 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] 129 public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] 130 130 131 132 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 133 public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ;134 public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ;135 public : SC_OUT(Tcontext_t ) * out_DCACHE_REQ_CONTEXT_ID;136 public : SC_OUT(Tpacket_t ) * out_DCACHE_REQ_PACKET_ID ;137 public : SC_OUT(Tdcache_address_t ) * out_DCACHE_REQ_ADDRESS ;138 public : SC_OUT(Tdcache_type_t ) * out_DCACHE_REQ_TYPE ;139 public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ;132 public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_cache_port] 133 public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_cache_port] 134 public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_CONTEXT_ID ;//[nb_cache_port] 135 public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_cache_port] 136 public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_cache_port] 137 public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_cache_port] 138 public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_cache_port] 140 139 141 140 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 142 public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ;143 public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ;144 public : SC_IN (Tcontext_t ) * in_DCACHE_RSP_CONTEXT_ID;145 public : SC_IN (Tpacket_t ) * in_DCACHE_RSP_PACKET_ID ;146 public : SC_IN (Tdcache_data_t ) * in_DCACHE_RSP_RDATA ;147 public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ;141 public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_cache_port] 142 public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_cache_port] 143 public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_CONTEXT_ID ;//[nb_cache_port] 144 public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_cache_port] 145 public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_cache_port] 146 public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_cache_port] 148 147 149 148 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 150 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ;151 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; 152 public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ;153 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ;149 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; //[nb_bypass_memory] 150 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; //[nb_bypass_memory] 151 public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; //[nb_bypass_memory] 152 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; //[nb_bypass_memory] 154 153 155 154 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 177 176 // signal 178 177 public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ; 179 180 private : Tcontrol_t internal_MEMORY_IN_ACK; 181 private : Tcontrol_t internal_MEMORY_OUT_VAL; 178 179 private : Tcontrol_t internal_MEMORY_IN_ACK ; 180 private : uint32_t internal_MEMORY_IN_PORT ; 181 182 private : Tcontrol_t internal_MEMORY_OUT_VAL ; 182 183 private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; 183 p ublic : Tlsq_ptr_t internal_MEMORY_OUT_PTR;184 185 private : Tcontrol_t internal_DCACHE_RSP_ACK ;186 private : Tcontrol_t internal_DCACHE_REQ_VAL ;184 private : Tlsq_ptr_t internal_MEMORY_OUT_PTR ; 185 186 private : Tcontrol_t internal_DCACHE_RSP_ACK ; 187 private : Tcontrol_t internal_DCACHE_REQ_VAL ; 187 188 private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; 188 189 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
r81 r88 27 27 { 28 28 //-----[ fields ]------------------------------------------------------------ 29 public : const uint32_t _size_store_queue ; 30 public : const uint32_t _size_load_queue ; 31 public : const uint32_t _size_speculative_access_queue; 32 public : const uint32_t _nb_port_check ; 33 public : const Tspeculative_load_t _speculative_load ; 34 public : const uint32_t _nb_bypass_memory ; 35 //public : const uint32_t _nb_cache_port ; 36 public : const uint32_t _nb_context ; 37 public : const uint32_t _nb_front_end ; 38 public : const uint32_t _nb_ooo_engine ; 39 public : const uint32_t _nb_packet ; 40 public : const uint32_t _size_general_data ; 41 public : const uint32_t _size_special_data ; 42 public : const uint32_t _nb_general_register ; 43 public : const uint32_t _nb_special_register ; 29 public : uint32_t _size_store_queue ; 30 public : uint32_t _size_load_queue ; 31 public : uint32_t _size_speculative_access_queue; 32 public : uint32_t _nb_port_check ; 33 public : Tspeculative_load_t _speculative_load ; 34 public : uint32_t _nb_bypass_memory ; 35 public : uint32_t _nb_cache_port ; 36 public : uint32_t _nb_inst_memory ; 37 public : uint32_t _nb_context ; 38 public : uint32_t _nb_front_end ; 39 public : uint32_t _nb_ooo_engine ; 40 public : uint32_t _nb_packet ; 41 //public : uint32_t _size_general_data ; 42 //public : uint32_t _size_special_data ; 43 public : uint32_t _nb_general_register ; 44 public : uint32_t _nb_special_register ; 44 45 45 public : constuint32_t _size_address_store_queue ;46 public : constuint32_t _size_address_load_queue ;47 public : const uint32_t _size_address_speculative_access_queue;48 public : constuint32_t _size_context_id ;49 public : constuint32_t _size_front_end_id ;50 public : constuint32_t _size_ooo_engine_id ;51 public : constuint32_t _size_packet_id ;52 public : constuint32_t _size_general_register ;53 public : constuint32_t _size_special_register ;54 public : constuint32_t _size_dcache_context_id ;55 public : constuint32_t _size_dcache_packet_id ;46 //public : uint32_t _size_address_store_queue ; 47 //public : uint32_t _size_address_load_queue ; 48 public : uint32_t _size_speculative_access_queue_ptr ; 49 //public : uint32_t _size_context_id ; 50 //public : uint32_t _size_front_end_id ; 51 //public : uint32_t _size_ooo_engine_id ; 52 //public : uint32_t _size_packet_id ; 53 //public : uint32_t _size_general_register ; 54 //public : uint32_t _size_special_register ; 55 public : uint32_t _size_dcache_context_id ; 56 public : uint32_t _size_dcache_packet_id ; 56 57 57 public : constbool _have_port_context_id ;58 public : constbool _have_port_front_end_id ;59 public : constbool _have_port_ooo_engine_id ;60 public : constbool _have_port_packet_id ;61 public : constbool _have_port_dcache_context_id ;62 public : constbool _have_port_load_queue_ptr ;58 //public : bool _have_port_context_id ; 59 //public : bool _have_port_front_end_id ; 60 //public : bool _have_port_ooo_engine_id ; 61 //public : bool _have_port_packet_id ; 62 public : bool _have_port_dcache_context_id ; 63 //public : bool _have_port_load_queue_ptr ; 63 64 64 public : constTdcache_address_t _mask_address_lsb ;65 public : constTdcache_address_t _mask_address_msb ;65 public : Tdcache_address_t _mask_address_lsb ; 66 public : Tdcache_address_t _mask_address_msb ; 66 67 67 68 //-----[ methods ]----------------------------------------------------------- … … 72 73 Tspeculative_load_t speculative_load , 73 74 uint32_t nb_bypass_memory , 75 uint32_t nb_cache_port , 76 uint32_t nb_inst_memory , 74 77 uint32_t nb_context , 75 78 uint32_t nb_front_end , … … 79 82 uint32_t size_special_data , 80 83 uint32_t nb_general_register , 81 uint32_t nb_special_register ); 84 uint32_t nb_special_register , 85 bool is_toplevel=false); 82 86 83 public : Parameters (Parameters & param) ; 87 // public : Parameters (Parameters & param) ; 88 84 89 public : ~Parameters () ; 90 91 public : void copy (void); 85 92 86 93 public : Parameters_test msg_error (void); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
r82 r88 39 39 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 40 40 41 #if DEBUG_Load_store_unit == true 42 log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); 43 44 std::cout << *param << std::endl; 45 #endif 46 41 47 #ifdef SYSTEMC 42 48 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation"); … … 46 52 47 53 #ifdef STATISTICS 48 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); 49 50 statistics_declaration(param_statistics); 54 if (usage_is_set(_usage,USE_STATISTICS)) 55 { 56 log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); 57 58 statistics_declaration(param_statistics); 59 } 51 60 #endif 52 61 53 62 #ifdef VHDL 54 // generate the vhdl 55 log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); 56 57 vhdl(); 58 #endif 59 60 #ifdef SYSTEMC 63 if (usage_is_set(_usage,USE_VHDL)) 64 { 65 // generate the vhdl 66 log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); 67 68 vhdl(); 69 } 70 #endif 71 72 #ifdef SYSTEMC 73 if (usage_is_set(_usage,USE_SYSTEMC)) 74 { 61 75 // Function pointer 62 76 … … 84 98 85 99 internal_DCACHE_RSP_ACK = 1; 86 PORT_WRITE(out_DCACHE_RSP_ACK, 1); 100 PORT_WRITE(out_DCACHE_RSP_ACK [0], internal_DCACHE_RSP_ACK); 101 for (uint32_t i=1; i<_param->_nb_cache_port; ++i) 102 { 103 PORT_WRITE(out_DCACHE_RSP_ACK [i], 0); 104 PORT_WRITE(out_DCACHE_REQ_VAL [i], 0); 105 } 106 107 for (uint32_t i=1; i<_param->_nb_inst_memory; i++) 108 { 109 PORT_WRITE(out_MEMORY_OUT_VAL [i], 0); 110 } 87 111 88 112 log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition"); … … 111 135 dont_initialize (); 112 136 sensitive_neg << *(in_CLOCK); 113 sensitive << *(in_MEMORY_IN_OPERATION); 114 115 #ifdef SYSTEMCASS_SPECIFIC 116 // List dependency information 117 (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION)); 137 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 138 sensitive << (*(in_MEMORY_IN_VAL [i])) 139 << (*(in_MEMORY_IN_OPERATION [i])); 140 141 #ifdef SYSTEMCASS_SPECIFIC 142 // List dependency information 143 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 144 // for (uint32_t x=0; x<_param->_nb_inst_memory; x++) 145 { 146 (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_VAL [i])); 147 (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_OPERATION [i])); 148 } 118 149 #endif 119 150 … … 137 168 // List dependency information 138 169 #endif 139 170 } 140 171 #endif 141 172 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); … … 149 180 150 181 #ifdef STATISTICS 151 log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); 152 153 delete _stat; 182 if (usage_is_set(_usage,USE_STATISTICS)) 183 { 184 log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); 185 186 delete _stat; 187 } 154 188 #endif 155 189 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r82 r88 3 3 * $Id$ 4 4 * 5 * [ 5 * [ Description ] 6 6 * 7 7 */ 8 8 9 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 37 38 _interfaces = entity->set_interfaces(); 38 39 39 // ~~~~~[ 40 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 41 { 41 42 Interface * interface = _interfaces->set_interface("" … … 43 44 ,IN 44 45 ,SOUTH, 45 "Generalist interface"46 _("Generalist interface") 46 47 #endif 47 48 ); … … 50 51 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 51 52 } 52 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 54 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 55 { 54 Interface_fifo * interface = _interfaces->set_interface("memory_in" 55 #ifdef POSITION 56 ,IN 57 ,WEST 58 ,"Instruction from Reservations station" 59 #endif 60 ); 56 ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); 61 57 62 in_MEMORY_IN_VAL = interface->set_signal_valack_in (VAL); 63 out_MEMORY_IN_ACK = interface->set_signal_valack_out (ACK); 64 65 if (_param->_have_port_context_id) 66 in_MEMORY_IN_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id" ,_param->_size_context_id ); 67 if (_param->_have_port_front_end_id) 68 in_MEMORY_IN_FRONT_END_ID = interface->set_signal_in <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 69 if (_param->_have_port_ooo_engine_id) 70 in_MEMORY_IN_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id ); 71 if (_param->_have_port_packet_id) 72 in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 73 in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 74 in_MEMORY_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type ); 75 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage 76 if (_param->_have_port_load_queue_ptr) 77 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); 78 in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 ); 79 in_MEMORY_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); 80 in_MEMORY_IN_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); 81 in_MEMORY_IN_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); 82 in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); 83 in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); 84 in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,1 ); 85 in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); 86 in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 ); 58 ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); 59 ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK); 60 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 61 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 62 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 63 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 64 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 65 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 66 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 67 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 68 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 69 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 70 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); 71 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); 72 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 73 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,1 ); 75 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,1 ); 87 77 } 88 78 89 // ~~~~~[ 79 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 90 80 { 91 Interface_fifo * interface = _interfaces->set_interface("memory_out" 92 #ifdef POSITION 93 ,OUT 94 ,EAST 95 ,"Instruction to write queue" 96 #endif 97 ); 81 ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); 98 82 99 out_MEMORY_OUT_VAL = interface->set_signal_valack_out(VAL); 100 in_MEMORY_OUT_ACK = interface->set_signal_valack_in (ACK); 101 if (_param->_have_port_context_id) 102 out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id" ,_param->_size_context_id ); 103 if (_param->_have_port_front_end_id) 104 out_MEMORY_OUT_FRONT_END_ID = interface->set_signal_out <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 105 if (_param->_have_port_ooo_engine_id) 106 out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id ); 107 if (_param->_have_port_packet_id) 108 out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 109 // out_MEMORY_OUT_OPERATION = interface->set_signal_out <Toperation_t > ("operation" ,_param->_size_operation ); 110 out_MEMORY_OUT_TYPE = interface->set_signal_out <Ttype_t > ("type" ,_param->_size_type ); 111 out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); 112 out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); 113 out_MEMORY_OUT_DATA_RD = interface->set_signal_out <Tgeneral_data_t > ("data_rd" ,_param->_size_general_data ); 114 out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_re" ,1 ); 115 out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register ); 116 out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data ); 117 out_MEMORY_OUT_EXCEPTION = interface->set_signal_out <Texception_t > ("exception" ,_param->_size_exception ); 118 out_MEMORY_OUT_NO_SEQUENCE = interface->set_signal_out <Tcontrol_t > ("no_sequence" ,1 ); 119 out_MEMORY_OUT_ADDRESS = interface->set_signal_out <Tgeneral_data_t > ("address" ,_param->_size_general_data ); 83 ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); 84 ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK); 85 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 86 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 87 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 88 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 89 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 90 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 91 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 92 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 93 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); 94 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_general_register ); 96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_general_data ); 97 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 98 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); 120 100 } 121 101 122 // ~~~~~[ 102 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 123 103 { 124 Interface_fifo * interface = _interfaces->set_interface("dcache_req" 125 #ifdef POSITION 126 ,OUT 127 ,NORTH 128 ,"Request port to dcache" 129 #endif 130 ); 104 ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); 131 105 132 out_DCACHE_REQ_VAL = interface->set_signal_valack_out(VAL); 133 in_DCACHE_REQ_ACK = interface->set_signal_valack_in (ACK); 134 if (_param->_have_port_dcache_context_id) 135 out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 136 out_DCACHE_REQ_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 137 out_DCACHE_REQ_ADDRESS = interface->set_signal_out <Tdcache_address_t > ("address" ,_param->_size_general_data); 138 out_DCACHE_REQ_TYPE = interface->set_signal_out <Tdcache_type_t > ("type" ,_param->_size_dcache_type ); 139 out_DCACHE_REQ_WDATA = interface->set_signal_out <Tdcache_data_t > ("wdata" ,_param->_size_general_data); 106 ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); 107 ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); 108 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 109 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 110 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); 111 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); 112 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); 140 113 } 141 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 115 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 142 116 { 143 Interface_fifo * interface = _interfaces->set_interface("dcache_rsp" 144 #ifdef POSITION 145 ,IN 146 ,NORTH 147 ,"Respons port from dcache" 148 #endif 149 ); 117 ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); 150 118 151 in_DCACHE_RSP_VAL = interface->set_signal_valack_in (VAL); 152 out_DCACHE_RSP_ACK = interface->set_signal_valack_out(ACK); 153 if (_param->_have_port_dcache_context_id) 154 in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 155 in_DCACHE_RSP_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 156 in_DCACHE_RSP_RDATA = interface->set_signal_in <Tdcache_data_t > ("rdata" ,_param->_size_general_data); 157 in_DCACHE_RSP_ERROR = interface->set_signal_in <Tdcache_error_t> ("error" ,_param->_size_dcache_error); 119 ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); 120 ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); 121 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 122 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 123 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); 124 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); 158 125 } 159 // ~~~~~[ 126 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 127 161 // if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 162 { 163 out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_bypass_memory]; 164 if (_param->_have_port_ooo_engine_id) 165 out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_bypass_memory]; 166 out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory]; 167 out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_bypass_memory]; 168 169 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 170 { 171 Interface_fifo * interface = _interfaces->set_interface("memory_out" 172 #ifdef POSITION 173 ,OUT 174 ,NORTH 175 ,"Bypass between the load queue and the reservation station" 176 #endif 177 ); 128 { 129 ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); 178 130 179 out_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_out(VAL); 180 if (_param->_have_port_ooo_engine_id) 181 out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t > ("ooo_engine_id", _param->_size_ooo_engine_id); 182 out_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg" , _param->_size_general_register); 183 out_BYPASS_MEMORY_DATA [i] = interface->set_signal_out <Tgeneral_data_t > ("data" , _param->_size_general_data); 184 } 185 } 186 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); 132 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id ); 133 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); 134 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); 135 } 136 137 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; 140 141 // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; 142 // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; 143 // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; 144 // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; 145 146 // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; 147 // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; 148 // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; 149 150 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 187 151 188 152 #ifdef POSITION 189 _component->generate_file(); 153 if (usage_is_set(_usage,USE_POSITION)) 154 _component->generate_file(); 190 155 #endif 191 156 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r81 r88 6 6 * $Id$ 7 7 * 8 * [ 8 * [ Description ] 9 9 * 10 10 */ 11 11 12 12 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" 13 #include "Behavioural/include/Allocation.h" 13 14 14 15 namespace morpheo { … … 28 29 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 29 30 31 if (usage_is_set(_usage,USE_SYSTEMC)) 32 { 30 33 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) 31 34 delete in_CLOCK ; … … 33 36 delete in_NRESET; 34 37 35 delete in_MEMORY_IN_VAL ; 36 delete out_MEMORY_IN_ACK ; 37 if (_param->_have_port_context_id) 38 delete in_MEMORY_IN_CONTEXT_ID ; 39 if (_param->_have_port_front_end_id) 40 delete in_MEMORY_IN_FRONT_END_ID ; 41 if (_param->_have_port_ooo_engine_id) 42 delete in_MEMORY_IN_OOO_ENGINE_ID ; 43 if (_param->_have_port_packet_id) 44 delete in_MEMORY_IN_PACKET_ID ; 45 delete in_MEMORY_IN_OPERATION ; 46 delete in_MEMORY_IN_TYPE ; 47 delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 48 if (_param->_have_port_load_queue_ptr) 49 delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 50 delete in_MEMORY_IN_HAS_IMMEDIAT; 51 delete in_MEMORY_IN_IMMEDIAT ; 52 delete in_MEMORY_IN_DATA_RA ; 53 delete in_MEMORY_IN_DATA_RB ; 54 delete in_MEMORY_IN_DATA_RC ; 55 delete in_MEMORY_IN_WRITE_RD ; 56 delete in_MEMORY_IN_NUM_REG_RD ; 57 delete in_MEMORY_IN_WRITE_RE ; 58 delete in_MEMORY_IN_NUM_REG_RE ; 38 DELETE1_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory,1); 39 DELETE1_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory,1); 40 DELETE1_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); 41 DELETE1_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); 42 DELETE1_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); 43 DELETE1_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 44 DELETE1_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 45 DELETE1_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 46 DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr ); 47 DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr ); 48 DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory,1 ); 49 DELETE1_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory,_param->_size_general_data ); 50 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory,_param->_size_general_data ); 51 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory,_param->_size_general_data ); 52 DELETE1_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory,_param->_size_special_data ); 53 DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory,1 ); 54 DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory,1 ); 55 DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory,1 ); 56 DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory,1 ); 57 58 DELETE1_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory,1); 59 DELETE1_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory,1); 60 DELETE1_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); 61 DELETE1_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); 62 DELETE1_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); 63 DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); 64 // DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); 65 DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); 66 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); 67 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); 68 DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory,_param->_size_general_data ); 69 DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory,1 ); 70 DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory,_param->_size_general_register ); 71 DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory,_param->_size_general_data ); 72 DELETE1_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory,_param->_size_exception ); 73 DELETE1_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory,1 ); 74 DELETE1_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory,_param->_size_general_data ); 75 76 DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port,1); 77 DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port,1); 78 DELETE1_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); 79 DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); 80 DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port,_param->_size_general_data); 81 DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port,_param->_size_dcache_type ); 82 DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port,_param->_size_general_data); 83 84 DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port,1); 85 DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port,1); 86 DELETE1_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); 87 DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); 88 DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port,_param->_size_general_data); 89 DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port,_param->_size_dcache_error); 90 91 DELETE1_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory,1); 92 DELETE1_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory,_param->_size_ooo_engine_id ); 93 DELETE1_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory,_param->_size_general_register); 94 DELETE1_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory,_param->_size_general_data ); 95 96 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 97 60 delete out_MEMORY_OUT_VAL ; 61 delete in_MEMORY_OUT_ACK ; 62 if (_param->_have_port_context_id) 63 delete out_MEMORY_OUT_CONTEXT_ID; 64 if (_param->_have_port_front_end_id) 65 delete out_MEMORY_OUT_FRONT_END_ID; 66 if (_param->_have_port_ooo_engine_id) 67 delete out_MEMORY_OUT_OOO_ENGINE_ID; 68 if (_param->_have_port_packet_id) 69 delete out_MEMORY_OUT_PACKET_ID ; 70 // delete out_MEMORY_OUT_OPERATION ; 71 delete out_MEMORY_OUT_TYPE ; 72 delete out_MEMORY_OUT_WRITE_RD ; 73 delete out_MEMORY_OUT_NUM_REG_RD; 74 delete out_MEMORY_OUT_DATA_RD ; 75 delete out_MEMORY_OUT_WRITE_RE ; 76 delete out_MEMORY_OUT_NUM_REG_RE; 77 delete out_MEMORY_OUT_DATA_RE ; 78 delete out_MEMORY_OUT_EXCEPTION ; 79 delete out_MEMORY_OUT_NO_SEQUENCE; 80 delete out_MEMORY_OUT_ADDRESS ; 98 // delete [] internal_MEMORY_IN_ACK ; 99 // delete [] internal_MEMORY_OUT_VAL ; 100 // delete [] internal_MEMORY_OUT_SELECT_QUEUE; 101 // delete [] internal_MEMORY_OUT_PTR ; 81 102 82 delete out_DCACHE_REQ_VAL ; 83 delete in_DCACHE_REQ_ACK ; 84 if (_param->_have_port_dcache_context_id) 85 delete out_DCACHE_REQ_CONTEXT_ID; 86 delete out_DCACHE_REQ_PACKET_ID ; 87 delete out_DCACHE_REQ_ADDRESS ; 88 delete out_DCACHE_REQ_TYPE ; 89 delete out_DCACHE_REQ_WDATA ; 90 91 delete in_DCACHE_RSP_VAL ; 92 delete out_DCACHE_RSP_ACK ; 93 if (_param->_have_port_dcache_context_id) 94 delete in_DCACHE_RSP_CONTEXT_ID; 95 delete in_DCACHE_RSP_PACKET_ID ; 96 delete in_DCACHE_RSP_RDATA ; 97 delete in_DCACHE_RSP_ERROR ; 98 99 delete [] out_BYPASS_MEMORY_VAL ; 100 if (_param->_have_port_ooo_engine_id) 101 delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; 102 delete [] out_BYPASS_MEMORY_NUM_REG ; 103 delete [] out_BYPASS_MEMORY_DATA ; 104 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 // delete [] internal_DCACHE_RSP_ACK ; 104 // delete [] internal_DCACHE_REQ_VAL ; 105 // delete [] internal_DCACHE_REQ_SELECT_QUEUE; 106 107 // delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ; 108 } 109 110 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 111 106 112 delete _component; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp
r81 r88 26 26 27 27 #ifdef STATISTICS 28 _stat->end_cycle(); 28 if (usage_is_set(_usage,USE_STATISTICS)) 29 _stat->end_cycle(); 29 30 #endif 30 31 … … 32 33 // Evaluation before read the ouput signal 33 34 // sc_start(0); 34 _interfaces->testbench(); 35 if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) 36 _interfaces->testbench(); 35 37 #endif 36 38 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
r81 r88 27 27 28 28 // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 30 // Initialisation 31 internal_MEMORY_IN_PORT = 0; 32 Tcontrol_t ack [_param->_nb_inst_memory]; 33 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 34 ack [i] = 0; 29 35 36 // find first valid entry 30 37 // store queue is never full (pointer is manage by rename stage) 31 internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) or not _speculative_access_queue_control->full(); 38 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 39 if (PORT_READ(in_MEMORY_IN_VAL [i])) 40 { 41 internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full(); 32 42 33 PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK); 43 if (internal_MEMORY_IN_ACK) 44 { 45 ack [i] = 1; 46 internal_MEMORY_IN_PORT = i; 47 break; // end 48 } 49 } 50 51 for (uint32_t i=0; i<_param->_nb_inst_memory; i++) 52 PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); 34 53 35 54 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r81 r88 4 4 * $Id$ 5 5 * 6 * [ 6 * [ Description ] 7 7 * 8 8 */ … … 26 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 27 27 28 // ~~~~~[ 28 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29 29 30 30 Tcontext_t memory_out_context_id = 0; … … 110 110 } 111 111 // write output 112 PORT_WRITE(out_MEMORY_OUT_VAL , internal_MEMORY_OUT_VAL);112 PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); 113 113 114 114 if (_param->_have_port_context_id) 115 PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID , memory_out_context_id );115 PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID [0], memory_out_context_id ); 116 116 if (_param->_have_port_front_end_id) 117 PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID , memory_out_front_end_id );117 PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id ); 118 118 if (_param->_have_port_ooo_engine_id) 119 PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID, memory_out_ooo_engine_id); 120 if (_param->_have_port_packet_id) 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation ); 123 PORT_WRITE(out_MEMORY_OUT_TYPE , TYPE_MEMORY ); 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD , memory_out_num_reg_rd ); 126 PORT_WRITE(out_MEMORY_OUT_DATA_RD , memory_out_data_rd ); 127 // PORT_WRITE(out_MEMORY_OUT_WRITE_RE , memory_out_write_re ); 128 // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , memory_out_num_reg_re ); 129 // PORT_WRITE(out_MEMORY_OUT_DATA_RE , memory_out_data_re ); 130 PORT_WRITE(out_MEMORY_OUT_WRITE_RE , 0); 131 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , 0); 132 PORT_WRITE(out_MEMORY_OUT_DATA_RE , 0); 133 PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); 134 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE , 0); 135 PORT_WRITE(out_MEMORY_OUT_ADDRESS , 0); 136 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 119 PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id); 120 if (_param->_have_port_rob_ptr) 121 PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); 122 // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); 123 PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); 124 PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); 125 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); 126 PORT_WRITE(out_MEMORY_OUT_DATA_RD [0], memory_out_data_rd ); 127 // PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], memory_out_write_re ); 128 // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], memory_out_num_reg_re ); 129 // PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], memory_out_data_re ); 130 PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], 0); 131 PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], 0); 132 PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); 133 PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); 134 PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], 0); 135 PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); 136 137 // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 138 138 139 Tcontext_t dcache_req_context_id; … … 201 202 } 202 203 203 PORT_WRITE(out_DCACHE_REQ_VAL , internal_DCACHE_REQ_VAL);204 PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL); 204 205 if (_param->_have_port_dcache_context_id) 205 PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID , dcache_req_context_id);206 PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );207 PORT_WRITE(out_DCACHE_REQ_ADDRESS , dcache_req_address );208 PORT_WRITE(out_DCACHE_REQ_TYPE , dcache_req_type );209 PORT_WRITE(out_DCACHE_REQ_WDATA , dcache_req_wdata );206 PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id); 207 PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id ); 208 PORT_WRITE(out_DCACHE_REQ_ADDRESS [0], dcache_req_address ); 209 PORT_WRITE(out_DCACHE_REQ_TYPE [0], dcache_req_type ); 210 PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); 210 211 211 212 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r81 r88 255 255 // Interface "MEMORY_IN" 256 256 //================================================================ 257 258 if ((PORT_READ(in_MEMORY_IN_VAL ) == 1) and257 258 if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and 259 259 ( internal_MEMORY_IN_ACK == 1)) 260 260 { … … 266 266 267 267 #ifdef DEBUG_TEST 268 if (PORT_READ(in_MEMORY_IN_TYPE ) != TYPE_MEMORY)268 if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) 269 269 throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); 270 270 #endif 271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION );272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT ) +273 PORT_READ(in_MEMORY_IN_DATA_RA ));271 Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); 272 Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + 273 PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); 274 274 bool exception_alignement = (mask_memory_access(operation) & address) != 0; 275 275 … … 287 287 288 288 // Write pointer is define in rename stage : 289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );289 Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 290 290 log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); 291 291 … … 375 375 log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); 376 376 377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );380 _store_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);377 _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 378 _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 379 _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 380 _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 381 381 _store_queue [index]._operation = operation; 382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );382 _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 383 383 _store_queue [index]._address = address; 384 384 385 385 // reordering data 386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB ), memory_size(operation), 0);387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );386 _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); 387 // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 388 388 } 389 389 } … … 413 413 // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) 414 414 _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; 415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID );416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID );417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID );418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_ packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);415 _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); 416 _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); 417 _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); 418 _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); 419 419 420 420 _speculative_access_queue [index]._operation = operation; 421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE );422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE );421 _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 422 _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); 423 423 _speculative_access_queue [index]._address = address; 424 424 // NOTE : is operation is a load, then they are a result and must write in the register file 425 425 _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); 426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD );426 _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); 427 427 428 428 _speculative_access_queue [index]._exception = exception; … … 437 437 438 438 if (( internal_MEMORY_OUT_VAL == 1) and 439 (PORT_READ(in_MEMORY_OUT_ACK ) == 1))439 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 440 440 { 441 441 log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); … … 495 495 496 496 if (( internal_DCACHE_REQ_VAL == 1) and 497 (PORT_READ(in_DCACHE_REQ_ACK ) == 1))497 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 498 498 { 499 499 log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); … … 598 598 // Interface "DCACHE_RSP" 599 599 //================================================================ 600 if ((PORT_READ(in_DCACHE_RSP_VAL )== 1) and600 if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and 601 601 ( internal_DCACHE_RSP_ACK == 1)) 602 602 { … … 604 604 605 605 // don't use context_id : because there are one queue for all thread 606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID );607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID );608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA );609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR );606 //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 607 Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); 608 Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); 609 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 610 610 611 611 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); … … 662 662 663 663 664 #if DEBUG>=DEBUG_TRACE664 #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) 665 665 // ***** dump store queue 666 666 std::cout << "Dump STORE_QUEUE :" << std::endl … … 694 694 << _load_queue[j] << std::endl; 695 695 } 696 697 696 #endif 698 697 699 698 #ifdef STATISTICS 700 for (uint32_t i=0; i<_param->_size_store_queue; i++) 701 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 702 (*_stat_use_store_queue) ++; 703 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 704 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 705 (*_stat_use_speculative_access_queue) ++; 706 for (uint32_t i=0; i<_param->_size_load_queue; i++) 707 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 708 (*_stat_use_load_queue) ++; 699 if (usage_is_set(_usage,USE_STATISTICS)) 700 { 701 for (uint32_t i=0; i<_param->_size_store_queue; i++) 702 if (_store_queue[i]._state != STORE_QUEUE_EMPTY) 703 (*_stat_use_store_queue) ++; 704 for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) 705 if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) 706 (*_stat_use_speculative_access_queue) ++; 707 for (uint32_t i=0; i<_param->_size_load_queue; i++) 708 if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) 709 (*_stat_use_load_queue) ++; 710 } 709 711 #endif 710 712 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r81 r88 26 26 Tspeculative_load_t speculative_load , 27 27 uint32_t nb_bypass_memory , 28 uint32_t nb_cache_port , 29 uint32_t nb_inst_memory , 28 30 uint32_t nb_context , 29 31 uint32_t nb_front_end , … … 33 35 uint32_t size_special_data , 34 36 uint32_t nb_general_register , 35 uint32_t nb_special_register ): 36 _size_store_queue (size_store_queue ), 37 _size_load_queue (size_load_queue ), 38 _size_speculative_access_queue (size_speculative_access_queue), 39 _nb_port_check (nb_port_check ), 40 _speculative_load (speculative_load ), 41 _nb_bypass_memory (nb_bypass_memory ), 42 _nb_context (nb_context ), 43 _nb_front_end (nb_front_end ), 44 _nb_ooo_engine (nb_ooo_engine ), 45 _nb_packet (nb_packet ), 46 _size_general_data (size_general_data ), 47 _size_special_data (size_special_data ), 48 _nb_general_register (nb_general_register ), 49 _nb_special_register (nb_special_register ), 50 51 _size_address_store_queue (log2(size_store_queue )), 52 _size_address_load_queue (log2(size_load_queue )), 53 _size_address_speculative_access_queue (log2(size_speculative_access_queue)), 54 55 _size_context_id (log2(nb_context )), 56 _size_front_end_id (log2(nb_front_end )), 57 _size_ooo_engine_id (log2(nb_ooo_engine )), 58 _size_packet_id (log2(nb_packet )), 59 _size_general_register (log2(nb_general_register)), 60 _size_special_register (log2(nb_special_register)), 61 _size_dcache_context_id (_size_context_id + _size_front_end_id + _size_ooo_engine_id), 62 _size_dcache_packet_id ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1), 63 64 _have_port_context_id (_size_context_id >0), 65 _have_port_front_end_id (_size_front_end_id >0), 66 _have_port_ooo_engine_id (_size_ooo_engine_id>0), 67 _have_port_packet_id (_size_packet_id >0), 68 _have_port_dcache_context_id (_size_dcache_context_id>0), 69 _have_port_load_queue_ptr (_size_load_queue>1), 70 71 _mask_address_lsb (gen_mask<Tdcache_address_t>(log2(size_general_data/8))), 72 _mask_address_msb (gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8)) 37 uint32_t nb_special_register , 38 bool is_toplevel) 73 39 { 74 40 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 41 42 _size_store_queue = size_store_queue ; 43 _size_load_queue = size_load_queue ; 44 _size_speculative_access_queue = size_speculative_access_queue; 45 _nb_port_check = nb_port_check ; 46 _speculative_load = speculative_load ; 47 _nb_bypass_memory = nb_bypass_memory ; 48 _nb_cache_port = nb_cache_port ; 49 _nb_inst_memory = nb_inst_memory ; 50 _nb_context = nb_context ; 51 _nb_front_end = nb_front_end ; 52 _nb_ooo_engine = nb_ooo_engine ; 53 _nb_packet = nb_packet ; 54 _nb_general_register = nb_general_register ; 55 _nb_special_register = nb_special_register ; 56 57 _size_speculative_access_queue_ptr = log2(size_speculative_access_queue); 58 59 _size_dcache_context_id = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine); 60 _size_dcache_packet_id = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1; 61 62 _have_port_dcache_context_id = _size_dcache_context_id>0; 63 64 _mask_address_lsb = gen_mask<Tdcache_address_t>(log2(size_general_data/8)); 65 _mask_address_msb = gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8); 66 75 67 test(); 68 69 if (is_toplevel) 70 { 71 _size_context_id = log2(nb_context ); 72 _size_front_end_id = log2(nb_front_end ); 73 _size_ooo_engine_id = log2(nb_ooo_engine ); 74 _size_rob_ptr = log2(nb_packet ); 75 _size_general_register = log2(nb_general_register); 76 _size_special_register = log2(nb_special_register); 77 _size_store_queue_ptr = log2(size_store_queue ); 78 _size_load_queue_ptr = log2(size_load_queue ); 79 _size_general_data = size_general_data ; 80 _size_special_data = size_special_data ; 81 82 _have_port_context_id = _size_context_id >0; 83 _have_port_front_end_id = _size_front_end_id >0; 84 _have_port_ooo_engine_id = _size_ooo_engine_id >0; 85 _have_port_rob_ptr = _size_rob_ptr >0; 86 _have_port_load_queue_ptr = _size_load_queue_ptr>0; 87 88 copy(); 89 } 90 76 91 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 77 92 }; 78 93 94 // #undef FUNCTION 95 // #define FUNCTION "Load_store_unit::Parameters (copy)" 96 // Parameters::Parameters (Parameters & param): 97 // _size_store_queue (param._size_store_queue ), 98 // _size_load_queue (param._size_load_queue ), 99 // _size_speculative_access_queue (param._size_speculative_access_queue), 100 // _nb_port_check (param._nb_port_check ), 101 // _speculative_load (param._speculative_load ), 102 // _nb_bypass_memory (param._nb_bypass_memory ), 103 // _nb_cache_port (param._nb_cache_port ), 104 // _nb_inst_memory (param._nb_inst_memory ), 105 // _nb_context (param._nb_context ), 106 // _nb_front_end (param._nb_front_end ), 107 // _nb_ooo_engine (param._nb_ooo_engine ), 108 // _nb_packet (param._nb_packet ), 109 // _size_general_data (param._size_general_data ), 110 // _size_special_data (param._size_special_data ), 111 // _nb_general_register (param._nb_general_register ), 112 // _nb_special_register (param._nb_special_register ), 113 114 // _size_address_store_queue (param._size_address_store_queue ), 115 // _size_address_load_queue (param._size_address_load_queue ), 116 // _size_address_speculative_access_queue (param._size_address_speculative_access_queue), 117 118 // _size_context_id (param._size_context_id ), 119 // _size_front_end_id (param._size_front_end_id ), 120 // _size_ooo_engine_id (param._size_ooo_engine_id ), 121 // _size_packet_id (param._size_packet_id ), 122 // _size_general_register (param._size_general_register ), 123 // _size_special_register (param._size_special_register ), 124 // _size_dcache_context_id (param._size_dcache_context_id ), 125 // _size_dcache_packet_id (param._size_dcache_packet_id ), 126 127 // _have_port_context_id (param._have_port_context_id ), 128 // _have_port_front_end_id (param._have_port_front_end_id ), 129 // _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 130 // _have_port_packet_id (param._have_port_packet_id ), 131 // _have_port_dcache_context_id(param._have_port_dcache_context_id), 132 // _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 133 134 // _mask_address_lsb (param._mask_address_lsb), 135 // _mask_address_msb (param._mask_address_msb) 136 // { 137 // log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 138 // test(); 139 // log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 140 // }; 141 79 142 #undef FUNCTION 80 #define FUNCTION "Load_store_unit::Parameters (copy)" 81 Parameters::Parameters (Parameters & param): 82 _size_store_queue (param._size_store_queue ), 83 _size_load_queue (param._size_load_queue ), 84 _size_speculative_access_queue (param._size_speculative_access_queue), 85 _nb_port_check (param._nb_port_check ), 86 _speculative_load (param._speculative_load ), 87 _nb_bypass_memory (param._nb_bypass_memory ), 88 _nb_context (param._nb_context ), 89 _nb_front_end (param._nb_front_end ), 90 _nb_ooo_engine (param._nb_ooo_engine ), 91 _nb_packet (param._nb_packet ), 92 _size_general_data (param._size_general_data ), 93 _size_special_data (param._size_special_data ), 94 _nb_general_register (param._nb_general_register ), 95 _nb_special_register (param._nb_special_register ), 96 97 _size_address_store_queue (param._size_address_store_queue ), 98 _size_address_load_queue (param._size_address_load_queue ), 99 _size_address_speculative_access_queue (param._size_address_speculative_access_queue), 100 101 _size_context_id (param._size_context_id ), 102 _size_front_end_id (param._size_front_end_id ), 103 _size_ooo_engine_id (param._size_ooo_engine_id ), 104 _size_packet_id (param._size_packet_id ), 105 _size_general_register (param._size_general_register ), 106 _size_special_register (param._size_special_register ), 107 _size_dcache_context_id (param._size_dcache_context_id ), 108 _size_dcache_packet_id (param._size_dcache_packet_id ), 109 110 _have_port_context_id (param._have_port_context_id ), 111 _have_port_front_end_id (param._have_port_front_end_id ), 112 _have_port_ooo_engine_id (param._have_port_ooo_engine_id), 113 _have_port_packet_id (param._have_port_packet_id ), 114 _have_port_dcache_context_id(param._have_port_dcache_context_id), 115 _have_port_load_queue_ptr(param._have_port_load_queue_ptr), 116 117 _mask_address_lsb (param._mask_address_lsb), 118 _mask_address_msb (param._mask_address_msb) 143 #define FUNCTION "Load_store_unit::~Parameters" 144 Parameters::~Parameters (void) 119 145 { 120 146 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 121 test();122 147 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); 123 148 }; 124 149 125 150 #undef FUNCTION 126 #define FUNCTION "Load_store_unit:: ~Parameters"127 Parameters::~Parameters ()151 #define FUNCTION "Load_store_unit::copy" 152 void Parameters::copy (void) 128 153 { 129 154 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
r81 r88 32 32 { 33 33 if (not (_nb_bypass_memory == 0)) 34 test.error( "Bypass memory is not supported. Please wait a next revision.");34 test.error(_("Bypass memory is not supported. Please wait a next revision.\n")); 35 35 36 36 break; … … 42 42 { 43 43 if (not (_nb_bypass_memory == 0)) 44 test.error( "In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");44 test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str())); 45 45 46 test.error( "Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");46 test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str())); 47 47 break; 48 48 } … … 50 50 51 51 if (not (_size_store_queue >= 2)) 52 test.error( "Store queue must have at less two slot.");52 test.error(_("Store queue must have at less two slot.\n")); 53 53 54 54 if (not (_nb_bypass_memory <= _size_load_queue)) 55 test.error("Bypass number must be less than load_queue's size."); 55 test.error(_("Bypass number must be less than load_queue's size.\n")); 56 57 if (_nb_cache_port > 1) 58 test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); 59 60 if (_nb_inst_memory > 1) 61 test.warning(_("nb_inst_memory > 1 is unsupported (Coming Soon).\n")); 56 62 57 63 log_printf(FUNC,Load_store_unit,FUNCTION,"End");
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