- Timestamp:
- Dec 19, 2008, 4:34:00 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 1 deleted
- 28 edited
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Context_State/SelfTest/src/test.cpp (modified) (4 diffs)
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Context_State/include/Context_State.h (modified) (1 diff)
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Context_State/src/Context_State_allocation.cpp (modified) (2 diffs)
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Context_State/src/Context_State_deallocation.cpp (modified) (1 diff)
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Context_State/src/Context_State_genMoore.cpp (modified) (3 diffs)
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Decod_unit/Decod/Instruction/src/Instruction.cpp (modified) (131 diffs)
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Front_end_Glue/SelfTest/src/test.cpp (modified) (6 diffs)
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Front_end_Glue/include/Front_end_Glue.h (modified) (2 diffs)
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Front_end_Glue/src/Front_end_Glue.cpp (modified) (1 diff)
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Front_end_Glue/src/Front_end_Glue_allocation.cpp (modified) (2 diffs)
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Front_end_Glue/src/Front_end_Glue_deallocation.cpp (modified) (2 diffs)
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Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp (modified) (1 diff)
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Prediction_unit/SelfTest/src/test.cpp (modified) (3 diffs)
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Prediction_unit/Update_Prediction_Table/Makefile.deps (modified) (1 diff)
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Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg (deleted)
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Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (modified) (8 diffs)
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Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (modified) (3 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (modified) (2 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (modified) (2 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (modified) (2 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (modified) (3 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp (modified) (2 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp (modified) (2 diffs)
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Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (modified) (5 diffs)
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Prediction_unit/include/Prediction_unit.h (modified) (1 diff)
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Prediction_unit/src/Prediction_unit_allocation.cpp (modified) (2 diffs)
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Prediction_unit/src/Prediction_unit_deallocation.cpp (modified) (1 diff)
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SelfTest/src/test.cpp (modified) (1 diff)
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src/Front_end_allocation.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r95 r97 75 75 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 76 76 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",T address_t);77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t); 78 78 79 79 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 97 97 ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context ); 98 98 ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context ); 99 99 ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context ); 100 ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context ); 101 100 102 ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); 101 103 ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context ); … … 177 179 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); 178 180 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 181 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context ); 182 if (_param->_have_port_depth) 183 INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context ); 179 184 180 185 INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context ); … … 1273 1278 DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); 1274 1279 DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context ); 1280 DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context ); 1281 DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context ); 1275 1282 DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context ); 1276 1283 DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r95 r97 93 93 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; 94 94 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; 95 public : SC_IN (T address_t) * in_COMMIT_EVENT_ADDRESS_EEAR ;95 public : SC_IN (Tgeneral_data_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; 96 96 97 97 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r95 r97 97 97 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 98 98 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); 99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,T address_t ,_param->_size_instruction_address);99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); 100 100 } 101 101 … … 133 133 ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t ,1); 134 134 ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t ,1); 135 ALLOC1_SIGNAL_OUT(out_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); 136 ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 137 135 138 } 136 139 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r95 r97 76 76 DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 77 77 DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1); 78 78 DELETE1_SIGNAL(out_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type); 79 DELETE1_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 80 79 81 DELETE1_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context,1); 80 82 DELETE1_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r88 r97 38 38 // SR can't change in this cycle 39 39 // Exception Prefix High 40 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);41 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i];42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]);40 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); 41 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; 42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); 43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); 44 44 // excep : address exception 45 45 // miss : address delay_slot, and address dest 46 46 // psync : address next 47 47 // csync : address next 48 Tevent_type_t type ;//[nb_context] 49 Tdepth_t depth = reg_EVENT_DEPTH [i]; 50 51 switch (state) 52 { 53 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 54 case CONTEXT_STATE_KO_MISS_ADDR : (type = EVENT_TYPE_MISS_SPECULATION ); break; 55 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 56 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 57 default : (type = EVENT_TYPE_NONE ); break; 58 } 59 // (type = EVENT_TYPE_SPR_ACCESS ); 60 // (type = EVENT_TYPE_MSYNC ); 61 // (type = EVENT_TYPE_BRANCH_NO_ACCURATE); 62 48 63 internal_EVENT_VAL [i] = val; 49 64 PORT_WRITE(out_EVENT_VAL [i], val); … … 52 67 PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); 53 68 PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); 69 PORT_WRITE(out_EVENT_TYPE [i], type); 70 if (_param->_have_port_depth) 71 PORT_WRITE(out_EVENT_DEPTH [i], depth); 54 72 55 73 log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); … … 59 77 log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); 60 78 log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); 79 log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type); 80 log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth); 61 81 } 62 82 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
r88 r97 255 255 inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; 256 256 inst->_has_immediat = 0; 257 // inst->_immediat = ; 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 // inst->_num_reg_rc = ; 257 inst->_immediat = 0; // unnecessary 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 inst->_num_reg_rc = 0; //unnecessary 264 264 inst->_write_rd = 1; 265 265 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 271 271 // inst->_branch_stack_write = ; 272 272 // inst->_branch_direction = ; 273 // inst->_address_next = ; 273 // inst->_address_next = ; // already define : PC+4 274 274 inst->_no_execute = 0; 275 275 inst->_event_type = EVENT_TYPE_NONE; … … 283 283 inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; 284 284 inst->_has_immediat = 0; 285 // inst->_immediat = ; 285 inst->_immediat = 0; // unnecessary 286 286 inst->_read_ra = 1; 287 287 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 299 299 // inst->_branch_stack_write = ; 300 300 // inst->_branch_direction = ; 301 // inst->_address_next = ; 301 // inst->_address_next = ; // already define : PC+4 302 302 inst->_no_execute = 0; 303 303 inst->_event_type = EVENT_TYPE_NONE; … … 315 315 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 316 316 inst->_read_rb = 0; 317 // inst->_num_reg_rb = ; 318 inst->_read_rc = 0; 319 // inst->_num_reg_rc = ; 317 inst->_num_reg_rb = 0; //unnecessary 318 inst->_read_rc = 0; 319 inst->_num_reg_rc = 0; //unnecessary 320 320 inst->_write_rd = 1; 321 321 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 327 327 // inst->_branch_stack_write = ; 328 328 // inst->_branch_direction = ; 329 // inst->_address_next = ; 329 // inst->_address_next = ; // already define : PC+4 330 330 inst->_no_execute = 0; 331 331 inst->_event_type = EVENT_TYPE_NONE; … … 343 343 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 344 344 inst->_read_rb = 0; 345 // inst->_num_reg_rb = ; 345 inst->_num_reg_rb = 0; //unnecessary 346 346 inst->_read_rc = 1; 347 347 inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; … … 355 355 // inst->_branch_stack_write = ; 356 356 // inst->_branch_direction = ; 357 // inst->_address_next = ; 357 // inst->_address_next = ; // already define : PC+4 358 358 inst->_no_execute = 0; 359 359 inst->_event_type = EVENT_TYPE_NONE; … … 367 367 inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; 368 368 inst->_has_immediat = 0; 369 // inst->_immediat = ; 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 // inst->_num_reg_rc = ; 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 // inst->_num_reg_re = ; 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; 369 inst->_immediat = 0; // unnecessary 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 inst->_num_reg_rc = 0; //unnecessary 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 inst->_num_reg_re = 0; //unnecessary 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; // already define : PC+4 386 386 inst->_no_execute = 0; 387 387 inst->_event_type = EVENT_TYPE_NONE; … … 399 399 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 400 400 inst->_read_rb = 0; 401 // inst->_num_reg_rb = ; 402 inst->_read_rc = 0; 403 // inst->_num_reg_rc = ; 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 // inst->_num_reg_re = ; 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; 401 inst->_num_reg_rb = 0; //unnecessary 402 inst->_read_rc = 0; 403 inst->_num_reg_rc = 0; //unnecessary 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 inst->_num_reg_re = 0; //unnecessary 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; // already define : PC+4 414 414 inst->_no_execute = 0; 415 415 inst->_event_type = EVENT_TYPE_NONE; … … 428 428 inst->_immediat = address_next; 429 429 inst->_read_ra = 0; 430 // inst->_num_reg_ra = ; 431 inst->_read_rb = 0; 432 // inst->_num_reg_rb = ; 430 inst->_num_reg_ra = 0; //unnecessary 431 inst->_read_rb = 0; 432 inst->_num_reg_rb = 0; //unnecessary 433 433 inst->_read_rc = 1; 434 434 inst->_num_reg_rc = SPR_LOGIC_SR_F; 435 435 inst->_write_rd = 0; 436 // inst->_num_reg_rd = ; 437 inst->_write_re = 0; 438 // inst->_num_reg_re = ; 436 inst->_num_reg_rd = 0; //unnecessary 437 inst->_write_re = 0; 438 inst->_num_reg_re = 0; //unnecessary 439 439 inst->_exception_use = EXCEPTION_USE_NONE; 440 440 inst->_exception = EXCEPTION_DECOD_NONE; … … 460 460 inst->_immediat = address_next; 461 461 inst->_read_ra = 0; 462 // inst->_num_reg_ra = ; 463 inst->_read_rb = 0; 464 // inst->_num_reg_rb = ; 462 inst->_num_reg_ra = 0; //unnecessary 463 inst->_read_rb = 0; 464 inst->_num_reg_rb = 0; //unnecessary 465 465 inst->_read_rc = 1; 466 466 inst->_num_reg_rc = SPR_LOGIC_SR_F; … … 468 468 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 469 469 inst->_write_re = 0; 470 // inst->_num_reg_re = ; 470 inst->_num_reg_re = 0; //unnecessary 471 471 inst->_exception_use = EXCEPTION_USE_NONE; 472 472 inst->_exception = EXCEPTION_DECOD_NONE; … … 486 486 inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; 487 487 inst->_has_immediat = 0; 488 // inst->_immediat = ; 488 inst->_immediat = 0; // unnecessary 489 489 inst->_read_ra = 1; 490 490 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 496 496 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 497 497 inst->_write_re = 0; 498 // inst->_num_reg_re = ; 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; 498 inst->_num_reg_re = 0; //unnecessary 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; // already define : PC+4 505 505 inst->_no_execute = 0; 506 506 inst->_event_type = EVENT_TYPE_NONE; … … 520 520 inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; 521 521 inst->_has_immediat = 0; 522 // inst->_immediat = ; 522 inst->_immediat = 0; // unnecessary 523 523 inst->_read_ra = 0; 524 // inst->_num_reg_ra = ; 525 inst->_read_rb = 0; 526 // inst->_num_reg_rb = ; 527 inst->_read_rc = 0; 528 // inst->_num_reg_rc = ; 529 inst->_write_rd = 0; 530 // inst->_num_reg_rd = ; 531 inst->_write_re = 0; 532 // inst->_num_reg_re = ; 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // don't change524 inst->_num_reg_ra = 0; //unnecessary 525 inst->_read_rb = 0; 526 inst->_num_reg_rb = 0; //unnecessary 527 inst->_read_rc = 0; 528 inst->_num_reg_rc = 0; //unnecessary 529 inst->_write_rd = 0; 530 inst->_num_reg_rd = 0; //unnecessary 531 inst->_write_re = 0; 532 inst->_num_reg_re = 0; //unnecessary 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // already define : PC+4 // don't change 539 539 inst->_no_execute = 0; 540 540 inst->_event_type = EVENT_TYPE_CSYNC; … … 558 558 inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; 559 559 inst->_has_immediat = 0; 560 // inst->_immediat = ; 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 // inst->_num_reg_rc = ; 560 inst->_immediat = 0; // unnecessary 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 inst->_num_reg_rc = 0; //unnecessary 567 567 inst->_write_rd = 1; 568 568 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 574 574 // inst->_branch_stack_write = ; 575 575 // inst->_branch_direction = ; 576 // inst->_address_next = ; 576 // inst->_address_next = ; // already define : PC+4 577 577 inst->_no_execute = 0; 578 578 inst->_event_type = EVENT_TYPE_NONE; … … 586 586 inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; 587 587 inst->_has_immediat = 0; 588 // inst->_immediat = ; 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 // inst->_num_reg_rc = ; 588 inst->_immediat = 0; // unnecessary 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 inst->_num_reg_rc = 0; //unnecessary 595 595 inst->_write_rd = 1; 596 596 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 602 602 // inst->_branch_stack_write = ; 603 603 // inst->_branch_direction = ; 604 // inst->_address_next = ; 604 // inst->_address_next = ; // already define : PC+4 605 605 inst->_no_execute = 0; 606 606 inst->_event_type = EVENT_TYPE_NONE; … … 618 618 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 619 619 inst->_read_rb = 0; 620 // inst->_num_reg_rb = ; 621 inst->_read_rc = 0; 622 // inst->_num_reg_rc = ; 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 // inst->_num_reg_re = ; 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; 620 inst->_num_reg_rb = 0; //unnecessary 621 inst->_read_rc = 0; 622 inst->_num_reg_rc = 0; //unnecessary 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 inst->_num_reg_re = 0; //unnecessary 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; // already define : PC+4 633 633 inst->_no_execute = 0; 634 634 inst->_event_type = EVENT_TYPE_NONE; … … 646 646 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 647 647 inst->_read_rb = 0; 648 // inst->_num_reg_rb = ; 649 inst->_read_rc = 0; 650 // inst->_num_reg_rc = ; 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 // inst->_num_reg_re = ; 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; 648 inst->_num_reg_rb = 0; //unnecessary 649 inst->_read_rc = 0; 650 inst->_num_reg_rc = 0; //unnecessary 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 inst->_num_reg_re = 0; //unnecessary 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; // already define : PC+4 661 661 inst->_no_execute = 0; 662 662 inst->_event_type = EVENT_TYPE_NONE; … … 674 674 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 675 675 inst->_read_rb = 0; 676 // inst->_num_reg_rb = ; 677 inst->_read_rc = 0; 678 // inst->_num_reg_rc = ; 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 // inst->_num_reg_re = ; 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; 676 inst->_num_reg_rb = 0; //unnecessary 677 inst->_read_rc = 0; 678 inst->_num_reg_rc = 0; //unnecessary 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 inst->_num_reg_re = 0; //unnecessary 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; // already define : PC+4 689 689 inst->_no_execute = 0; 690 690 inst->_event_type = EVENT_TYPE_NONE; … … 702 702 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 703 703 inst->_read_rb = 0; 704 // inst->_num_reg_rb = ; 705 inst->_read_rc = 0; 706 // inst->_num_reg_rc = ; 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 // inst->_num_reg_re = ; 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; 704 inst->_num_reg_rb = 0; //unnecessary 705 inst->_read_rc = 0; 706 inst->_num_reg_rc = 0; //unnecessary 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 inst->_num_reg_re = 0; //unnecessary 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; // already define : PC+4 717 717 inst->_no_execute = 0; 718 718 inst->_event_type = EVENT_TYPE_NONE; … … 730 730 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 731 731 inst->_read_rb = 0; 732 // inst->_num_reg_rb = ; 733 inst->_read_rc = 0; 734 // inst->_num_reg_rc = ; 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 // inst->_num_reg_re = ; 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; 732 inst->_num_reg_rb = 0; //unnecessary 733 inst->_read_rc = 0; 734 inst->_num_reg_rc = 0; //unnecessary 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 inst->_num_reg_re = 0; //unnecessary 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; // already define : PC+4 745 745 inst->_no_execute = 0; 746 746 inst->_event_type = EVENT_TYPE_NONE; … … 758 758 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 759 759 inst->_read_rb = 0; 760 // inst->_num_reg_rb = ; 761 inst->_read_rc = 0; 762 // inst->_num_reg_rc = ; 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 // inst->_num_reg_re = ; 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; 760 inst->_num_reg_rb = 0; //unnecessary 761 inst->_read_rc = 0; 762 inst->_num_reg_rc = 0; //unnecessary 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 inst->_num_reg_re = 0; //unnecessary 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; // already define : PC+4 773 773 inst->_no_execute = 0; 774 774 inst->_event_type = EVENT_TYPE_NONE; … … 782 782 inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; 783 783 inst->_has_immediat = 0; 784 // inst->_immediat = ; 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 // inst->_num_reg_rb = ; 789 inst->_read_rc = 0; 790 // inst->_num_reg_rc = ; 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 // inst->_num_reg_re = ; 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; 784 inst->_immediat = 0; // unnecessary 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 inst->_num_reg_rb = 0; //unnecessary 789 inst->_read_rc = 0; 790 inst->_num_reg_rc = 0; //unnecessary 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 inst->_num_reg_re = 0; //unnecessary 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; // already define : PC+4 801 801 inst->_no_execute = 0; 802 802 inst->_event_type = EVENT_TYPE_NONE; … … 810 810 inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; 811 811 inst->_has_immediat = 0; 812 // inst->_immediat = ; 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 // inst->_num_reg_rb = ; 817 inst->_read_rc = 0; 818 // inst->_num_reg_rc = ; 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 // inst->_num_reg_re = ; 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; 812 inst->_immediat = 0; // unnecessary 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 inst->_num_reg_rb = 0; //unnecessary 817 inst->_read_rc = 0; 818 inst->_num_reg_rc = 0; //unnecessary 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 inst->_num_reg_re = 0; //unnecessary 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; // already define : PC+4 829 829 inst->_no_execute = 0; 830 830 inst->_event_type = EVENT_TYPE_NONE; … … 838 838 inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; 839 839 inst->_has_immediat = 0; 840 // inst->_immediat = ; 840 inst->_immediat = 0; // unnecessary 841 841 inst->_read_ra = 0; 842 // inst->_num_reg_ra = ; 843 inst->_read_rb = 0; 844 // inst->_num_reg_rb = ; 845 inst->_read_rc = 0; 846 // inst->_num_reg_rc = ; 847 inst->_write_rd = 0; 848 // inst->_num_reg_rd = ; 849 inst->_write_re = 0; 850 // inst->_num_reg_re = ; 842 inst->_num_reg_ra = 0; //unnecessary 843 inst->_read_rb = 0; 844 inst->_num_reg_rb = 0; //unnecessary 845 inst->_read_rc = 0; 846 inst->_num_reg_rc = 0; //unnecessary 847 inst->_write_rd = 0; 848 inst->_num_reg_rd = 0; //unnecessary 849 inst->_write_re = 0; 850 inst->_num_reg_re = 0; //unnecessary 851 851 inst->_exception_use = EXCEPTION_USE_NONE; 852 852 inst->_exception = EXCEPTION_DECOD_NONE; … … 869 869 inst->_immediat = inst->_address_next+1; 870 870 inst->_read_ra = 0; 871 // inst->_num_reg_ra = ; 872 inst->_read_rb = 0; 873 // inst->_num_reg_rb = ; 874 inst->_read_rc = 0; 875 // inst->_num_reg_rc = ; 871 inst->_num_reg_ra = 0; //unnecessary 872 inst->_read_rb = 0; 873 inst->_num_reg_rb = 0; //unnecessary 874 inst->_read_rc = 0; 875 inst->_num_reg_rc = 0; //unnecessary 876 876 inst->_write_rd = 1; 877 877 inst->_num_reg_rd = 9; // Link register 878 878 inst->_write_re = 0; 879 // inst->_num_reg_re = ; 879 inst->_num_reg_re = 0; //unnecessary 880 880 inst->_exception_use = EXCEPTION_USE_NONE; 881 881 inst->_exception = EXCEPTION_DECOD_NONE; … … 904 904 inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; 905 905 inst->_has_immediat = 0; 906 // inst->_immediat = ; 906 inst->_immediat = 0; // unnecessary 907 907 inst->_read_ra = 0; 908 // inst->_num_reg_ra = ; 908 inst->_num_reg_ra = 0; //unnecessary 909 909 inst->_read_rb = 1; 910 910 // inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 911 911 inst->_read_rc = 0; 912 // inst->_num_reg_rc = ; 912 inst->_num_reg_rc = 0; //unnecessary 913 913 inst->_write_rd = 1; 914 914 inst->_num_reg_rd = 9; // Link register 915 915 inst->_write_re = 0; 916 // inst->_num_reg_re = ; 916 inst->_num_reg_re = 0; //unnecessary 917 917 inst->_exception_use = EXCEPTION_USE_NONE; 918 918 inst->_exception = EXCEPTION_DECOD_NONE; … … 921 921 // inst->_branch_stack_write = 1; 922 922 inst->_branch_direction = 1; 923 // inst->_address_next = ; 923 // inst->_address_next = ; // already define : PC+4 924 924 inst->_no_execute = 0; 925 925 inst->_event_type = EVENT_TYPE_NONE; … … 934 934 inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; 935 935 inst->_has_immediat = 0; 936 // inst->_immediat = ; 936 inst->_immediat = 0; // unnecessary 937 937 inst->_read_ra = 0; 938 // inst->_num_reg_ra = ; 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 // inst->_num_reg_rc = ; 943 inst->_write_rd = 0; 944 // inst->_num_reg_rd = ; 945 inst->_write_re = 0; 946 // inst->_num_reg_re = ; 938 inst->_num_reg_ra = 0; //unnecessary 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 inst->_num_reg_rc = 0; //unnecessary 943 inst->_write_rd = 0; 944 inst->_num_reg_rd = 0; //unnecessary 945 inst->_write_re = 0; 946 inst->_num_reg_re = 0; //unnecessary 947 947 inst->_exception_use = EXCEPTION_USE_NONE; 948 948 inst->_exception = EXCEPTION_DECOD_NONE; … … 950 950 // inst->_branch_stack_write = 0; 951 951 inst->_branch_direction = 1; 952 // inst->_address_next = ; 952 // inst->_address_next = ; // already define : PC+4 953 953 inst->_no_execute = 0; 954 954 inst->_event_type = EVENT_TYPE_NONE; … … 966 966 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 967 967 inst->_read_rb = 0; 968 // inst->_num_reg_rb = ; 969 inst->_read_rc = 0; 970 // inst->_num_reg_rc = ; 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 // inst->_num_reg_re = ; 968 inst->_num_reg_rb = 0; //unnecessary 969 inst->_read_rc = 0; 970 inst->_num_reg_rc = 0; //unnecessary 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 inst->_num_reg_re = 0; //unnecessary 975 975 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 976 976 inst->_exception = EXCEPTION_DECOD_NONE; … … 978 978 // inst->_branch_stack_write = ; 979 979 // inst->_branch_direction = ; 980 // inst->_address_next = ; 980 // inst->_address_next = ; // already define : PC+4 981 981 inst->_no_execute = 0; 982 982 inst->_event_type = EVENT_TYPE_NONE; … … 994 994 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 995 995 inst->_read_rb = 0; 996 // inst->_num_reg_rb = ; 997 inst->_read_rc = 0; 998 // inst->_num_reg_rc = ; 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 // inst->_num_reg_re = ; 996 inst->_num_reg_rb = 0; //unnecessary 997 inst->_read_rc = 0; 998 inst->_num_reg_rc = 0; //unnecessary 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 inst->_num_reg_re = 0; //unnecessary 1003 1003 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1004 1004 inst->_exception = EXCEPTION_DECOD_NONE; … … 1006 1006 // inst->_branch_stack_write = ; 1007 1007 // inst->_branch_direction = ; 1008 // inst->_address_next = ; 1008 // inst->_address_next = ; // already define : PC+4 1009 1009 inst->_no_execute = 0; 1010 1010 inst->_event_type = EVENT_TYPE_NONE; … … 1022 1022 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1023 1023 inst->_read_rb = 0; 1024 // inst->_num_reg_rb = ; 1025 inst->_read_rc = 0; 1026 // inst->_num_reg_rc = ; 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 // inst->_num_reg_re = ; 1024 inst->_num_reg_rb = 0; //unnecessary 1025 inst->_read_rc = 0; 1026 inst->_num_reg_rc = 0; //unnecessary 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 inst->_num_reg_re = 0; //unnecessary 1031 1031 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1032 1032 inst->_exception = EXCEPTION_DECOD_NONE; … … 1034 1034 // inst->_branch_stack_write = ; 1035 1035 // inst->_branch_direction = ; 1036 // inst->_address_next = ; 1036 // inst->_address_next = ; // already define : PC+4 1037 1037 inst->_no_execute = 0; 1038 1038 inst->_event_type = EVENT_TYPE_NONE; … … 1050 1050 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1051 1051 inst->_read_rb = 0; 1052 // inst->_num_reg_rb = ; 1053 inst->_read_rc = 0; 1054 // inst->_num_reg_rc = ; 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 // inst->_num_reg_re = ; 1052 inst->_num_reg_rb = 0; //unnecessary 1053 inst->_read_rc = 0; 1054 inst->_num_reg_rc = 0; //unnecessary 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 inst->_num_reg_re = 0; //unnecessary 1059 1059 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1060 1060 inst->_exception = EXCEPTION_DECOD_NONE; … … 1062 1062 // inst->_branch_stack_write = ; 1063 1063 // inst->_branch_direction = ; 1064 // inst->_address_next = ; 1064 // inst->_address_next = ; // already define : PC+4 1065 1065 inst->_no_execute = 0; 1066 1066 inst->_event_type = EVENT_TYPE_NONE; … … 1078 1078 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1079 1079 inst->_read_rb = 0; 1080 // inst->_num_reg_rb = ; 1081 inst->_read_rc = 0; 1082 // inst->_num_reg_rc = ; 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 // inst->_num_reg_re = ; 1080 inst->_num_reg_rb = 0; //unnecessary 1081 inst->_read_rc = 0; 1082 inst->_num_reg_rc = 0; //unnecessary 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 inst->_num_reg_re = 0; //unnecessary 1087 1087 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1088 1088 inst->_exception = EXCEPTION_DECOD_NONE; … … 1090 1090 // inst->_branch_stack_write = ; 1091 1091 // inst->_branch_direction = ; 1092 // inst->_address_next = ; 1092 // inst->_address_next = ; // already define : PC+4 1093 1093 inst->_no_execute = 0; 1094 1094 inst->_event_type = EVENT_TYPE_NONE; … … 1106 1106 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1107 1107 inst->_read_rb = 0; 1108 // inst->_num_reg_rb = ; 1109 inst->_read_rc = 0; 1110 // inst->_num_reg_rc = ; 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 // inst->_num_reg_re = ; 1108 inst->_num_reg_rb = 0; //unnecessary 1109 inst->_read_rc = 0; 1110 inst->_num_reg_rc = 0; //unnecessary 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 inst->_num_reg_re = 0; //unnecessary 1115 1115 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1116 1116 inst->_exception = EXCEPTION_DECOD_NONE; … … 1118 1118 // inst->_branch_stack_write = ; 1119 1119 // inst->_branch_direction = ; 1120 // inst->_address_next = ; 1120 // inst->_address_next = ; // already define : PC+4 1121 1121 inst->_no_execute = 0; 1122 1122 inst->_event_type = EVENT_TYPE_NONE; … … 1134 1134 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1135 1135 inst->_read_rb = 0; 1136 // inst->_num_reg_rb = ; 1137 inst->_read_rc = 0; 1138 // inst->_num_reg_rc = ; 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 // inst->_num_reg_re = ; 1136 inst->_num_reg_rb = 0; //unnecessary 1137 inst->_read_rc = 0; 1138 inst->_num_reg_rc = 0; //unnecessary 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 inst->_num_reg_re = 0; //unnecessary 1143 1143 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1144 1144 inst->_exception = EXCEPTION_DECOD_NONE; … … 1146 1146 // inst->_branch_stack_write = ; 1147 1147 // inst->_branch_direction = ; 1148 // inst->_address_next = ; 1148 // inst->_address_next = ; // already define : PC+4 1149 1149 inst->_no_execute = 0; 1150 1150 inst->_event_type = EVENT_TYPE_NONE; … … 1158 1158 inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; 1159 1159 inst->_has_immediat = 0; 1160 // inst->_immediat = ; 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 // inst->_num_reg_rc = ; 1167 inst->_write_rd = 0; 1168 // inst->_num_reg_rd = ; 1169 inst->_write_re = 0; 1170 // inst->_num_reg_re = ; 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // don't change1160 inst->_immediat = 0; // unnecessary 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 inst->_num_reg_rc = 0; //unnecessary 1167 inst->_write_rd = 0; 1168 inst->_num_reg_rd = 0; //unnecessary 1169 inst->_write_re = 0; 1170 inst->_num_reg_re = 0; //unnecessary 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // already define : PC+4 // don't change 1177 1177 inst->_no_execute = 0; 1178 1178 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1191 1191 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1192 1192 inst->_read_rb = 0; 1193 // inst->_num_reg_rb = ; 1194 inst->_read_rc = 0; 1195 // inst->_num_reg_rc = ; 1196 inst->_write_rd = 0; 1197 // inst->_num_reg_rd = ; 1198 inst->_write_re = 0; 1199 // inst->_num_reg_re = ; 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // don't change1193 inst->_num_reg_rb = 0; //unnecessary 1194 inst->_read_rc = 0; 1195 inst->_num_reg_rc = 0; //unnecessary 1196 inst->_write_rd = 0; 1197 inst->_num_reg_rd = 0; //unnecessary 1198 inst->_write_re = 0; 1199 inst->_num_reg_re = 0; //unnecessary 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // already define : PC+4 // don't change 1206 1206 inst->_no_execute = 0; 1207 1207 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1221 1221 inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; 1222 1222 inst->_has_immediat = 0; 1223 // inst->_immediat = ; 1223 inst->_immediat = 0; // unnecessary 1224 1224 inst->_read_ra = 0; 1225 // inst->_num_reg_ra = ; 1226 inst->_read_rb = 0; 1227 // inst->_num_reg_rb = ; 1228 inst->_read_rc = 0; 1229 // inst->_num_reg_rc = ; 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 // inst->_num_reg_re = ; 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // don't change1225 inst->_num_reg_ra = 0; //unnecessary 1226 inst->_read_rb = 0; 1227 inst->_num_reg_rb = 0; //unnecessary 1228 inst->_read_rc = 0; 1229 inst->_num_reg_rc = 0; //unnecessary 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 inst->_num_reg_re = 0; //unnecessary 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // already define : PC+4 // don't change 1240 1240 inst->_no_execute = 0; 1241 1241 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1254 1254 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1255 1255 inst->_read_rb = 0; 1256 // inst->_num_reg_rb = ; 1257 inst->_read_rc = 0; 1258 // inst->_num_reg_rc = ; 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 // inst->_num_reg_re = ; 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // don't change1256 inst->_num_reg_rb = 0; //unnecessary 1257 inst->_read_rc = 0; 1258 inst->_num_reg_rc = 0; //unnecessary 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 inst->_num_reg_re = 0; //unnecessary 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // already define : PC+4 // don't change 1269 1269 inst->_no_execute = 0; 1270 1270 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1280 1280 inst->_immediat = EXTENDZ(inst->_instruction,16); 1281 1281 inst->_read_ra = 0; 1282 // inst->_num_reg_ra = ; 1283 inst->_read_rb = 0; 1284 // inst->_num_reg_rb = ; 1285 inst->_read_rc = 0; 1286 // inst->_num_reg_rc = ; 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 // inst->_num_reg_re = ; 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; 1282 inst->_num_reg_ra = 0; //unnecessary 1283 inst->_read_rb = 0; 1284 inst->_num_reg_rb = 0; //unnecessary 1285 inst->_read_rc = 0; 1286 inst->_num_reg_rc = 0; //unnecessary 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 inst->_num_reg_re = 0; //unnecessary 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; // already define : PC+4 1297 1297 inst->_no_execute = 0; 1298 1298 inst->_event_type = EVENT_TYPE_NONE; … … 1306 1306 inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; 1307 1307 inst->_has_immediat = 0; 1308 // inst->_immediat = ; 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 // inst->_num_reg_rc = ; 1315 inst->_write_rd = 0; 1316 // inst->_num_reg_rd = ; 1317 inst->_write_re = 0; 1318 // inst->_num_reg_re = ; 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // don't change1308 inst->_immediat = 0; // unnecessary 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 inst->_num_reg_rc = 0; //unnecessary 1315 inst->_write_rd = 0; 1316 inst->_num_reg_rd = 0; //unnecessary 1317 inst->_write_re = 0; 1318 inst->_num_reg_re = 0; //unnecessary 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // already define : PC+4 // don't change 1325 1325 inst->_no_execute = 0; 1326 1326 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1340 1340 inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; 1341 1341 inst->_has_immediat = 0; 1342 // inst->_immediat = ; 1342 inst->_immediat = 0; // unnecessary 1343 1343 inst->_read_ra = 0; 1344 // inst->_num_reg_ra = ; 1345 inst->_read_rb = 0; 1346 // inst->_num_reg_rb = ; 1347 inst->_read_rc = 0; 1348 // inst->_num_reg_rc = ; 1349 inst->_write_rd = 0; 1350 // inst->_num_reg_rd = ; 1351 inst->_write_re = 0; 1352 // inst->_num_reg_re = ; 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // don't change1344 inst->_num_reg_ra = 0; //unnecessary 1345 inst->_read_rb = 0; 1346 inst->_num_reg_rb = 0; //unnecessary 1347 inst->_read_rc = 0; 1348 inst->_num_reg_rc = 0; //unnecessary 1349 inst->_write_rd = 0; 1350 inst->_num_reg_rd = 0; //unnecessary 1351 inst->_write_re = 0; 1352 inst->_num_reg_re = 0; //unnecessary 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // already define : PC+4 // don't change 1359 1359 inst->_no_execute = 0; 1360 1360 inst->_event_type = EVENT_TYPE_MSYNC; … … 1376 1376 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1377 1377 inst->_read_rc = 0; 1378 // inst->_num_reg_rc = ; 1379 inst->_write_rd = 0; 1380 // inst->_num_reg_rd = ; 1381 inst->_write_re = 0; 1382 // inst->_num_reg_re = ; 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // don't change1378 inst->_num_reg_rc = 0; //unnecessary 1379 inst->_write_rd = 0; 1380 inst->_num_reg_rd = 0; //unnecessary 1381 inst->_write_re = 0; 1382 inst->_num_reg_re = 0; //unnecessary 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // already define : PC+4 // don't change 1389 1389 inst->_no_execute = 0; 1390 1390 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1398 1398 inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; 1399 1399 inst->_has_immediat = 0; 1400 // inst->_immediat = ; 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 // inst->_num_reg_rc = ; 1400 inst->_immediat = 0; // unnecessary 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 inst->_num_reg_rc = 0; //unnecessary 1407 1407 inst->_write_rd = 1; 1408 1408 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1414 1414 // inst->_branch_stack_write = ; 1415 1415 // inst->_branch_direction = ; 1416 // inst->_address_next = ; 1416 // inst->_address_next = ; // already define : PC+4 1417 1417 inst->_no_execute = 0; 1418 1418 inst->_event_type = EVENT_TYPE_NONE; … … 1430 1430 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1431 1431 inst->_read_rb = 0; 1432 // inst->_num_reg_rb = ; 1433 inst->_read_rc = 0; 1434 // inst->_num_reg_rc = ; 1432 inst->_num_reg_rb = 0; //unnecessary 1433 inst->_read_rc = 0; 1434 inst->_num_reg_rc = 0; //unnecessary 1435 1435 inst->_write_rd = 1; 1436 1436 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1442 1442 // inst->_branch_stack_write = ; 1443 1443 // inst->_branch_direction = ; 1444 // inst->_address_next = ; 1444 // inst->_address_next = ; // already define : PC+4 1445 1445 inst->_no_execute = 0; 1446 1446 inst->_event_type = EVENT_TYPE_NONE; … … 1454 1454 inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; 1455 1455 inst->_has_immediat = 0; 1456 // inst->_immediat = ; 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 // inst->_num_reg_rc = ; 1456 inst->_immediat = 0; // unnecessary 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 inst->_num_reg_rc = 0; //unnecessary 1463 1463 inst->_write_rd = 1; 1464 1464 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1470 1470 // inst->_branch_stack_write = ; 1471 1471 // inst->_branch_direction = ; 1472 // inst->_address_next = ; 1472 // inst->_address_next = ; // already define : PC+4 1473 1473 inst->_no_execute = 0; 1474 1474 inst->_event_type = EVENT_TYPE_NONE; … … 1484 1484 // inst->_immediat = EXTENDZ(inst->_instruction,16); 1485 1485 inst->_has_immediat = 0; 1486 // inst->_immediat = ; 1486 inst->_immediat = 0; // unnecessary 1487 1487 inst->_read_ra = 0; 1488 // inst->_num_reg_ra = ; 1489 inst->_read_rb = 0; 1490 // inst->_num_reg_rb = ; 1491 inst->_read_rc = 0; 1492 // inst->_num_reg_rc = ; 1493 inst->_write_rd = 0; 1494 // inst->_num_reg_rd = ; 1495 inst->_write_re = 0; 1496 // inst->_num_reg_re = ; 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; 1488 inst->_num_reg_ra = 0; //unnecessary 1489 inst->_read_rb = 0; 1490 inst->_num_reg_rb = 0; //unnecessary 1491 inst->_read_rc = 0; 1492 inst->_num_reg_rc = 0; //unnecessary 1493 inst->_write_rd = 0; 1494 inst->_num_reg_rd = 0; //unnecessary 1495 inst->_write_re = 0; 1496 inst->_num_reg_re = 0; //unnecessary 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; // already define : PC+4 1503 1503 inst->_no_execute = 1; 1504 1504 inst->_event_type = EVENT_TYPE_NONE; … … 1512 1512 inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; 1513 1513 inst->_has_immediat = 0; 1514 // inst->_immediat = ; 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 // inst->_num_reg_rc = ; 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 // inst->_num_reg_re = ; 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; 1514 inst->_immediat = 0; // unnecessary 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 inst->_num_reg_rc = 0; //unnecessary 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 inst->_num_reg_re = 0; //unnecessary 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; // already define : PC+4 1531 1531 inst->_no_execute = 0; 1532 1532 inst->_event_type = EVENT_TYPE_NONE; … … 1544 1544 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1545 1545 inst->_read_rb = 0; 1546 // inst->_num_reg_rb = ; 1547 inst->_read_rc = 0; 1548 // inst->_num_reg_rc = ; 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 // inst->_num_reg_re = ; 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; 1546 inst->_num_reg_rb = 0; //unnecessary 1547 inst->_read_rc = 0; 1548 inst->_num_reg_rc = 0; //unnecessary 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 inst->_num_reg_re = 0; //unnecessary 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; // already define : PC+4 1559 1559 inst->_no_execute = 0; 1560 1560 inst->_event_type = EVENT_TYPE_NONE; … … 1574 1574 inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; 1575 1575 inst->_has_immediat = 0; 1576 // inst->_immediat = ; 1576 inst->_immediat = 0; // unnecessary 1577 1577 inst->_read_ra = 0; 1578 // inst->_num_reg_ra = ; 1579 inst->_read_rb = 0; 1580 // inst->_num_reg_rb = ; 1581 inst->_read_rc = 0; 1582 // inst->_num_reg_rc = ; 1583 inst->_write_rd = 0; 1584 // inst->_num_reg_rd = ; 1585 inst->_write_re = 0; 1586 // inst->_num_reg_re = ; 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // don't change1578 inst->_num_reg_ra = 0; //unnecessary 1579 inst->_read_rb = 0; 1580 inst->_num_reg_rb = 0; //unnecessary 1581 inst->_read_rc = 0; 1582 inst->_num_reg_rc = 0; //unnecessary 1583 inst->_write_rd = 0; 1584 inst->_num_reg_rd = 0; //unnecessary 1585 inst->_write_re = 0; 1586 inst->_num_reg_re = 0; //unnecessary 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // already define : PC+4 // don't change 1593 1593 inst->_no_execute = 0; 1594 1594 inst->_event_type = EVENT_TYPE_PSYNC; … … 1603 1603 inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; 1604 1604 inst->_has_immediat = 0; 1605 // inst->_immediat = ; 1605 inst->_immediat = 0; // unnecessary 1606 1606 inst->_read_ra = 0; 1607 // inst->_num_reg_ra = ; 1608 inst->_read_rb = 0; 1609 // inst->_num_reg_rb = ; 1610 inst->_read_rc = 0; 1611 // inst->_num_reg_rc = ; 1612 inst->_write_rd = 0; 1613 // inst->_num_reg_rd = ; 1614 inst->_write_re = 0; 1615 // inst->_num_reg_re = ; 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // don't change1607 inst->_num_reg_ra = 0; //unnecessary 1608 inst->_read_rb = 0; 1609 inst->_num_reg_rb = 0; //unnecessary 1610 inst->_read_rc = 0; 1611 inst->_num_reg_rc = 0; //unnecessary 1612 inst->_write_rd = 0; 1613 inst->_num_reg_rd = 0; //unnecessary 1614 inst->_write_re = 0; 1615 inst->_num_reg_re = 0; //unnecessary 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // already define : PC+4 // don't change 1622 1622 inst->_no_execute = 1; 1623 1623 inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage … … 1631 1631 inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; 1632 1632 inst->_has_immediat = 0; 1633 // inst->_immediat = ; 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 // inst->_num_reg_rc = ; 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 // inst->_num_reg_re = ; 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; 1633 inst->_immediat = 0; // unnecessary 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 inst->_num_reg_rc = 0; //unnecessary 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 inst->_num_reg_re = 0; //unnecessary 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; // already define : PC+4 1650 1650 inst->_no_execute = 0; 1651 1651 inst->_event_type = EVENT_TYPE_NONE; … … 1663 1663 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1664 1664 inst->_read_rb = 0; 1665 // inst->_num_reg_rb = ; 1666 inst->_read_rc = 0; 1667 // inst->_num_reg_rc = ; 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 // inst->_num_reg_re = ; 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; 1665 inst->_num_reg_rb = 0; //unnecessary 1666 inst->_read_rc = 0; 1667 inst->_num_reg_rc = 0; //unnecessary 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 inst->_num_reg_re = 0; //unnecessary 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; // already define : PC+4 1678 1678 inst->_no_execute = 0; 1679 1679 inst->_event_type = EVENT_TYPE_NONE; … … 1694 1694 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1695 1695 inst->_read_rc = 0; 1696 // inst->_num_reg_rc = ; 1697 inst->_write_rd = 0; 1698 // inst->_num_reg_rd = ; 1699 inst->_write_re = 0; 1700 // inst->_num_reg_re = ; 1696 inst->_num_reg_rc = 0; //unnecessary 1697 inst->_write_rd = 0; 1698 inst->_num_reg_rd = 0; //unnecessary 1699 inst->_write_re = 0; 1700 inst->_num_reg_re = 0; //unnecessary 1701 1701 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1702 1702 inst->_exception = EXCEPTION_DECOD_NONE; … … 1704 1704 // inst->_branch_stack_write = ; 1705 1705 // inst->_branch_direction = ; 1706 // inst->_address_next = ; 1706 // inst->_address_next = ; // already define : PC+4 1707 1707 inst->_no_execute = 0; 1708 1708 inst->_event_type = EVENT_TYPE_NONE; … … 1723 1723 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1724 1724 inst->_read_rc = 0; 1725 // inst->_num_reg_rc = ; 1726 inst->_write_rd = 0; 1727 // inst->_num_reg_rd = ; 1728 inst->_write_re = 0; 1729 // inst->_num_reg_re = ; 1725 inst->_num_reg_rc = 0; //unnecessary 1726 inst->_write_rd = 0; 1727 inst->_num_reg_rd = 0; //unnecessary 1728 inst->_write_re = 0; 1729 inst->_num_reg_re = 0; //unnecessary 1730 1730 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1731 1731 inst->_exception = EXCEPTION_DECOD_NONE; … … 1733 1733 // inst->_branch_stack_write = ; 1734 1734 // inst->_branch_direction = ; 1735 // inst->_address_next = ; 1735 // inst->_address_next = ; // already define : PC+4 1736 1736 inst->_no_execute = 0; 1737 1737 inst->_event_type = EVENT_TYPE_NONE; … … 1745 1745 inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; 1746 1746 inst->_has_immediat = 0; 1747 // inst->_immediat = ; 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 // inst->_num_reg_rc = ; 1754 inst->_write_rd = 0; 1755 // inst->_num_reg_rd = ; 1747 inst->_immediat = 0; // unnecessary 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 inst->_num_reg_rc = 0; //unnecessary 1754 inst->_write_rd = 0; 1755 inst->_num_reg_rd = 0; //unnecessary 1756 1756 inst->_write_re = 1; 1757 1757 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1761 1761 // inst->_branch_stack_write = ; 1762 1762 // inst->_branch_direction = ; 1763 // inst->_address_next = ; 1763 // inst->_address_next = ; // already define : PC+4 1764 1764 inst->_no_execute = 0; 1765 1765 inst->_event_type = EVENT_TYPE_NONE; … … 1777 1777 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1778 1778 inst->_read_rb = 0; 1779 // inst->_num_reg_rb = ; 1780 inst->_read_rc = 0; 1781 // inst->_num_reg_rc = ; 1782 inst->_write_rd = 0; 1783 // inst->_num_reg_rd = ; 1779 inst->_num_reg_rb = 0; //unnecessary 1780 inst->_read_rc = 0; 1781 inst->_num_reg_rc = 0; //unnecessary 1782 inst->_write_rd = 0; 1783 inst->_num_reg_rd = 0; //unnecessary 1784 1784 inst->_write_re = 1; 1785 1785 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1789 1789 // inst->_branch_stack_write = ; 1790 1790 // inst->_branch_direction = ; 1791 // inst->_address_next = ; 1791 // inst->_address_next = ; // already define : PC+4 1792 1792 inst->_no_execute = 0; 1793 1793 inst->_event_type = EVENT_TYPE_NONE; … … 1801 1801 inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; 1802 1802 inst->_has_immediat = 0; 1803 // inst->_immediat = ; 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 // inst->_num_reg_rc = ; 1810 inst->_write_rd = 0; 1811 // inst->_num_reg_rd = ; 1803 inst->_immediat = 0; // unnecessary 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 inst->_num_reg_rc = 0; //unnecessary 1810 inst->_write_rd = 0; 1811 inst->_num_reg_rd = 0; //unnecessary 1812 1812 inst->_write_re = 1; 1813 1813 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1817 1817 // inst->_branch_stack_write = ; 1818 1818 // inst->_branch_direction = ; 1819 // inst->_address_next = ; 1819 // inst->_address_next = ; // already define : PC+4 1820 1820 inst->_no_execute = 0; 1821 1821 inst->_event_type = EVENT_TYPE_NONE; … … 1833 1833 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1834 1834 inst->_read_rb = 0; 1835 // inst->_num_reg_rb = ; 1836 inst->_read_rc = 0; 1837 // inst->_num_reg_rc = ; 1838 inst->_write_rd = 0; 1839 // inst->_num_reg_rd = ; 1835 inst->_num_reg_rb = 0; //unnecessary 1836 inst->_read_rc = 0; 1837 inst->_num_reg_rc = 0; //unnecessary 1838 inst->_write_rd = 0; 1839 inst->_num_reg_rd = 0; //unnecessary 1840 1840 inst->_write_re = 1; 1841 1841 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1845 1845 // inst->_branch_stack_write = ; 1846 1846 // inst->_branch_direction = ; 1847 // inst->_address_next = ; 1847 // inst->_address_next = ; // already define : PC+4 1848 1848 inst->_no_execute = 0; 1849 1849 inst->_event_type = EVENT_TYPE_NONE; … … 1857 1857 inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; 1858 1858 inst->_has_immediat = 0; 1859 // inst->_immediat = ; 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 // inst->_num_reg_rc = ; 1866 inst->_write_rd = 0; 1867 // inst->_num_reg_rd = ; 1859 inst->_immediat = 0; // unnecessary 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 inst->_num_reg_rc = 0; //unnecessary 1866 inst->_write_rd = 0; 1867 inst->_num_reg_rd = 0; //unnecessary 1868 1868 inst->_write_re = 1; 1869 1869 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1873 1873 // inst->_branch_stack_write = ; 1874 1874 // inst->_branch_direction = ; 1875 // inst->_address_next = ; 1875 // inst->_address_next = ; // already define : PC+4 1876 1876 inst->_no_execute = 0; 1877 1877 inst->_event_type = EVENT_TYPE_NONE; … … 1889 1889 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1890 1890 inst->_read_rb = 0; 1891 // inst->_num_reg_rb = ; 1892 inst->_read_rc = 0; 1893 // inst->_num_reg_rc = ; 1894 inst->_write_rd = 0; 1895 // inst->_num_reg_rd = ; 1891 inst->_num_reg_rb = 0; //unnecessary 1892 inst->_read_rc = 0; 1893 inst->_num_reg_rc = 0; //unnecessary 1894 inst->_write_rd = 0; 1895 inst->_num_reg_rd = 0; //unnecessary 1896 1896 inst->_write_re = 1; 1897 1897 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1901 1901 // inst->_branch_stack_write = ; 1902 1902 // inst->_branch_direction = ; 1903 // inst->_address_next = ; 1903 // inst->_address_next = ; // already define : PC+4 1904 1904 inst->_no_execute = 0; 1905 1905 inst->_event_type = EVENT_TYPE_NONE; … … 1913 1913 inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; 1914 1914 inst->_has_immediat = 0; 1915 // inst->_immediat = ; 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 // inst->_num_reg_rc = ; 1922 inst->_write_rd = 0; 1923 // inst->_num_reg_rd = ; 1915 inst->_immediat = 0; // unnecessary 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 inst->_num_reg_rc = 0; //unnecessary 1922 inst->_write_rd = 0; 1923 inst->_num_reg_rd = 0; //unnecessary 1924 1924 inst->_write_re = 1; 1925 1925 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1929 1929 // inst->_branch_stack_write = ; 1930 1930 // inst->_branch_direction = ; 1931 // inst->_address_next = ; 1931 // inst->_address_next = ; // already define : PC+4 1932 1932 inst->_no_execute = 0; 1933 1933 inst->_event_type = EVENT_TYPE_NONE; … … 1945 1945 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1946 1946 inst->_read_rb = 0; 1947 // inst->_num_reg_rb = ; 1948 inst->_read_rc = 0; 1949 // inst->_num_reg_rc = ; 1950 inst->_write_rd = 0; 1951 // inst->_num_reg_rd = ; 1947 inst->_num_reg_rb = 0; //unnecessary 1948 inst->_read_rc = 0; 1949 inst->_num_reg_rc = 0; //unnecessary 1950 inst->_write_rd = 0; 1951 inst->_num_reg_rd = 0; //unnecessary 1952 1952 inst->_write_re = 1; 1953 1953 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1957 1957 // inst->_branch_stack_write = ; 1958 1958 // inst->_branch_direction = ; 1959 // inst->_address_next = ; 1959 // inst->_address_next = ; // already define : PC+4 1960 1960 inst->_no_execute = 0; 1961 1961 inst->_event_type = EVENT_TYPE_NONE; … … 1969 1969 inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; 1970 1970 inst->_has_immediat = 0; 1971 // inst->_immediat = ; 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 // inst->_num_reg_rc = ; 1978 inst->_write_rd = 0; 1979 // inst->_num_reg_rd = ; 1971 inst->_immediat = 0; // unnecessary 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 inst->_num_reg_rc = 0; //unnecessary 1978 inst->_write_rd = 0; 1979 inst->_num_reg_rd = 0; //unnecessary 1980 1980 inst->_write_re = 1; 1981 1981 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1985 1985 // inst->_branch_stack_write = ; 1986 1986 // inst->_branch_direction = ; 1987 // inst->_address_next = ; 1987 // inst->_address_next = ; // already define : PC+4 1988 1988 inst->_no_execute = 0; 1989 1989 inst->_event_type = EVENT_TYPE_NONE; … … 2001 2001 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2002 2002 inst->_read_rb = 0; 2003 // inst->_num_reg_rb = ; 2004 inst->_read_rc = 0; 2005 // inst->_num_reg_rc = ; 2006 inst->_write_rd = 0; 2007 // inst->_num_reg_rd = ; 2003 inst->_num_reg_rb = 0; //unnecessary 2004 inst->_read_rc = 0; 2005 inst->_num_reg_rc = 0; //unnecessary 2006 inst->_write_rd = 0; 2007 inst->_num_reg_rd = 0; //unnecessary 2008 2008 inst->_write_re = 1; 2009 2009 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2013 2013 // inst->_branch_stack_write = ; 2014 2014 // inst->_branch_direction = ; 2015 // inst->_address_next = ; 2015 // inst->_address_next = ; // already define : PC+4 2016 2016 inst->_no_execute = 0; 2017 2017 inst->_event_type = EVENT_TYPE_NONE; … … 2025 2025 inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; 2026 2026 inst->_has_immediat = 0; 2027 // inst->_immediat = ; 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 // inst->_num_reg_rc = ; 2034 inst->_write_rd = 0; 2035 // inst->_num_reg_rd = ; 2027 inst->_immediat = 0; // unnecessary 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 inst->_num_reg_rc = 0; //unnecessary 2034 inst->_write_rd = 0; 2035 inst->_num_reg_rd = 0; //unnecessary 2036 2036 inst->_write_re = 1; 2037 2037 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2041 2041 // inst->_branch_stack_write = ; 2042 2042 // inst->_branch_direction = ; 2043 // inst->_address_next = ; 2043 // inst->_address_next = ; // already define : PC+4 2044 2044 inst->_no_execute = 0; 2045 2045 inst->_event_type = EVENT_TYPE_NONE; … … 2057 2057 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2058 2058 inst->_read_rb = 0; 2059 // inst->_num_reg_rb = ; 2060 inst->_read_rc = 0; 2061 // inst->_num_reg_rc = ; 2062 inst->_write_rd = 0; 2063 // inst->_num_reg_rd = ; 2059 inst->_num_reg_rb = 0; //unnecessary 2060 inst->_read_rc = 0; 2061 inst->_num_reg_rc = 0; //unnecessary 2062 inst->_write_rd = 0; 2063 inst->_num_reg_rd = 0; //unnecessary 2064 2064 inst->_write_re = 1; 2065 2065 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2069 2069 // inst->_branch_stack_write = ; 2070 2070 // inst->_branch_direction = ; 2071 // inst->_address_next = ; 2071 // inst->_address_next = ; // already define : PC+4 2072 2072 inst->_no_execute = 0; 2073 2073 inst->_event_type = EVENT_TYPE_NONE; … … 2081 2081 inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; 2082 2082 inst->_has_immediat = 0; 2083 // inst->_immediat = ; 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 // inst->_num_reg_rc = ; 2090 inst->_write_rd = 0; 2091 // inst->_num_reg_rd = ; 2083 inst->_immediat = 0; // unnecessary 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 inst->_num_reg_rc = 0; //unnecessary 2090 inst->_write_rd = 0; 2091 inst->_num_reg_rd = 0; //unnecessary 2092 2092 inst->_write_re = 1; 2093 2093 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2097 2097 // inst->_branch_stack_write = ; 2098 2098 // inst->_branch_direction = ; 2099 // inst->_address_next = ; 2099 // inst->_address_next = ; // already define : PC+4 2100 2100 inst->_no_execute = 0; 2101 2101 inst->_event_type = EVENT_TYPE_NONE; … … 2113 2113 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2114 2114 inst->_read_rb = 0; 2115 // inst->_num_reg_rb = ; 2116 inst->_read_rc = 0; 2117 // inst->_num_reg_rc = ; 2118 inst->_write_rd = 0; 2119 // inst->_num_reg_rd = ; 2115 inst->_num_reg_rb = 0; //unnecessary 2116 inst->_read_rc = 0; 2117 inst->_num_reg_rc = 0; //unnecessary 2118 inst->_write_rd = 0; 2119 inst->_num_reg_rd = 0; //unnecessary 2120 2120 inst->_write_re = 1; 2121 2121 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2125 2125 // inst->_branch_stack_write = ; 2126 2126 // inst->_branch_direction = ; 2127 // inst->_address_next = ; 2127 // inst->_address_next = ; // already define : PC+4 2128 2128 inst->_no_execute = 0; 2129 2129 inst->_event_type = EVENT_TYPE_NONE; … … 2137 2137 inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; 2138 2138 inst->_has_immediat = 0; 2139 // inst->_immediat = ; 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 // inst->_num_reg_rc = ; 2146 inst->_write_rd = 0; 2147 // inst->_num_reg_rd = ; 2139 inst->_immediat = 0; // unnecessary 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 inst->_num_reg_rc = 0; //unnecessary 2146 inst->_write_rd = 0; 2147 inst->_num_reg_rd = 0; //unnecessary 2148 2148 inst->_write_re = 1; 2149 2149 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2153 2153 // inst->_branch_stack_write = ; 2154 2154 // inst->_branch_direction = ; 2155 // inst->_address_next = ; 2155 // inst->_address_next = ; // already define : PC+4 2156 2156 inst->_no_execute = 0; 2157 2157 inst->_event_type = EVENT_TYPE_NONE; … … 2169 2169 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2170 2170 inst->_read_rb = 0; 2171 // inst->_num_reg_rb = ; 2172 inst->_read_rc = 0; 2173 // inst->_num_reg_rc = ; 2174 inst->_write_rd = 0; 2175 // inst->_num_reg_rd = ; 2171 inst->_num_reg_rb = 0; //unnecessary 2172 inst->_read_rc = 0; 2173 inst->_num_reg_rc = 0; //unnecessary 2174 inst->_write_rd = 0; 2175 inst->_num_reg_rd = 0; //unnecessary 2176 2176 inst->_write_re = 1; 2177 2177 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2181 2181 // inst->_branch_stack_write = ; 2182 2182 // inst->_branch_direction = ; 2183 // inst->_address_next = ; 2183 // inst->_address_next = ; // already define : PC+4 2184 2184 inst->_no_execute = 0; 2185 2185 inst->_event_type = EVENT_TYPE_NONE; … … 2193 2193 inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; 2194 2194 inst->_has_immediat = 0; 2195 // inst->_immediat = ; 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 // inst->_num_reg_rc = ; 2202 inst->_write_rd = 0; 2203 // inst->_num_reg_rd = ; 2195 inst->_immediat = 0; // unnecessary 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 inst->_num_reg_rc = 0; //unnecessary 2202 inst->_write_rd = 0; 2203 inst->_num_reg_rd = 0; //unnecessary 2204 2204 inst->_write_re = 1; 2205 2205 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2209 2209 // inst->_branch_stack_write = ; 2210 2210 // inst->_branch_direction = ; 2211 // inst->_address_next = ; 2211 // inst->_address_next = ; // already define : PC+4 2212 2212 inst->_no_execute = 0; 2213 2213 inst->_event_type = EVENT_TYPE_NONE; … … 2225 2225 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2226 2226 inst->_read_rb = 0; 2227 // inst->_num_reg_rb = ; 2228 inst->_read_rc = 0; 2229 // inst->_num_reg_rc = ; 2230 inst->_write_rd = 0; 2231 // inst->_num_reg_rd = ; 2227 inst->_num_reg_rb = 0; //unnecessary 2228 inst->_read_rc = 0; 2229 inst->_num_reg_rc = 0; //unnecessary 2230 inst->_write_rd = 0; 2231 inst->_num_reg_rd = 0; //unnecessary 2232 2232 inst->_write_re = 1; 2233 2233 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2237 2237 // inst->_branch_stack_write = ; 2238 2238 // inst->_branch_direction = ; 2239 // inst->_address_next = ; 2239 // inst->_address_next = ; // already define : PC+4 2240 2240 inst->_no_execute = 0; 2241 2241 inst->_event_type = EVENT_TYPE_NONE; … … 2249 2249 inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; 2250 2250 inst->_has_immediat = 0; 2251 // inst->_immediat = ; 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 // inst->_num_reg_rc = ; 2258 inst->_write_rd = 0; 2259 // inst->_num_reg_rd = ; 2251 inst->_immediat = 0; // unnecessary 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 inst->_num_reg_rc = 0; //unnecessary 2258 inst->_write_rd = 0; 2259 inst->_num_reg_rd = 0; //unnecessary 2260 2260 inst->_write_re = 1; 2261 2261 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2265 2265 // inst->_branch_stack_write = ; 2266 2266 // inst->_branch_direction = ; 2267 // inst->_address_next = ; 2267 // inst->_address_next = ; // already define : PC+4 2268 2268 inst->_no_execute = 0; 2269 2269 inst->_event_type = EVENT_TYPE_NONE; … … 2281 2281 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2282 2282 inst->_read_rb = 0; 2283 // inst->_num_reg_rb = ; 2284 inst->_read_rc = 0; 2285 // inst->_num_reg_rc = ; 2286 inst->_write_rd = 0; 2287 // inst->_num_reg_rd = ; 2283 inst->_num_reg_rb = 0; //unnecessary 2284 inst->_read_rc = 0; 2285 inst->_num_reg_rc = 0; //unnecessary 2286 inst->_write_rd = 0; 2287 inst->_num_reg_rd = 0; //unnecessary 2288 2288 inst->_write_re = 1; 2289 2289 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2293 2293 // inst->_branch_stack_write = ; 2294 2294 // inst->_branch_direction = ; 2295 // inst->_address_next = ; 2295 // inst->_address_next = ; // already define : PC+4 2296 2296 inst->_no_execute = 0; 2297 2297 inst->_event_type = EVENT_TYPE_NONE; … … 2312 2312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2313 2313 inst->_read_rc = 0; 2314 // inst->_num_reg_rc = ; 2315 inst->_write_rd = 0; 2316 // inst->_num_reg_rd = ; 2317 inst->_write_re = 0; 2318 // inst->_num_reg_re = ; 2314 inst->_num_reg_rc = 0; //unnecessary 2315 inst->_write_rd = 0; 2316 inst->_num_reg_rd = 0; //unnecessary 2317 inst->_write_re = 0; 2318 inst->_num_reg_re = 0; //unnecessary 2319 2319 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2320 2320 inst->_exception = EXCEPTION_DECOD_NONE; … … 2322 2322 // inst->_branch_stack_write = ; 2323 2323 // inst->_branch_direction = ; 2324 // inst->_address_next = ; 2324 // inst->_address_next = ; // already define : PC+4 2325 2325 inst->_no_execute = 0; 2326 2326 inst->_event_type = EVENT_TYPE_NONE; … … 2334 2334 inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; 2335 2335 inst->_has_immediat = 0; 2336 // inst->_immediat = ; 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 // inst->_num_reg_rc = ; 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 // inst->_num_reg_re = ; 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; 2336 inst->_immediat = 0; // unnecessary 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 inst->_num_reg_rc = 0; //unnecessary 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 inst->_num_reg_re = 0; //unnecessary 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; // already define : PC+4 2353 2353 inst->_no_execute = 0; 2354 2354 inst->_event_type = EVENT_TYPE_NONE; … … 2366 2366 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2367 2367 inst->_read_rb = 0; 2368 // inst->_num_reg_rb = ; 2369 inst->_read_rc = 0; 2370 // inst->_num_reg_rc = ; 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 // inst->_num_reg_re = ; 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; 2368 inst->_num_reg_rb = 0; //unnecessary 2369 inst->_read_rc = 0; 2370 inst->_num_reg_rc = 0; //unnecessary 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 inst->_num_reg_re = 0; //unnecessary 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; // already define : PC+4 2381 2381 inst->_no_execute = 0; 2382 2382 inst->_event_type = EVENT_TYPE_NONE; … … 2390 2390 inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; 2391 2391 inst->_has_immediat = 0; 2392 // inst->_immediat = ; 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 // inst->_num_reg_rc = ; 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 // inst->_num_reg_re = ; 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; 2392 inst->_immediat = 0; // unnecessary 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 inst->_num_reg_rc = 0; //unnecessary 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 inst->_num_reg_re = 0; //unnecessary 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; // already define : PC+4 2409 2409 inst->_no_execute = 0; 2410 2410 inst->_event_type = EVENT_TYPE_NONE; … … 2422 2422 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2423 2423 inst->_read_rb = 0; 2424 // inst->_num_reg_rb = ; 2425 inst->_read_rc = 0; 2426 // inst->_num_reg_rc = ; 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 // inst->_num_reg_re = ; 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; 2424 inst->_num_reg_rb = 0; //unnecessary 2425 inst->_read_rc = 0; 2426 inst->_num_reg_rc = 0; //unnecessary 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 inst->_num_reg_re = 0; //unnecessary 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; // already define : PC+4 2437 2437 inst->_no_execute = 0; 2438 2438 inst->_event_type = EVENT_TYPE_NONE; … … 2446 2446 inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; 2447 2447 inst->_has_immediat = 0; 2448 // inst->_immediat = ; 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 // inst->_num_reg_rc = ; 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 // inst->_num_reg_re = ; 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; 2448 inst->_immediat = 0; // unnecessary 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 inst->_num_reg_rc = 0; //unnecessary 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 inst->_num_reg_re = 0; //unnecessary 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; // already define : PC+4 2465 2465 inst->_no_execute = 0; 2466 2466 inst->_event_type = EVENT_TYPE_NONE; … … 2478 2478 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2479 2479 inst->_read_rb = 0; 2480 // inst->_num_reg_rb = ; 2481 inst->_read_rc = 0; 2482 // inst->_num_reg_rc = ; 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 // inst->_num_reg_re = ; 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; 2480 inst->_num_reg_rb = 0; //unnecessary 2481 inst->_read_rc = 0; 2482 inst->_num_reg_rc = 0; //unnecessary 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 inst->_num_reg_re = 0; //unnecessary 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; // already define : PC+4 2493 2493 inst->_no_execute = 0; 2494 2494 inst->_event_type = EVENT_TYPE_NONE; … … 2502 2502 inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; 2503 2503 inst->_has_immediat = 0; 2504 // inst->_immediat = ; 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 // inst->_num_reg_rc = ; 2504 inst->_immediat = 0; // unnecessary 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 inst->_num_reg_rc = 0; //unnecessary 2511 2511 inst->_write_rd = 1; 2512 2512 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 2518 2518 // inst->_branch_stack_write = ; 2519 2519 // inst->_branch_direction = ; 2520 // inst->_address_next = ; 2520 // inst->_address_next = ; // already define : PC+4 2521 2521 inst->_no_execute = 0; 2522 2522 inst->_event_type = EVENT_TYPE_NONE; … … 2537 2537 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2538 2538 inst->_read_rc = 0; 2539 // inst->_num_reg_rc = ; 2540 inst->_write_rd = 0; 2541 // inst->_num_reg_rd = ; 2542 inst->_write_re = 0; 2543 // inst->_num_reg_re = ; 2539 inst->_num_reg_rc = 0; //unnecessary 2540 inst->_write_rd = 0; 2541 inst->_num_reg_rd = 0; //unnecessary 2542 inst->_write_re = 0; 2543 inst->_num_reg_re = 0; //unnecessary 2544 2544 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2545 2545 inst->_exception = EXCEPTION_DECOD_NONE; … … 2547 2547 // inst->_branch_stack_write = ; 2548 2548 // inst->_branch_direction = ; 2549 // inst->_address_next = ; 2549 // inst->_address_next = ; // already define : PC+4 2550 2550 inst->_no_execute = 0; 2551 2551 inst->_event_type = EVENT_TYPE_NONE; … … 2567 2567 // inst->_immediat = EXTENDZ(inst->_instruction,16); 2568 2568 inst->_has_immediat = 0; 2569 // inst->_immediat = ; 2569 inst->_immediat = 0; // unnecessary 2570 2570 inst->_read_ra = 0; 2571 // inst->_num_reg_ra = ; 2572 inst->_read_rb = 0; 2573 // inst->_num_reg_rb = ; 2574 inst->_read_rc = 0; 2575 // inst->_num_reg_rc = ; 2576 inst->_write_rd = 0; 2577 // inst->_num_reg_rd = ; 2578 inst->_write_re = 0; 2579 // inst->_num_reg_re = ; 2571 inst->_num_reg_ra = 0; //unnecessary 2572 inst->_read_rb = 0; 2573 inst->_num_reg_rb = 0; //unnecessary 2574 inst->_read_rc = 0; 2575 inst->_num_reg_rc = 0; //unnecessary 2576 inst->_write_rd = 0; 2577 inst->_num_reg_rd = 0; //unnecessary 2578 inst->_write_re = 0; 2579 inst->_num_reg_re = 0; //unnecessary 2580 2580 inst->_exception_use = EXCEPTION_USE_SYSCALL; 2581 2581 inst->_exception = EXCEPTION_SYSCALL; … … 2590 2590 2591 2591 2592 // inst->_address_next = ; // don't change2592 // inst->_address_next = ; // already define : PC+4 // don't change 2593 2593 inst->_no_execute = 1; 2594 2594 inst->_event_type = EVENT_TYPE_EXCEPTION; … … 2611 2611 inst->_immediat = EXTENDZ(inst->_instruction,16); 2612 2612 inst->_read_ra = 0; 2613 // inst->_num_reg_ra = ; 2614 inst->_read_rb = 0; 2615 // inst->_num_reg_rb = ; 2613 inst->_num_reg_ra = 0; //unnecessary 2614 inst->_read_rb = 0; 2615 inst->_num_reg_rb = 0; //unnecessary 2616 2616 inst->_read_rc = 0; // read all SR 2617 // inst->_num_reg_rc = ; 2618 inst->_write_rd = 0; 2619 // inst->_num_reg_rd = ; 2620 inst->_write_re = 0; 2621 // inst->_num_reg_re = ; 2617 inst->_num_reg_rc = 0; //unnecessary 2618 inst->_write_rd = 0; 2619 inst->_num_reg_rd = 0; //unnecessary 2620 inst->_write_re = 0; 2621 inst->_num_reg_re = 0; //unnecessary 2622 2622 inst->_exception_use = EXCEPTION_USE_TRAP; 2623 2623 inst->_exception = EXCEPTION_DECOD_NONE; … … 2625 2625 // inst->_branch_stack_write = ; 2626 2626 // inst->_branch_direction = ; 2627 // inst->_address_next = ; 2627 // inst->_address_next = ; // already define : PC+4 2628 2628 inst->_no_execute = 1; 2629 2629 inst->_event_type = EVENT_TYPE_NONE; … … 2638 2638 inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; 2639 2639 inst->_has_immediat = 0; 2640 // inst->_immediat = ; 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 // inst->_num_reg_rc = ; 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 // inst->_num_reg_re = ; 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; 2640 inst->_immediat = 0; // unnecessary 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 inst->_num_reg_rc = 0; //unnecessary 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 inst->_num_reg_re = 0; //unnecessary 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; // already define : PC+4 2657 2657 inst->_no_execute = 0; 2658 2658 inst->_event_type = EVENT_TYPE_NONE; … … 2670 2670 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2671 2671 inst->_read_rb = 0; 2672 // inst->_num_reg_rb = ; 2673 inst->_read_rc = 0; 2674 // inst->_num_reg_rc = ; 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 // inst->_num_reg_re = ; 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; 2672 inst->_num_reg_rb = 0; //unnecessary 2673 inst->_read_rc = 0; 2674 inst->_num_reg_rc = 0; //unnecessary 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 inst->_num_reg_re = 0; //unnecessary 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; // already define : PC+4 2685 2685 inst->_no_execute = 0; 2686 2686 inst->_event_type = EVENT_TYPE_NONE; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp
r88 r97 75 75 ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); 76 76 ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"out_EVENT_IFETCH_UNIT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); 77 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,"out_EVENT_PREDICTION_UNIT_VAL ",Tcontrol_t,_param->_nb_context); 78 ALLOC1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ," in_EVENT_PREDICTION_UNIT_ACK ",Tcontrol_t,_param->_nb_context); 79 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,"out_EVENT_PREDICTION_UNIT_TYPE ",Tevent_type_t,_param->_nb_context); 80 ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,"out_EVENT_PREDICTION_UNIT_DEPTH ",Tdepth_t ,_param->_nb_context); 77 81 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ," in_EVENT_CONTEXT_STATE_VAL ",Tcontrol_t,_param->_nb_context); 78 82 ALLOC1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,"out_EVENT_CONTEXT_STATE_ACK ",Tcontrol_t,_param->_nb_context); … … 81 85 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); 82 86 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ," in_EVENT_CONTEXT_STATE_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); 87 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ," in_EVENT_CONTEXT_STATE_TYPE ",Tevent_type_t,_param->_nb_context); 88 ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ," in_EVENT_CONTEXT_STATE_DEPTH ",Tdepth_t ,_param->_nb_context); 83 89 84 90 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); … … 132 138 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); 133 139 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); 140 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); 141 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); 142 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); 143 if (_param->_have_port_depth) 144 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); 134 145 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); 135 146 INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); … … 138 149 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); 139 150 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); 151 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); 152 if (_param->_have_port_depth) 153 INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); 140 154 141 155 for (uint32_t i=0; i<_param->_nb_context; ++i) … … 230 244 DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); 231 245 DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); 246 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); 247 DELETE1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); 248 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); 249 DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); 232 250 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); 233 251 DELETE1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); … … 236 254 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); 237 255 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); 256 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); 257 DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); 238 258 239 259 DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h
r88 r97 97 97 public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ;//[nb_context] 98 98 public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_IS_DS_TAKE ;//[nb_context] 99 100 public : SC_OUT(Tcontrol_t ) ** out_EVENT_PREDICTION_UNIT_VAL ;//[nb_context] 101 public : SC_IN (Tcontrol_t ) ** in_EVENT_PREDICTION_UNIT_ACK ;//[nb_context] 102 public : SC_OUT(Tevent_type_t ) ** out_EVENT_PREDICTION_UNIT_TYPE ;//[nb_context] 103 public : SC_OUT(Tdepth_t ) ** out_EVENT_PREDICTION_UNIT_DEPTH ;//[nb_context] 99 104 100 105 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_VAL ;//[nb_context] … … 104 109 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ;//[nb_context] 105 110 public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_IS_DS_TAKE ;//[nb_context] 111 public : SC_IN (Tevent_type_t ) ** in_EVENT_CONTEXT_STATE_TYPE ;//[nb_context] 112 public : SC_IN (Tdepth_t ) ** in_EVENT_CONTEXT_STATE_DEPTH ;//[nb_context] 106 113 107 114 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp
r88 r97 138 138 // sensitive << (*(in_CLOCK)).neg(); // don't need internal register 139 139 for (uint32_t i=0; i<_param->_nb_context; ++i) 140 sensitive << (*( in_EVENT_ACK [i])) 141 << (*( in_EVENT_IFETCH_UNIT_ACK [i])) 142 << (*( in_EVENT_CONTEXT_STATE_VAL [i])) 143 << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) 144 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) 145 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) 146 << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])); 140 { 141 sensitive << (*( in_EVENT_ACK [i])) 142 << (*( in_EVENT_IFETCH_UNIT_ACK [i])) 143 << (*( in_EVENT_PREDICTION_UNIT_ACK [i])) 144 << (*( in_EVENT_CONTEXT_STATE_VAL [i])) 145 << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) 146 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) 147 << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) 148 << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])) 149 << (*( in_EVENT_CONTEXT_STATE_TYPE [i])); 150 if (_param->_have_port_depth) 151 sensitive << (*( in_EVENT_CONTEXT_STATE_DEPTH [i])); 152 } 147 153 148 154 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp
r88 r97 105 105 ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"IFETCH_UNIT_ADDRESS_NEXT_VAL" ,Tcontrol_t ,1); 106 106 ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"IFETCH_UNIT_IS_DS_TAKE" ,Tcontrol_t ,1); 107 108 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_VAL ,"PREDICTION_UNIT_VAL" ,Tcontrol_t ,1); 109 ALLOC1_SIGNAL_IN ( in_EVENT_PREDICTION_UNIT_ACK ,"PREDICTION_UNIT_ACK" ,Tcontrol_t ,1); 110 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_TYPE ,"PREDICTION_UNIT_TYPE" ,Tevent_type_t ,_param->_size_event_type); 111 ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_DEPTH ,"PREDICTION_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth); 107 112 108 113 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_VAL ,"CONTEXT_STATE_VAL" ,Tcontrol_t ,1); … … 112 117 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,"CONTEXT_STATE_ADDRESS_NEXT_VAL",Tcontrol_t ,1); 113 118 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,"CONTEXT_STATE_IS_DS_TAKE" ,Tcontrol_t ,1); 119 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_TYPE ,"CONTEXT_STATE_TYPE" ,Tevent_type_t ,_param->_size_event_type); 120 ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_DEPTH ,"CONTEXT_STATE_DEPTH" ,Tdepth_t ,_param->_size_depth); 121 114 122 } 115 123 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp
r88 r97 55 55 DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 56 56 DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context,1); 57 58 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context,1); 59 DELETE1_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context,1); 60 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context,_param->_size_event_type); 61 DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context,_param->_size_depth); 62 57 63 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context,1); 58 64 DELETE1_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context,1); … … 61 67 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context,1); 62 68 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context,1); 69 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context,_param->_size_event_type); 70 DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context,_param->_size_depth); 63 71 64 72 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp
r88 r97 25 25 for (uint32_t i=0; i<_param->_nb_context; ++i) 26 26 { 27 Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]);27 Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]); 28 28 PORT_WRITE(out_EVENT_ADDRESS [i],address); 29 29 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS [i],address); 30 30 31 Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]);31 Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]); 32 32 PORT_WRITE(out_EVENT_ADDRESS_NEXT [i],address_next); 33 33 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT [i],address_next); 34 34 35 Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]);35 Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]); 36 36 PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i],address_next_val); 37 37 PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL [i],address_next_val); 38 38 39 Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]);39 Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]); 40 40 PORT_WRITE(out_EVENT_IS_DS_TAKE [i],is_ds_take); 41 41 PORT_WRITE(out_EVENT_IFETCH_UNIT_IS_DS_TAKE [i],is_ds_take); 42 42 43 Tcontrol_t val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); 44 PORT_WRITE(out_EVENT_VAL [i],val); 45 PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i],val); 43 Tevent_type_t event_type = PORT_READ(in_EVENT_CONTEXT_STATE_TYPE [i]); 44 PORT_WRITE(out_EVENT_PREDICTION_UNIT_TYPE [i],event_type); 45 46 if (_param->_have_port_depth) 47 { 48 Tdepth_t depth = PORT_READ(in_EVENT_CONTEXT_STATE_DEPTH [i]); 49 PORT_WRITE(out_EVENT_PREDICTION_UNIT_DEPTH [i],depth); 50 } 51 46 52 47 Tcontrol_t ack = (PORT_READ(in_EVENT_ACK [i]) and 48 PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i])); 49 PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i],ack); 53 Tcontrol_t ack = PORT_READ(in_EVENT_ACK [i]); 54 Tcontrol_t ifetch_unit_ack = PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i]); 55 Tcontrol_t prediction_unit_ack = PORT_READ(in_EVENT_PREDICTION_UNIT_ACK [i]); 56 Tcontrol_t context_state_val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); 57 58 Tcontrol_t val = (//ack and 59 ifetch_unit_ack and 60 prediction_unit_ack and 61 context_state_val 62 ); 63 Tcontrol_t ifetch_unit_val = ( ack and 64 //ifetch_unit_ack and 65 prediction_unit_ack and 66 context_state_val 67 ); 68 Tcontrol_t prediction_unit_val = ( ack and 69 ifetch_unit_ack and 70 //prediction_unit_ack and 71 context_state_val 72 ); 73 Tcontrol_t context_state_ack = ( ack and 74 ifetch_unit_ack and 75 prediction_unit_ack // and 76 //context_state_val 77 ); 78 79 log_printf(TRACE,Front_end_Glue,FUNCTION," * val %d, ack %d",val ,ack ); 80 log_printf(TRACE,Front_end_Glue,FUNCTION," * ifetch_unit_val %d, ifetch_unit_ack %d",ifetch_unit_val ,ifetch_unit_ack ); 81 log_printf(TRACE,Front_end_Glue,FUNCTION," * prediction_unit_val %d, prediction_unit_ack %d",prediction_unit_val,prediction_unit_ack); 82 log_printf(TRACE,Front_end_Glue,FUNCTION," * context_state_val %d, context_state_ack %d",context_state_val ,context_state_ack ); 83 84 85 PORT_WRITE(out_EVENT_VAL [i], val ); 86 PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i], ifetch_unit_val ); 87 PORT_WRITE(out_EVENT_PREDICTION_UNIT_VAL [i], prediction_unit_val); 88 PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i], context_state_ack ); 50 89 51 90 #ifdef DEBUG -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
r95 r97 94 94 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); 95 95 96 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 97 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 98 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 96 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 97 ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 98 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 99 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 99 100 100 101 ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); … … 160 161 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 161 162 162 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE ,_param->_nb_context); 163 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL ,_param->_nb_context); 164 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK ,_param->_nb_context); 163 165 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); 164 166 if (_param->_have_port_depth) … … 364 366 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); 365 367 366 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 368 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); 369 DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); 367 370 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 368 371 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps
r81 r97 21 21 22 22 Update_Prediction_Table_LIBRARY = -lUpdate_Prediction_Table \ 23 $(Behavioural_LIBRARY) 23 $(Behavioural_LIBRARY) 24 24 25 25 Update_Prediction_Table_DIR_LIBRARY = -L$(Update_Prediction_Table_DIR)/lib \ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r95 r97 42 42 43 43 #ifdef STATISTICS 44 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5, 50);44 morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); 45 45 #endif 46 46 … … 137 137 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); 138 138 139 ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); 139 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 140 ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 140 141 ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); 141 142 ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); … … 230 231 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); 231 232 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); 232 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context); 233 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); 234 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); 233 235 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context); 234 236 if (_param->_have_port_depth) … … 316 318 in_UPDATE_ACK [i]->write(0); 317 319 for (uint32_t i=0; i<_param->_nb_context; ++i) 318 { 319 in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); 320 in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE ); 321 } 320 in_EVENT_VAL [i]->write(0); 321 322 322 //--------------------------------------------------------------------- 323 323 //--------------------------------------------------------------------- … … 932 932 933 933 SC_START(1); 934 in_EVENT_ STATE [context]->write(EVENT_STATE_END);934 in_EVENT_VAL [context]->write(1); 935 935 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 936 936 937 937 SC_START(1); 938 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);938 in_EVENT_VAL [context]->write(0); 939 939 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 940 940 } … … 1366 1366 1367 1367 SC_START(1); 1368 in_EVENT_ STATE [context]->write(EVENT_STATE_END);1368 in_EVENT_VAL [context]->write(1); 1369 1369 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1370 1370 1371 1371 SC_START(1); 1372 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);1372 in_EVENT_VAL [context]->write(0); 1373 1373 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1374 1374 } … … 1974 1974 1975 1975 SC_START(1); 1976 in_EVENT_ STATE [context]->write(EVENT_STATE_END);1976 in_EVENT_VAL [context]->write(1); 1977 1977 in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); 1978 1978 1979 1979 SC_START(1); 1980 in_EVENT_ STATE [context]->write(EVENT_STATE_NO_EVENT);1980 in_EVENT_VAL [context]->write(0); 1981 1981 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 1982 1982 } … … 2155 2155 delete [] out_UPDATE_RAS_PREDICTION_IFETCH; 2156 2156 2157 DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); 2157 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); 2158 DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); 2158 2159 DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); 2159 2160 DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r95 r97 52 52 public : Stat * _stat; 53 53 54 private : counter_t ** _stat_nb_branch_hit ; //[nb_context] 55 private : counter_t ** _stat_nb_branch_miss ; //[nb_context] 56 private : counter_t ** _stat_nb_branch_unused ; //[nb_context] 57 private : counter_t ** _stat_queue_nb_cycle_empty; //[nb_context] 58 private : counter_t ** _stat_queue_nb_cycle_full ; //[nb_context] 59 private : counter_t ** _stat_queue_nb_elt ; //[nb_context] 54 private : counter_t *** _stat_nb_branch_hit ; //[nb_context][MAX_BRANCH_CONDITION] 55 private : counter_t *** _stat_nb_branch_miss ; //[nb_context][MAX_BRANCH_CONDITION] 56 private : counter_t ** _stat_nb_branch_unused ; //[nb_context] 57 private : counter_t ** _stat_ufpt_queue_nb_elt ; //[nb_context] 58 private : counter_t ** _stat_upt_queue_nb_elt ; //[nb_context] 60 59 61 60 #endif … … 143 142 144 143 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 145 public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] 144 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] 145 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] 146 146 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 147 147 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] … … 197 197 private : Tdepth_t * internal_UPDATE_DEPTH ; //[nb_inst_update] 198 198 private : bool * internal_UPDATE_RAS ; //[nb_inst_update] 199 private : Tcontrol_t * internal_EVENT_ACK ; //[nb_context] 199 200 200 201 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp
r88 r97 76 76 if (usage_is_set(_usage,USE_SYSTEMC)) 77 77 { 78 78 // Constant 79 79 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 80 80 { … … 82 82 PORT_WRITE(out_BRANCH_COMPLETE_ACK [i], internal_BRANCH_COMPLETE_ACK [i]); 83 83 } 84 for (uint32_t i=0; i<_param->_nb_context; ++i) 85 { 86 internal_EVENT_ACK [i] = 1; 87 PORT_WRITE(out_EVENT_ACK [i], internal_EVENT_ACK [i]); 88 } 84 89 85 90 log_printf(INFO,Update_Prediction_Table,FUNCTION,"Method - transition"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r95 r97 151 151 ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); 152 152 153 ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); 153 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); 154 ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); 154 155 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 155 156 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); … … 183 184 ALLOC1(internal_UPDATE_DEPTH ,Tdepth_t ,_param->_nb_inst_update); 184 185 ALLOC1(internal_UPDATE_RAS ,bool ,_param->_nb_inst_update); 186 ALLOC1(internal_EVENT_ACK ,Tcontrol_t,_param->_nb_context); 185 187 186 188 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r95 r97 111 111 112 112 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); 113 DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); 114 DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); 114 115 DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); 115 116 DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); … … 137 138 DELETE1(internal_UPDATE_DEPTH ,_param->_nb_inst_update); 138 139 DELETE1(internal_UPDATE_RAS ,_param->_nb_inst_update); 140 DELETE1(internal_EVENT_ACK ,_param->_nb_context); 139 141 140 142 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
r94 r97 67 67 if (take != 1) 68 68 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); 69 if (addr_dest != addr_good)70 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));69 // if (addr_dest != addr_good) 70 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 71 71 #endif 72 72 … … 85 85 86 86 #ifdef DEBUG_TEST 87 if (addr_dest != addr_good)88 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));87 // if (addr_dest != addr_good) 88 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 89 89 #endif 90 90 … … 103 103 104 104 #ifdef DEBUG_TEST 105 if (addr_dest != addr_good)106 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));105 // if (addr_dest != addr_good) 106 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 107 107 #endif 108 108 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp
r88 r97 8 8 9 9 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" 10 #include "Behavioural/include/Allocation.h" 11 10 12 11 13 namespace morpheo { … … 28 30 param_statistics); 29 31 30 // _stat_nb_branch_hit = new counter_t * [_param->_nb_context]; 31 // _stat_nb_branch_miss = new counter_t * [_param->_nb_context]; 32 // _stat_nb_branch_unused = new counter_t * [_param->_nb_context]; 33 // _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context]; 34 // _stat_queue_nb_cycle_full = new counter_t * [_param->_nb_context]; 35 // _stat_queue_nb_elt = new counter_t * [_param->_nb_context]; 36 37 // for (uint32_t i=0; i<_param->_nb_context; ++i) 38 // { 39 // _stat_nb_branch_hit [i] = _stat->create_counter("nb_branch_hit_" +toString(i),"",toString(_("Branch hit speculation (context %d)"),i)); 40 // _stat_nb_branch_miss [i] = _stat->create_counter("nb_branch_miss_" +toString(i),"",toString(_("Branch miss speculation (context %d)"),i)); 41 // _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i)); 42 // _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i)); 43 // _stat_queue_nb_cycle_full [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i)); 44 // _stat_queue_nb_elt [i] = _stat->create_counter("queue_nb_elt_" +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); 45 // } 46 32 { 33 ALLOC2(_stat_nb_branch_hit ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); 34 ALLOC2(_stat_nb_branch_miss ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); 35 ALLOC1(_stat_nb_branch_unused ,counter_t *,_param->_nb_context); 36 37 for (uint32_t i=0; i<_param->_nb_context; ++i) 38 { 39 std::string sum_miss = "0"; 40 std::string sum_branchement = "0"; 41 42 for (uint32_t j=0; j<MAX_BRANCH_CONDITION; ++j) 43 if (is_branch_condition_valid(j)) 44 { 45 std::string nb_miss = "nb_branch_miss_"+toString(i)+"_"+toString(j); 46 std::string nb_branchement = "+ nb_branch_hit_"+toString(i)+"_"+toString(j)+" nb_branch_miss_"+toString(i)+"_"+toString(j); 47 _stat_nb_branch_hit [i][j] = _stat->create_counter("nb_branch_hit_" +toString(i)+"_"+toString(j),"",toString(_("Branch hit speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 48 _stat_nb_branch_miss [i][j] = _stat->create_counter(nb_miss,"",toString(_("Branch miss speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 49 50 // _stat->create_expr_average("average_miss_"+toString(i)+"_"+toString(j), 51 // "nb_branch_miss_"+toString(i)+"_"+toString(j), 52 // nb_branchement, 53 // "miss/branchement", 54 // toString(_("Average miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 55 56 _stat->create_expr_percent("percent_miss_"+toString(i)+"_"+toString(j), 57 nb_miss, 58 nb_branchement, 59 toString(_("Percent miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i)); 60 61 sum_miss = "+ "+nb_miss +" "+ sum_miss; 62 sum_branchement = "+ "+nb_branchement+" "+sum_branchement; 63 } 64 65 // _stat->create_expr_average("average_miss_"+toString(i), 66 // sum_miss, 67 // sum_branchement, 68 // "miss/branchement", 69 // toString(_("Average miss by branchement (context %d)"),i)); 70 71 _stat->create_expr_percent("percent_miss_"+toString(i), 72 sum_miss, 73 sum_branchement, 74 toString(_("Percent miss by branchement (context %d)"),i)); 75 76 _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused (previous speculation) (context %d)"),i)); 77 } 78 } 79 80 { 81 ALLOC1(_stat_ufpt_queue_nb_elt ,counter_t *,_param->_nb_context); 82 83 for (uint32_t i=0; i<_param->_nb_context; ++i) 84 { 85 _stat_ufpt_queue_nb_elt [i] = _stat->create_counter("ufpt_queue_nb_elt_"+toString(i),"",toString(_("Branchement in Update Fetch Prediction Table (context %d)"),i)); 86 87 _stat->create_expr_average_by_cycle("average_occupation_ufpt_queue_"+toString(i),"ufpt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Fetch Prediction Table (context %d)"),i)); 88 _stat->create_expr_percent ("percent_occupation_ufpt_queue_"+toString(i), "average_occupation_ufpt_queue_"+toString(i), toString(_param->_size_ufpt_queue[i]), toString(_("Percent occupation of Update Fetch Prediction Table (context %d)"),i)); 89 } 90 } 91 92 { 93 ALLOC1(_stat_upt_queue_nb_elt ,counter_t *,_param->_nb_context); 94 95 for (uint32_t i=0; i<_param->_nb_context; ++i) 96 { 97 _stat_upt_queue_nb_elt [i] = _stat->create_counter("upt_queue_nb_elt_"+toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); 98 99 _stat->create_expr_average_by_cycle("average_occupation_upt_queue_"+toString(i),"upt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Prediction Table (context %d)"),i)); 100 _stat->create_expr_percent ("percent_occupation_upt_queue_"+toString(i), "average_occupation_upt_queue_"+toString(i), toString(_param->_size_upt_queue[i]), toString(_("Percent occupation of Update Prediction Table (context %d)"),i)); 101 } 102 } 103 47 104 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 48 105 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
r88 r97 8 8 9 9 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 27 28 28 29 delete _stat; 29 // delete [] _stat_nb_branch_hit ; 30 // delete [] _stat_nb_branch_miss;31 // delete [] _stat_nb_branch_unused;32 // delete [] _stat_queue_nb_cycle_empty;33 // delete [] _stat_queue_nb_cycle_full;34 // delete [] _stat_queue_nb_elt;30 31 DELETE2(_stat_nb_branch_hit ,_param->_nb_context,MAX_BRANCH_CONDITION); 32 DELETE2(_stat_nb_branch_miss ,_param->_nb_context,MAX_BRANCH_CONDITION); 33 DELETE1(_stat_nb_branch_unused ,_param->_nb_context); 34 DELETE1(_stat_ufpt_queue_nb_elt ,_param->_nb_context); 35 DELETE1(_stat_upt_queue_nb_elt ,_param->_nb_context); 35 36 36 37 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r95 r97 472 472 // bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or 473 473 // (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); 474 #ifdef STATISTICS 475 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 476 bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK); 477 #endif 474 478 bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); 475 479 … … 480 484 481 485 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 486 487 #ifdef STATISTICS 488 if (usage_is_set(_usage,USE_STATISTICS)) 489 (*_stat_nb_branch_miss [context][condition])++; 490 #endif 482 491 } 483 492 else … … 486 495 487 496 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; 497 498 499 #ifdef STATISTICS 500 if (usage_is_set(_usage,USE_STATISTICS)) 501 { 502 if (ok) 503 (*_stat_nb_branch_hit [context][condition]) ++; 504 else 505 (*_stat_nb_branch_unused [context]) ++; 506 } 507 #endif 488 508 } 489 509 … … 548 568 // =================================================================== 549 569 for (uint32_t i=0; i<_param->_nb_context; ++i) 550 { 551 //---------------------------------------------------------------- 552 // Cases 553 //---------------------------------------------------------------- 554 // * EVENT_TYPE_NONE - nothing 555 // * EVENT_TYPE_MISS_SPECULATION 556 // * EVENT_STATE_END - Change state, reset pointer 557 // * EVENT_TYPE_EXCEPTION - 558 // * EVENT_STATE_EVENT - Flush upft and upt 559 // * EVENT_STATE_END - Change state, reset pointer 560 // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update 561 // * EVENT_TYPE_SPR_ACCESS - nothing 562 // * EVENT_TYPE_MSYNC - nothing 563 // * EVENT_TYPE_PSYNC - nothing 564 // * EVENT_TYPE_CSYNC - nothing 565 566 Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]); 567 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 568 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 570 if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i]) 571 { 572 //---------------------------------------------------------------- 573 // Cases 574 //---------------------------------------------------------------- 575 // * EVENT_TYPE_NONE - nothing 576 // * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer 577 // * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer 578 // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update 579 // * EVENT_TYPE_SPR_ACCESS - nothing 580 // * EVENT_TYPE_MSYNC - nothing 581 // * EVENT_TYPE_PSYNC - nothing 582 // * EVENT_TYPE_CSYNC - nothing 583 584 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 585 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 569 586 570 // Test if end of miss 571 if ((event_state == EVENT_STATE_END) and 572 (event_type == EVENT_TYPE_MISS_SPECULATION)) 573 { 574 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 575 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END"); 576 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 577 578 #ifdef DEBUG_TEST 579 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 580 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 581 #endif 582 583 // Change state 584 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 585 586 reg_EVENT_STATE [i] = EVENT_STATE_OK; 587 588 // uint32_t bottom = reg_UPT_BOTTOM [i]; 589 590 // reg_UPT_TOP [i] = bottom; 591 // reg_UPT_UPDATE [i] = bottom; 592 } 593 } 587 // Test if end of miss 588 if (event_type == EVENT_TYPE_MISS_SPECULATION) 589 { 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 591 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 592 593 #ifdef DEBUG_TEST 594 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 595 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 596 #endif 597 598 // Change state 599 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 600 601 reg_EVENT_STATE [i] = EVENT_STATE_OK; 602 } 603 } 594 604 595 605 // =================================================================== … … 634 644 } 635 645 646 #ifdef STATISTICS 647 if (usage_is_set(_usage,USE_STATISTICS)) 648 for (uint32_t i=0; i<_param->_nb_context; i++) 649 { 650 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) 651 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) 652 (*_stat_ufpt_queue_nb_elt [i]) ++; 653 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) 654 if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY) 655 (*_stat_upt_queue_nb_elt [i]) ++; 656 } 657 #endif 658 636 659 // =================================================================== 637 660 // =====[ PRINT ]===================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
r95 r97 115 115 116 116 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] 117 public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] 118 public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] 118 119 public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] 119 120 public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r95 r97 136 136 ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); 137 137 138 ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); 138 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); 139 ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); 139 140 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 140 141 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); … … 711 712 #endif 712 713 713 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE"); 714 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_VAL" ,dest, "in_EVENT_"+toString(i)+"_VAL" ); 715 PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ACK" ,dest,"out_EVENT_"+toString(i)+"_ACK" ); 714 716 PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" ); 715 717 if (_param->_have_port_depth) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r95 r97 71 71 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 72 72 73 DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); 73 DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); 74 DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); 74 75 DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); 75 76 DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r88 r97 99 99 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 100 100 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 101 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",T address_t);101 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); 102 102 ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 103 103 ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r95 r97 140 140 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 141 141 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); 142 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,T address_t ,_param->_size_instruction_address);142 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); 143 143 } 144 144 … … 580 580 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , 581 581 dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); 582 } 583 584 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 585 for (uint32_t i=0; i<_param->_nb_context; ++i) 586 { 587 dest = _name+"_glue"; 588 #ifdef POSITION 589 _component->interface_map (src ,"event_"+toString(i), 590 dest,"event_"+toString(i)); 591 #endif 592 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_VAL" , 593 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_VAL" ); 594 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ACK" , 595 dest, "in_EVENT_"+toString(i)+"_PREDICTION_UNIT_ACK" ); 596 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_TYPE" , 597 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_TYPE" ); 598 if (_param->_have_port_depth) 599 COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_DEPTH", 600 dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_DEPTH"); 582 601 } 583 602 … … 967 986 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_IS_DS_TAKE" , 968 987 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_IS_DS_TAKE" ); 988 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_TYPE" , 989 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_TYPE" ); 990 if (_param->_have_port_depth) 991 COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_DEPTH" , 992 dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_DEPTH" ); 969 993 } 970 994 … … 1129 1153 // in_EVENT_IFETCH_UNIT_ACK - component_ifetch_unit 1130 1154 // out_EVENT_IFETCH_UNIT_ADDRESS - component_ifetch_unit 1131 // in_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit1155 // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit 1132 1156 // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL - component_ifetch_unit 1133 1157 // in_EVENT_IFETCH_UNIT_IS_DS_TAKE - component_ifetch_unit 1158 // out_EVENT_PREDICTION_UNIT_VAL - component_prediction_unit 1159 // in_EVENT_PREDICTION_UNIT_ACK - component_prediction_unit 1160 // out_EVENT_PREDICTION_UNIT_TYPE - component_prediction_unit 1161 // out_EVENT_PREDICTION_UNIT_DEPTH - component_prediction_unit 1134 1162 // in_EVENT_CONTEXT_STATE_VAL - component_context_state 1135 1163 // out_EVENT_CONTEXT_STATE_ACK - component_context_state 1136 1164 // in_EVENT_CONTEXT_STATE_ADDRESS - component_context_state 1137 1165 // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT - component_context_state 1138 // out_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state1166 // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state 1139 1167 // in_EVENT_CONTEXT_STATE_IS_DS_TAKE - component_context_state 1168 // in_EVENT_CONTEXT_STATE_TYPE - component_context_state 1169 // in_EVENT_CONTEXT_STATE_DEPTH - component_context_state 1140 1170 1141 1171 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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