- Timestamp:
- Dec 31, 2008, 11:18:08 AM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 37 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg
r88 r98 4 4 1 1 +1 # nb_inst_branch_complete 5 5 0 0 +1 # size_depth [0] [nb_context] 6 3 0 30 +1 # size_address6 32 32 +1 # size_general_data 7 7 1 1 +1 # size_inst_decod [0] [nb_decod_unit] 8 8 1 1 +1 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg
r88 r98 4 4 1 4 *4 # nb_inst_branch_complete 5 5 0 2 +1 # size_depth [0] [nb_context] 6 3 0 30 +1 # size_address6 32 32 +1 # size_general_data 7 7 1 4 *4 # size_inst_decod [0] [nb_decod_unit] 8 8 1 4 *4 # size_inst_commit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg
r88 r98 11 11 1 1 +1 # size_depth [6] [nb_context] 12 12 0 0 +1 # size_depth [7] [nb_context] 13 3 0 30 +1 # size_address13 32 32 +1 # size_general_data 14 14 4 4 *4 # size_inst_decod [0] [nb_decod_unit] 15 15 1 1 *4 # size_inst_decod [1] [nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp
r88 r98 18 18 err (_(" * nb_inst_branch_complete (uint32_t)\n")); 19 19 err (_(" * size_depth [nb_context] (uint32_t)\n")); 20 err (_(" * size_ address(uint32_t)\n"));20 err (_(" * size_general_data (uint32_t)\n")); 21 21 err (_(" * size_inst_decod [nb_decod_unit] (uint32_t)\n")); 22 22 err (_(" * size_inst_commit (uint32_t)\n")); … … 52 52 _size_depth [i] = fromString<uint32_t>(argv[x++]); 53 53 54 uint32_t _size_ address= fromString<uint32_t>(argv[x++]);54 uint32_t _size_general_data = fromString<uint32_t>(argv[x++]); 55 55 56 56 uint32_t * _size_inst_decod = new uint32_t [_nb_decod_unit]; … … 70 70 _nb_inst_branch_complete , 71 71 _size_depth , 72 _size_ address,72 _size_general_data , 73 73 _size_inst_decod , 74 74 _size_inst_commit , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r97 r98 51 51 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 52 52 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); 53 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);53 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 54 54 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 55 55 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); … … 129 129 INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context); 130 130 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 131 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 131 if (_param->_have_port_depth) 132 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 132 133 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 133 134 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); … … 217 218 srand(seed); 218 219 220 const int32_t percent_transaction_branch_event = 75; 219 221 const int32_t percent_transaction_decod_event = 75; 220 222 const int32_t percent_transaction_commit_event = 75; 221 223 //const int32_t percent_transaction_branch_complete = 75; 222 224 const int32_t percent_transaction_event = 75; 223 225 const int32_t percent_transaction_spr = 75; … … 239 241 in_DECOD_EVENT_VAL [i]->write(0); 240 242 in_COMMIT_EVENT_VAL ->write(0); 241 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 242 in_BRANCH_COMPLETE_VAL [i]->write(0); 243 // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 244 // in_BRANCH_COMPLETE_VAL [i]->write(0); 245 for (uint32_t i=0; i<_param->_nb_context; i++) 246 in_BRANCH_EVENT_VAL [i]->write(0); 243 247 244 248 for (uint32_t i=0; i<_param->_nb_context; i++) … … 525 529 in_NB_INST_COMMIT_MEM [context]->write(1); 526 530 527 uint32_t port = rand()%_param->_nb_inst_branch_complete; 528 529 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 531 // uint32_t port = rand()%_param->_nb_inst_branch_complete; 532 533 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 534 // if (_param->_have_port_depth) 535 // in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 536 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 537 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); 538 // in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 539 // in_BRANCH_COMPLETE_TAKE [port]->write(0); 540 541 // TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 542 543 // do 544 // { 545 // in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 546 547 // SC_START(1); 548 // } 549 // while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 550 // out_BRANCH_COMPLETE_ACK [port]->read())); 551 // in_BRANCH_COMPLETE_VAL [port]->write(0); 552 553 uint32_t port = context; 554 530 555 if (_param->_have_port_depth) 531 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 532 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 533 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); 534 in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 535 in_BRANCH_COMPLETE_TAKE [port]->write(0); 536 537 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 538 539 do 540 { 541 in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 542 543 SC_START(1); 544 } 545 while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 546 out_BRANCH_COMPLETE_ACK [port]->read())); 547 in_BRANCH_COMPLETE_VAL [port]->write(0); 556 in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 557 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400); 558 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500); 559 in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0); 560 561 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 562 563 do 564 { 565 in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); 566 567 SC_START(1); 568 } 569 while (not ( in_BRANCH_EVENT_VAL [port]->read() and 570 out_BRANCH_EVENT_ACK [port]->read())); 571 in_BRANCH_EVENT_VAL [port]->write(0); 548 572 549 573 LABEL("miss (wait end)"); … … 595 619 in_NB_INST_COMMIT_MEM [context]->write(1); 596 620 597 uint32_t port = rand()%_param->_nb_inst_branch_complete; 598 599 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 600 if (_param->_have_port_depth) 601 in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 602 in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 603 in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); 604 in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 605 in_BRANCH_COMPLETE_TAKE [port]->write(1); 606 607 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 608 609 do 610 { 611 in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 612 613 SC_START(1); 614 } 615 while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 616 out_BRANCH_COMPLETE_ACK [port]->read())); 617 in_BRANCH_COMPLETE_VAL [port]->write(0); 621 // uint32_t port = rand()%_param->_nb_inst_branch_complete; 622 623 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 624 // if (_param->_have_port_depth) 625 // in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 626 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 627 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); 628 // in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); 629 // in_BRANCH_COMPLETE_TAKE [port]->write(1); 630 631 // TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 632 633 // do 634 // { 635 // in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); 636 637 // SC_START(1); 638 // } 639 // while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and 640 // out_BRANCH_COMPLETE_ACK [port]->read())); 641 // in_BRANCH_COMPLETE_VAL [port]->write(0); 642 643 uint32_t port = context; 644 645 in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 646 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600); 647 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700); 648 in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1); 649 650 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 651 652 do 653 { 654 in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); 655 656 SC_START(1); 657 } 658 while (not ( in_BRANCH_EVENT_VAL [port]->read() and 659 out_BRANCH_EVENT_ACK [port]->read())); 660 in_BRANCH_EVENT_VAL [port]->write(0); 618 661 619 662 LABEL("miss (wait end)"); … … 1238 1281 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context); 1239 1282 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 1240 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);1283 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 1241 1284 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 1242 1285 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r97 r98 67 67 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_ACK ;//[nb_context] 68 68 //public : SC_IN (Tcontext_t ) ** in_BRANCH_EVENT_CONTEXT_ID ;//[nb_context] 69 //public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context]70 //public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context] 69 public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context] 70 //public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context]// always 71 71 public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] 72 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context] 72 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context]// take or not 73 73 public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_DEST ;//[nb_context] 74 74 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h
r88 r98 29 29 public : uint32_t * _array_size_depth ; //[nb_context] 30 30 //public : uint32_t * _size_depth ; //[nb_context] 31 //public : uint32_t _size_ address;31 //public : uint32_t _size_general_data ; 32 32 //public : uint32_t * _size_nb_inst_decod ; //[nb_decod_unit] 33 33 //public : uint32_t _size_nb_inst_commit ; … … 39 39 uint32_t nb_inst_branch_complete, 40 40 uint32_t * size_depth, 41 uint32_t size_ address,41 uint32_t size_general_data, 42 42 uint32_t * size_nb_inst_decod, 43 43 uint32_t size_nb_inst_commit, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r97 r98 63 63 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_ACK ,ACK); 64 64 // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 65 //ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth);65 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 66 66 // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 67 67 ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r97 r98 31 31 DELETE1_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context,1); 32 32 // DELETE1_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 33 //DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth);33 DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 34 34 // DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 35 35 DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r95 r98 40 40 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) 41 41 { 42 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); 43 42 44 // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); 43 45 44 46 context_state_t state = reg_STATE [i]; 45 47 46 Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): 47 0; 48 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; 48 49 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 49 50 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; … … 61 62 // is_valid = can modify local information 62 63 // if context_state_ok : yes 63 // if context_state_ko : test the depth, and the priority of e nvent64 // if context_state_ko : test the depth, and the priority of event 64 65 65 66 bool is_valid = ((state == CONTEXT_STATE_OK) or 66 67 (depth1< depth0) or 67 ((depth1==depth0) and (priority1> priority0)));68 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 68 69 69 70 if (is_valid) … … 76 77 //reg_EVENT_ADDRESS_EEAR [i] = 0; 77 78 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 78 reg_EVENT_IS_DELAY_SLOT [i] = dest_val;79 reg_EVENT_IS_DELAY_SLOT [i] = 1; 79 80 reg_EVENT_IS_DS_TAKE [i] = dest_val; 80 81 reg_EVENT_DEPTH [i] = depth; … … 89 90 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 90 91 { 92 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); 93 91 94 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 92 95 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; … … 190 193 if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) 191 194 { 195 log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); 196 192 197 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; 193 198 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; … … 252 257 // ------------------------------------------------------------------- 253 258 254 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 255 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 256 { 257 if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 258 { 259 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 260 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 261 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 262 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 263 Tdepth_t depth_max = _param->_array_size_depth [context]; 259 // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 260 // if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 261 // { 262 // log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); 263 // if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 264 // { 265 // Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 266 // Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 267 // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 268 // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 269 // Tdepth_t depth_max = _param->_array_size_depth [context]; 264 270 265 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));266 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));267 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));268 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));271 // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 272 // // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 273 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 274 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 269 275 270 context_state_t state = reg_STATE [context];276 // context_state_t state = reg_STATE [context]; 271 277 272 // miss > excep > spr/sync273 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);274 uint8_t priority1 = 2; // miss278 // // miss > excep > spr/sync 279 // uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 280 // uint8_t priority1 = 2; // miss 275 281 276 // is_valid = can modify local information277 // if context_state_ok : yes278 // if context_state_ko : test the depth, and the priority of envent282 // // is_valid = can modify local information 283 // // if context_state_ok : yes 284 // // if context_state_ko : test the depth, and the priority of envent 279 285 280 bool is_valid = ((state == CONTEXT_STATE_OK) or281 (depth1< depth0) or282 ((depth1==depth0) and (priority1>priority0)));286 // bool is_valid = ((state == CONTEXT_STATE_OK) or 287 // (depth1< depth0) or 288 // ((depth1==depth0) and (priority1>priority0))); 283 289 284 if (is_valid)285 {286 // commit287 Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);288 reg_STATE [context] = CONTEXT_STATE_KO_MISS;289 reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT290 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);291 reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence292 //reg_EVENT_ADDRESS_EEAR [context];293 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;294 reg_EVENT_IS_DELAY_SLOT [context] = take;295 reg_EVENT_IS_DS_TAKE [context] = take;296 reg_EVENT_DEPTH [context] = depth;297 }298 }299 }290 // if (is_valid) 291 // { 292 // // commit 293 // Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); 294 // reg_STATE [context] = CONTEXT_STATE_KO_MISS; 295 // reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT 296 // reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); 297 // reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence 298 // //reg_EVENT_ADDRESS_EEAR [context]; 299 // reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 300 // reg_EVENT_IS_DELAY_SLOT [context] = take; 301 // reg_EVENT_IS_DS_TAKE [context] = take; 302 // reg_EVENT_DEPTH [context] = depth; 303 // } 304 // } 305 // } 300 306 301 307 // ------------------------------------------------------------------- … … 305 311 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) 306 312 { 313 log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); 307 314 // Write pc 308 315 context_state_t state = reg_STATE [i]; … … 338 345 if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) 339 346 { 347 log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); 348 340 349 // Write spr 341 350 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp
r88 r98 23 23 uint32_t nb_inst_branch_complete, 24 24 uint32_t * size_depth, 25 uint32_t size_ address,25 uint32_t size_general_data, 26 26 uint32_t * size_nb_inst_decod, 27 27 uint32_t size_nb_inst_commit, … … 35 35 _nb_inst_branch_complete = nb_inst_branch_complete ; 36 36 _array_size_depth = size_depth ; 37 // _size_ address = size_address;37 // _size_general_data = size_general_data ; 38 38 // _size_nb_inst_decod = size_nb_inst_decod ; 39 39 // _size_nb_inst_commit = size_nb_inst_commit ; … … 46 46 _size_context_id = log2(_nb_context); 47 47 _size_depth = log2(max<uint32_t>(size_depth,_nb_context)); 48 _size_instruction_address = size_address; 48 _size_general_data = size_general_data; 49 _size_instruction_address = size_general_data-2; 49 50 _size_nb_inst_decod = max<uint32_t>(size_nb_inst_decod,_nb_decod_unit); 50 51 _size_nb_inst_commit = size_nb_inst_commit; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r88 r98 145 145 // Because, is not ds take, can continue in sequence 146 146 147 #ifdef DEBUG_TEST148 if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))149 throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));150 #endif147 // #ifdef DEBUG_TEST 148 // if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) 149 // throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); 150 // #endif 151 151 152 152 #ifdef STATISTICS -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_decod.cpp
r81 r98 22 22 void Branch_Target_Buffer_Glue::genMealy_decod (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Glue,FUNCTION); 25 log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 27 28 { 29 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * DECOD [%d]",i); 28 30 Tcontrol_t val = PORT_READ(in_DECOD_VAL [i]); 29 31 Tcontrol_t register_ack = PORT_READ(in_DECOD_REGISTER_ACK [i]); 30 32 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM_ACK [i]):true; 31 33 32 PORT_WRITE(out_DECOD_ACK [i], register_ack and victim_ack); 33 PORT_WRITE(out_DECOD_REGISTER_VAL [i], val and victim_ack); 34 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d", val ); 35 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d", register_ack); 36 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d", victim_ack ); 34 37 38 PORT_WRITE(out_DECOD_ACK [i], ( 39 // val and 40 register_ack and 41 victim_ack 42 )); 43 PORT_WRITE(out_DECOD_REGISTER_VAL [i], ( 44 val and 45 // register_ack and 46 victim_ack 47 )); 35 48 if (_param->_have_port_victim) 36 49 { 37 PORT_WRITE(out_DECOD_VICTIM_VAL [i], val and register_ack ); 50 PORT_WRITE(out_DECOD_VICTIM_VAL [i], ( 51 val and 52 register_ack // and 53 // victim_ack 54 )); 38 55 if (not _param->_is_full_associative) 39 PORT_WRITE(out_DECOD_VICTIM_ADDRESS [i], (PORT_READ(in_DECOD_ADDRESS_SRC [i]) >> _param->_shift_bank)&_param->_mask_bank); 56 { 57 Tgeneral_data_t address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); 58 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x", address_src); 59 60 PORT_WRITE(out_DECOD_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); 61 } 40 62 } 41 63 } 42 64 43 log_ printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End");65 log_end(Branch_Target_Buffer_Glue,FUNCTION); 44 66 }; 45 67 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp
r81 r98 22 22 void Branch_Target_Buffer_Glue::genMealy_predict (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Glue,FUNCTION); 25 log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 27 28 { 28 Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; 29 Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); 30 Tgeneral_data_t addr = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); 29 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * PREDICT [%d]",i); 30 Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; 31 Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); 32 Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); 33 34 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * index : %d" ,index ); 35 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * hit : %d" ,hit ); 36 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x",address_src); 31 37 32 38 // Multiplexor 33 39 PORT_WRITE(out_PREDICT_HIT [i],hit); 34 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],addr );40 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],address_src); 35 41 PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],PORT_READ(in_PREDICT_REGISTER_ADDRESS_DEST [i][index])); 36 42 PORT_WRITE(out_PREDICT_CONDITION [i],PORT_READ(in_PREDICT_REGISTER_CONDITION [i][index])); … … 42 48 Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true; 43 49 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true; 50 51 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); 52 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); 53 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); 54 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); 44 55 45 PORT_WRITE(out_PREDICT_ACK [i], register_ack and sort_val and victim_ack); 46 PORT_WRITE(out_PREDICT_REGISTER_VAL [i], val and sort_val and victim_ack); 56 PORT_WRITE(out_PREDICT_ACK [i], ( 57 // val and 58 register_ack and 59 sort_val and 60 victim_ack 61 )); 62 PORT_WRITE(out_PREDICT_REGISTER_VAL [i], ( 63 val and 64 // register_ack and 65 sort_val and 66 victim_ack 67 )); 47 68 48 69 if (_param->_have_port_victim) 49 70 { 50 PORT_WRITE(out_PREDICT_VICTIM_VAL [i], val and register_ack and sort_val ); 71 PORT_WRITE(out_PREDICT_VICTIM_VAL [i], ( 72 val and 73 register_ack and 74 sort_val // and 75 // victim_ack 76 )); 51 77 PORT_WRITE(out_PREDICT_VICTIM_HIT [i], hit); 52 78 if (not _param->_is_full_associative) 53 PORT_WRITE(out_PREDICT_VICTIM_ADDRESS [i], (addr >> _param->_shift_bank)&_param->_mask_bank);79 PORT_WRITE(out_PREDICT_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); 54 80 PORT_WRITE(out_PREDICT_VICTIM_INDEX [i], index); 55 81 } 56 82 } 57 83 58 log_ printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End");84 log_end(Branch_Target_Buffer_Glue,FUNCTION); 59 85 }; 60 86 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_update.cpp
r81 r98 22 22 void Branch_Target_Buffer_Glue::genMealy_update (void) 23 23 { 24 log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); 24 log_begin(Branch_Target_Buffer_Glue,FUNCTION); 25 log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 27 28 { 28 Tcontrol_t val = PORT_READ(in_UPDATE_VAL [i]); 29 Tcontrol_t register_ack = PORT_READ(in_UPDATE_REGISTER_ACK [i]); 30 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM_ACK [i]):true; 29 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * UPDATE [%d]",i); 30 31 Tcontrol_t val = PORT_READ(in_UPDATE_VAL [i]); 32 Tcontrol_t register_ack = PORT_READ(in_UPDATE_REGISTER_ACK [i]); 33 Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM_ACK [i]):true; 34 35 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); 36 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); 37 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); 31 38 32 39 PORT_WRITE(out_UPDATE_ACK [i], register_ack and victim_ack); … … 37 44 PORT_WRITE(out_UPDATE_VICTIM_VAL [i], val and register_ack ); 38 45 if (not _param->_is_full_associative) 39 PORT_WRITE(out_UPDATE_VICTIM_ADDRESS [i], (PORT_READ(in_UPDATE_ADDRESS_SRC [i]) >> _param->_shift_bank)&_param->_mask_bank); 46 { 47 Tgeneral_data_t address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); 48 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x",address_src); 49 50 PORT_WRITE(out_UPDATE_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); 51 } 40 52 } 41 53 } 42 54 43 log_ printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End");55 log_end(Branch_Target_Buffer_Glue,FUNCTION); 44 56 }; 45 57 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp
r88 r98 48 48 49 49 _mask_bank = gen_mask<Tgeneral_data_t> (_size_victim_address); 50 _shift_bank = log2(max_nb_instruction) +2;50 _shift_bank = log2(max_nb_instruction); 51 51 52 52 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp
r88 r98 60 60 _mask_offset = gen_mask<Tgeneral_data_t> (size_offset); 61 61 _mask_bank = gen_mask<Tgeneral_data_t> (size_bank ); 62 _shift_offset = 2;62 _shift_offset = 0; 63 63 _shift_bank = _shift_offset+size_offset; 64 64 _shift_tag = _shift_bank +size_bank ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp
r88 r98 270 270 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 271 271 272 #ifndef REGISTER_INIT273 if (usage_is_set(_usage,USE_SYSTEMC))274 {275 reg_PREDICT_PRIORITY = 0;276 reg_DECOD_PRIORITY = 0;277 }278 #endif279 280 272 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 281 273 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp
r88 r98 25 25 log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); 26 26 27 if (PORT_READ(in_NRESET)) 28 { 27 29 // Init 28 30 uint32_t decod_unit = reg_DECOD_PRIORITY; … … 262 264 else 263 265 PORT_WRITE(out_DECOD_ACK [i][j], ack[j]); 264 266 } 265 267 log_end(Prediction_unit_Glue,FUNCTION); 266 268 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
r88 r98 24 24 log_begin(Prediction_unit_Glue,FUNCTION); 25 25 log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); 26 26 27 if (PORT_READ(in_NRESET)) 28 { 29 30 // Init 27 31 Tcontrol_t ack [_param->_nb_context]; 28 32 for (uint32_t i=0; i<_param->_nb_context; i++) 29 { 30 ack [i] = 0; 31 32 // if (_param->_have_port_depth) 33 // { 34 // PORT_WRITE(out_DEPTH_TAIL [i],PORT_READ(in_DEPTH_UPT_TAIL [i])); 35 // } 36 // PORT_WRITE(out_DEPTH_NB_BRANCH [i],PORT_READ(in_DEPTH_UPT_NB_BRANCH [i])); 37 } 33 ack [i] = 0; 38 34 39 35 for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) … … 41 37 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); 42 38 43 Tcontrol_t btb_val; 44 Tcontrol_t dir_val; 45 Tcontrol_t ras_val; 46 Tcontrol_t upt_val; 47 48 Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; 39 Tcontrol_t btb_val = false; 40 Tcontrol_t dir_val = false; 41 Tcontrol_t ras_val = false; 42 Tcontrol_t upt_val = false; 43 44 Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); 45 Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); 46 Tcontrol_t ras_ack = PORT_READ(in_PREDICT_RAS_ACK [i]); 47 Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); 48 49 Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority 49 50 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); 50 51 51 52 ack [context] = 1; 52 53 53 54 if (PORT_READ(in_PREDICT_VAL[context]) == 0) 54 55 { 55 56 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); 56 57 57 btb_val = false;58 dir_val = false;59 ras_val = false;60 upt_val = false;58 // btb_val = false; 59 // dir_val = false; 60 // ras_val = false; 61 // upt_val = false; 61 62 } 62 63 else … … 67 68 Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); 68 69 Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); 70 71 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x",pc_previous ); 72 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x",pc_current ); 73 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); 69 74 70 75 Taddress_t pc_next ; … … 75 80 76 81 // STEP (1) - Compute the address source 82 // if pc_current is a ds take, then pc_previous is a branchement 77 83 Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; 78 84 Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 79 85 Taddress_t address_msb; 80 86 81 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%x",address); 87 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x",address); 88 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); 82 89 83 90 // STEP (2) - Test if branch (access at branch_target_buffer) 84 91 btb_val = true; 85 ack [context] &= PORT_READ(in_PREDICT_BTB_ACK [i]);86 92 87 93 if (_param->_have_port_context_id) 88 94 PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); 89 95 PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); 96 97 ack [context] &= btb_ack; 98 99 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); 100 101 // BTB_ack = 0 ? 102 if (not btb_ack) 103 continue; 90 104 91 105 // special case : … … 95 109 Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); 96 110 111 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit : %d" ,hit); 112 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); 113 97 114 // STEP (3) : Test if have branch in the packet 98 115 if (hit == 1) 99 116 { 100 117 // STEP (3a) : branch - test condition 101 102 118 bool use_dir = false; 103 119 bool use_ras = false; 104 120 bool use_upt = false; 105 121 106 Tbranch_condition_t cond 122 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 107 123 Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 108 124 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 109 Tcontrol_t push ;125 Tcontrol_t push ; 110 126 Tcontrol_t direction; 111 127 112 switch (cond) 128 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); 129 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); 130 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); 131 132 switch (condition) 113 133 { 114 134 case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j … … 188 208 if (use_dir) 189 209 { 190 ack[context] &= PORT_READ(in_PREDICT_DIR_ACK [i]);210 ack[context] &= dir_ack; 191 211 PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); 192 212 PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take … … 196 216 if (use_ras) 197 217 { 198 ack[context] &= PORT_READ(in_PREDICT_RAS_ACK [i]);218 ack[context] &= ras_ack; 199 219 if (_param->_have_port_context_id) 200 220 PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); … … 207 227 if (use_upt) 208 228 { 209 ack[context] &= PORT_READ(in_PREDICT_UPT_ACK [i]);229 ack[context] &= upt_ack; 210 230 231 if (_param->_have_port_context_id) 211 232 PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); 212 233 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); 213 234 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); 214 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],cond );235 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); 215 236 PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); 216 237 PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); … … 225 246 // * use_ras and ras_ack 226 247 // * use_upt and upt_ack 227 // ack [context] = (PORT_READ(in_PREDICT_BTB_ACK [i]) and 228 // (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i])) and 229 // (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])) and 230 // (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i]))); 231 232 dir_val = (use_dir and 233 PORT_READ(in_PREDICT_BTB_ACK [i]) and 234 (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i]))) and 235 (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); 236 237 ras_val = (use_ras and 238 PORT_READ(in_PREDICT_BTB_ACK [i]) and 239 (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and 240 (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); 241 242 upt_val = (use_upt and 243 PORT_READ(in_PREDICT_BTB_ACK [i]) and 244 (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and 245 (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])))); 248 // ack [context] = (btb_ack and 249 // (use_dir and dir_ack) and 250 // (use_ras and ras_ack) and 251 // (use_upt and upt_ack)); 252 253 dir_val = (btb_ack and 254 use_dir and 255 // use_ras and 256 // use_upt and 257 // (not use_dir or (use_dir and dir_ack)) and 258 (not use_ras or (use_ras and ras_ack)) and 259 (not use_upt or (use_upt and upt_ack))); 260 261 ras_val = (btb_ack and 262 // use_dir and 263 use_ras and 264 // use_upt and 265 (not use_dir or (use_dir and dir_ack)) and 266 // (not use_ras or (use_ras and ras_ack)) and 267 (not use_upt or (use_upt and upt_ack))); 268 269 upt_val = (btb_ack and 270 // use_dir and 271 // use_ras and 272 use_upt and 273 (not use_dir or (use_dir and dir_ack)) and 274 (not use_ras or (use_ras and ras_ack))// and 275 // (not use_upt or (use_upt and upt_ack)) 276 ); 246 277 247 278 // pc_next - is previously computed … … 252 283 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); 253 284 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); 285 254 286 if (address_src_lsb == (_param->_nb_instruction [context]-1)) 255 287 { … … 288 320 PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); 289 321 322 Taddress_t address_limit_min = address_lsb; 323 Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); 324 290 325 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); 291 326 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); 292 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_lsb);293 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_l sb,((pc_current_is_ds_take)?1:address_msb));294 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0", ((pc_current_is_ds_take)?1:address_msb),_param->_nb_instruction [context]);295 296 for (uint32_t j=0; j<address_l sb; j++)327 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); 328 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); 329 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); 330 331 for (uint32_t j=0; j<address_limit_min; j++) 297 332 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid 298 for (uint32_t j=address_l sb; j<((pc_current_is_ds_take)?1:address_msb); j++)333 for (uint32_t j=address_limit_min; j<address_limit_max; j++) 299 334 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Vald packet 300 for (uint32_t j= ((pc_current_is_ds_take)?1:address_msb); j<_param->_nb_instruction [context]; j++)335 for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) 301 336 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid 302 337 if (_param->_have_port_inst_ifetch_ptr) … … 316 351 for (uint32_t i=0; i<_param->_nb_context; i++) 317 352 PORT_WRITE(out_PREDICT_ACK[i],ack[i]); 353 } 318 354 319 355 log_end(Prediction_unit_Glue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp
r88 r98 23 23 { 24 24 log_begin(Prediction_unit_Glue,FUNCTION); 25 log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); 25 26 26 // for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) 27 // { 28 // Tcontrol_t btb_ack = PORT_READ(in_UPDATE_BTB_ACK [i]); 29 // Tcontrol_t dir_ack = PORT_READ(in_UPDATE_DIR_ACK [i]); 30 // Tcontrol_t ras_ack = PORT_READ(in_UPDATE_RAS_ACK [i]); 31 // Tcontrol_t upt_val = PORT_READ(in_UPDATE_UPT_VAL [i]); 27 for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) 28 { 29 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * UPDATE [%d]",i); 30 Tcontrol_t btb_ack = PORT_READ(in_UPDATE_BTB_ACK [i]); 31 Tcontrol_t dir_ack = PORT_READ(in_UPDATE_DIR_ACK [i]); 32 Tcontrol_t ras_ack = PORT_READ(in_UPDATE_RAS_ACK [i]); 33 Tcontrol_t upt_val = PORT_READ(in_UPDATE_UPT_VAL [i]); 32 34 33 // Tcontrol_t need_btb= PORT_READ(in_UPDATE_UPT_BTB_VAL [i]);34 // Tcontrol_t need_dir= PORT_READ(in_UPDATE_UPT_DIR_VAL [i]);35 // Tcontrol_t need_ras= PORT_READ(in_UPDATE_UPT_RAS_VAL [i]);35 Tcontrol_t upt_btb_val = PORT_READ(in_UPDATE_UPT_BTB_VAL [i]); 36 Tcontrol_t upt_dir_val = PORT_READ(in_UPDATE_UPT_DIR_VAL [i]); 37 Tcontrol_t upt_ras_val = PORT_READ(in_UPDATE_UPT_RAS_VAL [i]); 36 38 37 // PORT_WRITE(out_UPDATE_BTB_VAL [i], (upt_val and need_btb and 38 // (not need_dir or (need_dir and dir_ack)) and 39 // (not need_ras or (need_ras and ras_ack)))); 39 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_val : %d",upt_val); 40 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_btb_val - btb_ack : %d - %d",upt_btb_val, btb_ack); 41 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_dir_val - dir_ack : %d - %d",upt_dir_val, dir_ack); 42 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_ras_val - ras_ack : %d - %d",upt_ras_val, ras_ack); 40 43 41 // PORT_WRITE(out_UPDATE_DIR_VAL [i], (upt_val and need_dir and 42 // (not need_btb or (need_btb and btb_ack)) and 43 // (not need_ras or (need_ras and ras_ack)))); 44 Tcontrol_t btb_val = (upt_val and 45 upt_btb_val and 46 // upt_dir_val and 47 // upt_ras_val and 48 // (not upt_btb_val or (upt_btb_val and btb_ack)) and 49 (not upt_dir_val or (upt_dir_val and dir_ack)) and 50 (not upt_ras_val or (upt_ras_val and ras_ack)) 51 ); 44 52 45 // PORT_WRITE(out_UPDATE_RAS_VAL [i], (upt_val and need_ras and 46 // (not need_btb or (need_btb and btb_ack)) and 47 // (not need_dir or (need_dir and dir_ack)))); 53 Tcontrol_t dir_val = (upt_val and 54 // upt_btb_val and 55 upt_dir_val and 56 // upt_ras_val and 57 (not upt_btb_val or (upt_btb_val and btb_ack)) and 58 // (not upt_dir_val or (upt_dir_val and dir_ack)) and 59 (not upt_ras_val or (upt_ras_val and ras_ack)) 60 ); 48 61 49 // PORT_WRITE(out_UPDATE_UPT_ACK [i], ((not need_btb or (need_btb and btb_ack)) and 50 // (not need_dir or (need_dir and dir_ack)) and 51 // (not need_ras or (need_ras and ras_ack)))); 52 // } 62 Tcontrol_t ras_val = (upt_val and 63 // upt_btb_val and 64 // upt_dir_val and 65 upt_ras_val and 66 (not upt_btb_val or (upt_btb_val and btb_ack)) and 67 (not upt_dir_val or (upt_dir_val and dir_ack))// and 68 // (not upt_ras_val or (upt_ras_val and ras_ack)) 69 ); 70 71 Tcontrol_t upt_ack = ( 72 // upt_val and 73 // upt_btb_val and 74 // upt_dir_val and 75 // upt_ras_val and 76 (not upt_btb_val or (upt_btb_val and btb_ack)) and 77 (not upt_dir_val or (upt_dir_val and dir_ack)) and 78 (not upt_ras_val or (upt_ras_val and ras_ack)) 79 ); 80 81 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_val : %d",btb_val); 82 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * dir_val : %d",dir_val); 83 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * ras_val : %d",ras_val); 84 85 PORT_WRITE(out_UPDATE_BTB_VAL [i], btb_val); 86 PORT_WRITE(out_UPDATE_DIR_VAL [i], dir_val); 87 PORT_WRITE(out_UPDATE_RAS_VAL [i], ras_val); 88 PORT_WRITE(out_UPDATE_UPT_ACK [i], upt_ack); 89 } 53 90 54 91 log_end(Prediction_unit_Glue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
r97 r98 79 79 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 80 80 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); 81 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ FLAG ," in_BRANCH_COMPLETE_FLAG",Tcontrol_t ,_param->_nb_inst_branch_complete);81 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 82 82 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); 83 83 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 88 88 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 89 89 //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); 90 //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);90 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 91 91 //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); 92 92 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); … … 145 145 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 146 146 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 147 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);147 INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 148 148 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 149 149 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); … … 155 155 //if (_param->_have_port_context_id) 156 156 //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 157 //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 157 if (_param->_have_port_depth) 158 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 158 159 //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 159 160 INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); … … 351 352 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 352 353 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 353 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);354 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 354 355 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 355 356 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); … … 360 361 DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); 361 362 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 362 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context);363 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 363 364 //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); 364 365 DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r97 r98 27 27 Tcontrol_t take_good ; 28 28 Tcontrol_t flag ; 29 Tcontrol_t no_sequence ; 29 30 Tcontrol_t is_accurate ; 30 31 Thistory_t history ; … … 104 105 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 105 106 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); 106 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ FLAG ," in_BRANCH_COMPLETE_FLAG",Tcontrol_t ,_param->_nb_inst_branch_complete);107 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 107 108 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); 108 109 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); … … 112 113 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); 113 114 ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); 114 // ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);115 // ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);115 // ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); 116 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); 116 117 // ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context); 117 118 ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); … … 194 195 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 195 196 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 196 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);197 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 197 198 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 198 199 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); … … 202 203 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context); 203 204 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context); 204 // if (_param->_have_port_context_id) 205 // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 206 // if (_param->_have_port_depth) 207 // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); 208 // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ADDRESS ,_param->_nb_context); 209 // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); 205 //if (_param->_have_port_context_id) 206 //INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); 207 if (_param->_have_port_depth) 208 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); 209 //INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); 210 210 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); 211 211 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context); … … 347 347 request.take_good = 1; 348 348 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 349 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 349 350 request.is_accurate = true; 350 351 request.miss_ifetch = false; … … 486 487 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 487 488 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); 488 in_BRANCH_COMPLETE_ FLAG [port]->write(it_upt->flag);489 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 489 490 490 491 if (_param->_have_port_depth) … … 627 628 request.take_good = 1; 628 629 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 630 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 629 631 request.is_accurate = true; 630 632 request.miss_ifetch = false; … … 704 706 request.take_good = 0; 705 707 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 708 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 706 709 request.is_accurate = true; 707 710 request.miss_ifetch = false; … … 712 715 request.ras_index = (0x87654321)%_param->_size_ras_index[context]; 713 716 request.ufpt_ptr = ufpt_top [context]; 717 request.upt_ptr = upt_top [context]; 714 718 715 719 event = request; … … 786 790 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 787 791 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); 788 in_BRANCH_COMPLETE_ FLAG [port]->write(it_upt->flag);792 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 789 793 790 794 if (_param->_have_port_depth) … … 910 914 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 911 915 have_transaction = true; 912 916 917 TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); 913 918 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 914 919 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); … … 982 987 request.take_good = 1; 983 988 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 989 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 984 990 request.is_accurate = true; 985 991 request.miss_ifetch = false; … … 1059 1065 request.take_good = 0; 1060 1066 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1067 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 1061 1068 request.is_accurate = true; 1062 1069 request.miss_ifetch = false; … … 1067 1074 request.ras_index = (0x87654321)%_param->_size_ras_index[context]; 1068 1075 request.ufpt_ptr = ufpt_top [context]; 1076 request.upt_ptr = upt_top [context]; 1069 1077 1070 1078 event = request; … … 1141 1149 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 1142 1150 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); 1143 in_BRANCH_COMPLETE_ FLAG [port]->write(it_upt->flag);1151 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 1144 1152 1145 1153 if (_param->_have_port_depth) … … 1345 1353 have_transaction = true; 1346 1354 1355 TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); 1347 1356 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 1348 1357 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); … … 1415 1424 request.take_good = 1; 1416 1425 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1426 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 1417 1427 request.is_accurate = true ; 1418 1428 request.miss_ifetch = false; … … 1557 1567 request.take_good = 1; 1558 1568 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 1569 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 1559 1570 request.is_accurate = true ; 1560 1571 request.miss_ifetch = false; … … 1644 1655 it_event->address_good = it_event->address_dest; 1645 1656 it_event->flag = not it_event->flag; 1657 it_event->no_sequence = not it_event->no_sequence; 1646 1658 it_event->take_good = not it_event->take_good; 1647 1659 } … … 1662 1674 in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr ); 1663 1675 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good); 1664 in_BRANCH_COMPLETE_ FLAG [port]->write(it_event->flag);1676 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence ); 1665 1677 1666 1678 if (_param->_have_port_depth) … … 1675 1687 { 1676 1688 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 1677 LABEL(" * CONTEXT_ID %d" ,it_event->context ); 1678 LABEL(" * DEPTH %d" ,it_event->upt_ptr ); 1679 LABEL(" * CONDITION %d" ,it_event->condition ); 1680 LABEL(" * ADDRESS %.8x",it_event->address_good); 1681 LABEL(" * FLAG %d" ,it_event->flag ); 1689 LABEL(" * CONTEXT_ID : %d" ,it_event->context ); 1690 LABEL(" * DEPTH : %d" ,it_event->upt_ptr ); 1691 LABEL(" * CONDITION : %d" ,it_event->condition ); 1692 LABEL(" * ADDRESS : %.8x",it_event->address_good); 1693 LABEL(" * FLAG : %d" ,it_event->flag ); 1694 LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence ); 1682 1695 1683 1696 have_transaction = true; … … 1722 1735 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 1723 1736 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); 1724 in_BRANCH_COMPLETE_ FLAG [port]->write(it_upt->flag);1737 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 1725 1738 1726 1739 if (_param->_have_port_depth) … … 1735 1748 { 1736 1749 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 1737 LABEL(" * CONTEXT_ID %d" ,it_upt->context ); 1738 LABEL(" * DEPTH %d" ,it_upt->upt_ptr ); 1739 LABEL(" * CONDITION %d" ,it_upt->condition ); 1740 LABEL(" * ADDRESS %.8x",it_upt->address_dest); 1741 LABEL(" * FLAG %d" ,it_upt->flag ); 1750 LABEL(" * CONTEXT_ID : %d" ,it_upt->context ); 1751 LABEL(" * DEPTH : %d" ,it_upt->upt_ptr ); 1752 LABEL(" * CONDITION : %d" ,it_upt->condition ); 1753 LABEL(" * ADDRESS : %.8x",it_upt->address_dest); 1754 LABEL(" * FLAG : %d" ,it_upt->flag ); 1755 LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence ); 1742 1756 1743 1757 have_transaction = true; … … 1953 1967 LABEL(" * event.take : %.8x,",event.take ); 1954 1968 1969 TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); 1955 1970 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 1956 1971 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good); … … 2120 2135 delete [] in_BRANCH_COMPLETE_DEPTH ; 2121 2136 delete [] in_BRANCH_COMPLETE_ADDRESS ; 2122 delete [] in_BRANCH_COMPLETE_ FLAG;2137 delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; 2123 2138 delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; 2124 2139 delete [] out_BRANCH_COMPLETE_TAKE ; … … 2129 2144 delete [] out_BRANCH_EVENT_VAL ; 2130 2145 delete [] in_BRANCH_EVENT_ACK ; 2131 //delete [] in_BRANCH_EVENT_CONTEXT_ID ;2132 //delete [] in_BRANCH_EVENT_DEPTH ;2146 //delete [] out_BRANCH_EVENT_CONTEXT_ID ; 2147 delete [] out_BRANCH_EVENT_DEPTH ; 2133 2148 //delete [] out_BRANCH_EVENT_MISS_PREDICTION; 2134 2149 delete [] out_BRANCH_EVENT_ADDRESS_SRC ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r97 r98 106 106 public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ; //[nb_inst_branch_complete] 107 107 public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ; //[nb_inst_branch_complete] 108 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ FLAG; //[nb_inst_branch_complete]108 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ; //[nb_inst_branch_complete] 109 109 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION; //[nb_inst_branch_complete] 110 110 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_TAKE ; //[nb_inst_branch_complete] … … 116 116 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] 117 117 //public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] 118 //public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context]118 public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] 119 119 //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] is always miss prediction 120 120 public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] … … 176 176 177 177 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 178 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] 178 179 private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch 179 180 private : Tcontrol_t * reg_EVENT_ADDRESS_DEST_VAL ; //[nb_context] // if miss ifetch, decod issue branch, dest must be reload -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp
r97 r98 161 161 if (_param->_have_port_depth) 162 162 sensitive << (*(in_BRANCH_COMPLETE_DEPTH [i])); 163 sensitive << (*(in_BRANCH_COMPLETE_ FLAG[i]))163 sensitive << (*(in_BRANCH_COMPLETE_NO_SEQUENCE [i])) 164 164 << (*(in_BRANCH_COMPLETE_ADDRESS [i])); 165 165 } … … 173 173 if (_param->_have_port_depth) 174 174 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 175 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_ FLAG[i]));175 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_NO_SEQUENCE[i])); 176 176 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); 177 177 … … 180 180 if (_param->_have_port_depth) 181 181 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 182 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_ FLAG[i]));182 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_NO_SEQUENCE[i])); 183 183 184 184 if (_param->_have_port_context_id) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r97 r98 103 103 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 104 104 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 105 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ FLAG ,"flag",Tcontrol_t,1);105 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t,1); 106 106 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 107 107 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); … … 117 117 ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); 118 118 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 119 //ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth);119 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 120 120 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); 121 121 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); … … 203 203 204 204 ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); 205 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 205 206 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 206 207 ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r97 r98 73 73 delete [] in_BRANCH_COMPLETE_DEPTH ; 74 74 delete [] in_BRANCH_COMPLETE_ADDRESS ; 75 delete [] in_BRANCH_COMPLETE_ FLAG;75 delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; 76 76 delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; 77 77 delete [] out_BRANCH_COMPLETE_TAKE ; … … 83 83 DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); 84 84 // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 85 //DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth);85 DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 86 86 // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 87 87 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); … … 156 156 157 157 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 158 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); 158 159 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); 159 160 DELETE1(reg_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
r97 r98 40 40 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition ; 41 41 42 Tcontrol_t flag = PORT_READ(in_BRANCH_COMPLETE_FLAG[i]);42 Tcontrol_t no_sequence = PORT_READ(in_BRANCH_COMPLETE_NO_SEQUENCE [i]); 43 43 Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); 44 44 … … 46 46 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); 47 47 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); 48 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",flag);48 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * no_sequence : %d",no_sequence); 49 49 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_good : %.8x",addr_good); 50 50 … … 74 74 } 75 75 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 76 {77 //addr_dest : compute in decod stage78 //miss if the direction is bad79 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG_UNSET");80 81 Tcontrol_t take_good = not flag; // flag set = not take82 83 miss = (take != take_good);84 take = take_good;85 86 #ifdef DEBUG_TEST87 // if (addr_dest != addr_good)88 // throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));89 #endif90 91 break;92 }93 76 case BRANCH_CONDITION_FLAG_SET : // l.bf 94 77 { 95 78 //addr_dest : compute in decod stage 96 79 //miss if the direction is bad 97 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG _SET");80 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG"); 98 81 99 Tcontrol_t take_good = flag; // flag set = take 82 // Tcontrol_t take_good = not flag; // flag set = not take 83 // Tcontrol_t take_good = flag; // flag set = take 84 Tcontrol_t take_good = no_sequence; 100 85 101 86 miss = (take != take_good); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r95 r98 253 253 254 254 PORT_WRITE(out_BRANCH_EVENT_VAL [i],val); 255 if (_param->_have_port_depth) 256 PORT_WRITE(out_BRANCH_EVENT_DEPTH [i],reg_EVENT_DEPTH [i]); 255 257 PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]); 256 258 PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST_VAL [i],reg_EVENT_ADDRESS_DEST_VAL [i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r97 r98 213 213 flush_UFPT [context] = true; 214 214 215 reg_EVENT_DEPTH [context] = upt_ptr_write; 215 216 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 216 217 reg_EVENT_ADDRESS_DEST_VAL[context] = last_take; … … 303 304 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) 304 305 { 305 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;306 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;306 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 307 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 307 308 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; 308 309 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; … … 375 376 // else no update 376 377 378 reg_EVENT_DEPTH [context] = depth; 377 379 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 378 380 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; … … 668 670 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); 669 671 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 672 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 670 673 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); 671 674 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
r97 r98 98 98 public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ; //[nb_inst_branch_complete] 99 99 public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ; //[nb_inst_branch_complete] 100 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ FLAG; //[nb_inst_branch_complete]100 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ; //[nb_inst_branch_complete] 101 101 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ; //[nb_inst_branch_complete] 102 102 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_TAKE ; //[nb_inst_branch_complete] … … 108 108 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] 109 109 //public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] 110 //public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context]110 public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] 111 111 //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] 112 112 public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r97 r98 102 102 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 103 103 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); 104 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ FLAG ,"flag",Tcontrol_t,1);104 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t,1); 105 105 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 106 106 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); … … 116 116 ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); 117 117 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 118 //ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth);118 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 119 119 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); 120 120 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); … … 675 675 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , 676 676 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); 677 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ FLAG",678 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ FLAG");677 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" , 678 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" ); 679 679 PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", 680 680 dest,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); … … 698 698 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); 699 699 PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); 700 if (_param->_have_port_depth) 701 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); 700 702 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); 701 703 PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r97 r98 56 56 DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); 57 57 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 58 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete,1);58 DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); 59 59 DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); 60 60 DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r97 r98 88 88 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 89 89 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); 90 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ FLAG ," in_BRANCH_COMPLETE_FLAG",Tcontrol_t ,_param->_nb_inst_branch_complete);90 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 91 91 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); 92 92 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); … … 176 176 INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 177 177 INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 178 INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);178 INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 179 179 INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 180 180 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL ); … … 330 330 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 331 331 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 332 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);332 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 333 333 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 334 334 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h
r88 r98 116 116 public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] 117 117 public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] 118 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ FLAG;//[nb_inst_branch_complete]118 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] 119 119 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] 120 120 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r97 r98 123 123 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); 124 124 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); 125 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ FLAG ,"FLAG",Tcontrol_t ,1 );125 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); 126 126 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); 127 127 } … … 538 538 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , 539 539 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); 540 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ FLAG",541 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ FLAG");540 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE", 541 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE"); 542 542 543 543 dest = _name+"_context_state"; … … 570 570 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , 571 571 // dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); 572 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , 573 // dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); 572 if (_param->_have_port_depth) 573 COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , 574 dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); 574 575 // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" , 575 576 // dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
r88 r98 70 70 DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); 71 71 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); 72 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete,1 );72 DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); 73 73 DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); 74 74
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