[111] | 1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
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| 2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
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| 3 | |
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| 4 | <header> |
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| 5 | <!-- ISE source project file created by Project Navigator. --> |
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| 6 | <!-- --> |
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| 7 | <!-- This file contains project source information including a list of --> |
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| 8 | <!-- project source files, project and process properties. This file, --> |
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| 9 | <!-- along with the project source files, is sufficient to open and --> |
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| 10 | <!-- implement in ISE Project Navigator. --> |
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| 11 | <!-- --> |
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[139] | 12 | <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> |
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[111] | 13 | </header> |
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| 14 | |
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[139] | 15 | <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> |
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[111] | 16 | |
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| 17 | <files> |
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[139] | 18 | <file xil_pn:name="../NOC/Arbiter.vhd" xil_pn:type="FILE_VHDL"> |
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[136] | 19 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
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| 20 | <association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
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[111] | 21 | <library xil_pn:name="NoCLib"/> |
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| 22 | </file> |
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[139] | 23 | <file xil_pn:name="../NOC/conv.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 24 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 25 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 26 | <library xil_pn:name="NoCLib"/> |
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| 27 | </file> |
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[139] | 28 | <file xil_pn:name="../NOC/CoreTypes.vhd" xil_pn:type="FILE_VHDL"> |
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[136] | 29 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
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| 30 | <association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
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[111] | 31 | <library xil_pn:name="NoCLib"/> |
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| 32 | </file> |
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[139] | 33 | <file xil_pn:name="../NOC/Crossbar.vhd" xil_pn:type="FILE_VHDL"> |
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| 34 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> |
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| 35 | <association xil_pn:name="Implementation" xil_pn:seqID="24"/> |
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[111] | 36 | <library xil_pn:name="NoCLib"/> |
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| 37 | </file> |
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[139] | 38 | <file xil_pn:name="../NOC/Crossbit.vhd" xil_pn:type="FILE_VHDL"> |
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| 39 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> |
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| 40 | <association xil_pn:name="Implementation" xil_pn:seqID="20"/> |
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[111] | 41 | <library xil_pn:name="NoCLib"/> |
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| 42 | </file> |
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[139] | 43 | <file xil_pn:name="../NOC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL"> |
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| 44 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> |
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| 45 | <association xil_pn:name="Implementation" xil_pn:seqID="19"/> |
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[111] | 46 | <library xil_pn:name="NoCLib"/> |
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| 47 | </file> |
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[139] | 48 | <file xil_pn:name="../NOC/FIFO_DP.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 49 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 50 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 51 | <library xil_pn:name="NoCLib"/> |
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| 52 | </file> |
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[139] | 53 | <file xil_pn:name="../NOC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> |
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| 54 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> |
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| 55 | <association xil_pn:name="Implementation" xil_pn:seqID="23"/> |
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[111] | 56 | <library xil_pn:name="NoCLib"/> |
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| 57 | </file> |
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[139] | 58 | <file xil_pn:name="../NOC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> |
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| 59 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> |
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| 60 | <association xil_pn:name="Implementation" xil_pn:seqID="22"/> |
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[111] | 61 | <library xil_pn:name="NoCLib"/> |
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| 62 | </file> |
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[139] | 63 | <file xil_pn:name="../NOC/PortRam.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 64 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 65 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 66 | <library xil_pn:name="NoCLib"/> |
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| 67 | </file> |
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[139] | 68 | <file xil_pn:name="../NOC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL"> |
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| 69 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 70 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 71 | <library xil_pn:name="NoCLib"/> |
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| 72 | </file> |
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[139] | 73 | <file xil_pn:name="../NOC/proto_send.vhd" xil_pn:type="FILE_VHDL"> |
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| 74 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 75 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 76 | <library xil_pn:name="NoCLib"/> |
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| 77 | </file> |
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[139] | 78 | <file xil_pn:name="../NOC/RAM_256.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 79 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 80 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 81 | <library xil_pn:name="NoCLib"/> |
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| 82 | </file> |
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[139] | 83 | <file xil_pn:name="../NOC/Scheduler.vhd" xil_pn:type="FILE_VHDL"> |
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| 84 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> |
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| 85 | <association xil_pn:name="Implementation" xil_pn:seqID="21"/> |
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[111] | 86 | <library xil_pn:name="NoCLib"/> |
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| 87 | </file> |
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[139] | 88 | <file xil_pn:name="../NOC/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL"> |
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[136] | 89 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
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| 90 | <association xil_pn:name="Implementation" xil_pn:seqID="18"/> |
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| 91 | <library xil_pn:name="NoCLib"/> |
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| 92 | </file> |
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[139] | 93 | <file xil_pn:name="../NOC/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 94 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
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| 95 | <association xil_pn:name="Implementation" xil_pn:seqID="17"/> |
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| 96 | <library xil_pn:name="NoCLib"/> |
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| 97 | </file> |
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[139] | 98 | <file xil_pn:name="../NOC/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 99 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
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| 100 | <association xil_pn:name="Implementation" xil_pn:seqID="16"/> |
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| 101 | <library xil_pn:name="NoCLib"/> |
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| 102 | </file> |
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[139] | 103 | <file xil_pn:name="../NOC/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 104 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
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| 105 | <association xil_pn:name="Implementation" xil_pn:seqID="15"/> |
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| 106 | <library xil_pn:name="NoCLib"/> |
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| 107 | </file> |
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[139] | 108 | <file xil_pn:name="../NOC/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 109 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
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| 110 | <association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
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| 111 | <library xil_pn:name="NoCLib"/> |
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| 112 | </file> |
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[139] | 113 | <file xil_pn:name="../NOC/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 114 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
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| 115 | <association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
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| 116 | <library xil_pn:name="NoCLib"/> |
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| 117 | </file> |
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[139] | 118 | <file xil_pn:name="../NOC/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 119 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
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| 120 | <association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
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| 121 | <library xil_pn:name="NoCLib"/> |
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| 122 | </file> |
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[139] | 123 | <file xil_pn:name="../NOC/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 124 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
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| 125 | <association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
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| 126 | <library xil_pn:name="NoCLib"/> |
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| 127 | </file> |
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[139] | 128 | <file xil_pn:name="../NOC/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 129 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
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| 130 | <association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
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| 131 | <library xil_pn:name="NoCLib"/> |
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| 132 | </file> |
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[139] | 133 | <file xil_pn:name="../NOC/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 134 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
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| 135 | <association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
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| 136 | <library xil_pn:name="NoCLib"/> |
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| 137 | </file> |
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[139] | 138 | <file xil_pn:name="../NOC/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 139 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
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| 140 | <association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
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| 141 | <library xil_pn:name="NoCLib"/> |
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| 142 | </file> |
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[139] | 143 | <file xil_pn:name="../NOC/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 144 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
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| 145 | <association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
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| 146 | <library xil_pn:name="NoCLib"/> |
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| 147 | </file> |
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[139] | 148 | <file xil_pn:name="../NOC/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 149 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
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| 150 | <association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
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| 151 | <library xil_pn:name="NoCLib"/> |
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| 152 | </file> |
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[139] | 153 | <file xil_pn:name="../NOC/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 154 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
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| 155 | <association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
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| 156 | <library xil_pn:name="NoCLib"/> |
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| 157 | </file> |
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[139] | 158 | <file xil_pn:name="../NOC/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL"> |
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[111] | 159 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
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| 160 | <association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
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| 161 | <library xil_pn:name="NoCLib"/> |
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| 162 | </file> |
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[139] | 163 | <file xil_pn:name="../NOC/stimuli1.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 164 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 165 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 166 | <library xil_pn:name="NoCLib"/> |
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| 167 | </file> |
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[139] | 168 | <file xil_pn:name="../NOC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL"> |
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| 169 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> |
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| 170 | <association xil_pn:name="Implementation" xil_pn:seqID="25"/> |
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[111] | 171 | <library xil_pn:name="NoCLib"/> |
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| 172 | </file> |
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[139] | 173 | <file xil_pn:name="../NOC/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 174 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 175 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 176 | <library xil_pn:name="NoCLib"/> |
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| 177 | </file> |
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[139] | 178 | <file xil_pn:name="../NOC/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 179 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 180 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 181 | <library xil_pn:name="NoCLib"/> |
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| 182 | </file> |
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[139] | 183 | <file xil_pn:name="../CORE_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL"> |
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| 184 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 185 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 186 | <library xil_pn:name="MPI_HCL"/> |
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| 187 | </file> |
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[139] | 188 | <file xil_pn:name="../CORE_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL"> |
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| 189 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 190 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 191 | <library xil_pn:name="MPI_HCL"/> |
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| 192 | </file> |
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[139] | 193 | <file xil_pn:name="../CORE_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL"> |
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| 194 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 195 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 196 | <library xil_pn:name="MPI_HCL"/> |
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| 197 | </file> |
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[139] | 198 | <file xil_pn:name="../CORE_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL"> |
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| 199 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 200 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 201 | <library xil_pn:name="MPI_HCL"/> |
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| 202 | </file> |
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[139] | 203 | <file xil_pn:name="../CORE_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 204 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 205 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 206 | <library xil_pn:name="MPI_HCL"/> |
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| 207 | </file> |
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[139] | 208 | <file xil_pn:name="../CORE_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 209 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 210 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 211 | <library xil_pn:name="MPI_HCL"/> |
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| 212 | </file> |
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[139] | 213 | <file xil_pn:name="../CORE_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 214 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 215 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 216 | <library xil_pn:name="MPI_HCL"/> |
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| 217 | </file> |
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[139] | 218 | <file xil_pn:name="../CORE_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 219 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 220 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 221 | <library xil_pn:name="MPI_HCL"/> |
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| 222 | </file> |
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[139] | 223 | <file xil_pn:name="../CORE_MPI/Ex5_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 224 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 225 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 226 | <library xil_pn:name="MPI_HCL"/> |
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| 227 | </file> |
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[139] | 228 | <file xil_pn:name="../CORE_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL"> |
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| 229 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 230 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 231 | <library xil_pn:name="MPI_HCL"/> |
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| 232 | </file> |
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[139] | 233 | <file xil_pn:name="../CORE_MPI/FIfo_mem.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 234 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 235 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 236 | <library xil_pn:name="MPI_HCL"/> |
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| 237 | </file> |
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[139] | 238 | <file xil_pn:name="../CORE_MPI/FIfo_proc.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 239 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 240 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 241 | <library xil_pn:name="MPI_HCL"/> |
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| 242 | </file> |
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[139] | 243 | <file xil_pn:name="../CORE_MPI/image_pkg.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 244 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 245 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 246 | <library xil_pn:name="MPI_HCL"/> |
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| 247 | </file> |
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[139] | 248 | <file xil_pn:name="../CORE_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL"> |
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| 249 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 250 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 251 | <library xil_pn:name="MPI_HCL"/> |
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| 252 | </file> |
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[139] | 253 | <file xil_pn:name="../CORE_MPI/MPICORETEST.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 254 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 255 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 256 | <library xil_pn:name="MPI_HCL"/> |
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| 257 | </file> |
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[139] | 258 | <file xil_pn:name="../CORE_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL"> |
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| 259 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 260 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 261 | <library xil_pn:name="MPI_HCL"/> |
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| 262 | </file> |
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[139] | 263 | <file xil_pn:name="../CORE_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL"> |
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| 264 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 265 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 266 | <library xil_pn:name="MPI_HCL"/> |
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| 267 | </file> |
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[139] | 268 | <file xil_pn:name="../CORE_MPI/MPI_PKG.vhd" xil_pn:type="FILE_VHDL"> |
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[111] | 269 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 270 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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| 271 | <library xil_pn:name="MPI_HCL"/> |
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| 272 | </file> |
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[139] | 273 | <file xil_pn:name="../CORE_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL"> |
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| 274 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
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| 275 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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[111] | 276 | <library xil_pn:name="MPI_HCL"/> |
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| 277 | </file> |
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[139] | 278 | <file xil_pn:name="../CORE_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL"> |
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| 279 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 280 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 281 | </file> |
---|
[139] | 282 | <file xil_pn:name="../CORE_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 283 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 284 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 285 | <library xil_pn:name="MPI_HCL"/> |
---|
| 286 | </file> |
---|
[139] | 287 | <file xil_pn:name="../CORE_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 288 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 289 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 290 | <library xil_pn:name="MPI_HCL"/> |
---|
| 291 | </file> |
---|
[139] | 292 | <file xil_pn:name="../CORE_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 293 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 294 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 295 | <library xil_pn:name="MPI_HCL"/> |
---|
| 296 | </file> |
---|
[139] | 297 | <file xil_pn:name="../CORE_MPI/RAM_32_32.vhd" xil_pn:type="FILE_VHDL"> |
---|
[111] | 298 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 299 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 300 | <library xil_pn:name="MPI_HCL"/> |
---|
| 301 | </file> |
---|
[139] | 302 | <file xil_pn:name="../CORE_MPI/RAM_64.vhd" xil_pn:type="FILE_VHDL"> |
---|
[111] | 303 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 304 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 305 | <library xil_pn:name="MPI_HCL"/> |
---|
| 306 | </file> |
---|
[139] | 307 | <file xil_pn:name="../CORE_MPI/RAM_MUX.vhd" xil_pn:type="FILE_VHDL"> |
---|
[111] | 308 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 309 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 310 | <library xil_pn:name="MPI_HCL"/> |
---|
| 311 | </file> |
---|
[139] | 312 | <file xil_pn:name="../CORE_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 313 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 314 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 315 | <library xil_pn:name="MPI_HCL"/> |
---|
| 316 | </file> |
---|
[139] | 317 | <file xil_pn:name="../CORE_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 318 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 319 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 320 | <library xil_pn:name="MPI_HCL"/> |
---|
| 321 | </file> |
---|
[139] | 322 | <file xil_pn:name="../CORE_MPI/test_DMA.vhd" xil_pn:type="FILE_VHDL"> |
---|
[111] | 323 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 324 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 325 | <library xil_pn:name="MPI_HCL"/> |
---|
| 326 | </file> |
---|
| 327 | <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 328 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 329 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 330 | </file> |
---|
| 331 | <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 332 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 333 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 334 | </file> |
---|
| 335 | <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 336 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 337 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 338 | </file> |
---|
| 339 | <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 340 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 341 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 342 | </file> |
---|
| 343 | <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 344 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 345 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 346 | </file> |
---|
| 347 | <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL"> |
---|
[139] | 348 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
[111] | 349 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 350 | </file> |
---|
| 351 | <file xil_pn:name="ipcore_dir/mem_4k8.xco" xil_pn:type="FILE_COREGEN"> |
---|
| 352 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 353 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 354 | </file> |
---|
| 355 | <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN"> |
---|
[139] | 356 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
---|
| 357 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
[111] | 358 | </file> |
---|
[136] | 359 | <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 360 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
---|
| 361 | <association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
---|
| 362 | <library xil_pn:name="NoCLib"/> |
---|
| 363 | </file> |
---|
[139] | 364 | <file xil_pn:name="Nexys4_Master.ucf" xil_pn:type="FILE_UCF"> |
---|
[111] | 365 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 366 | </file> |
---|
[139] | 367 | <file xil_pn:name="../NOC/NOC_tree.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 368 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> |
---|
| 369 | <association xil_pn:name="Implementation" xil_pn:seqID="26"/> |
---|
| 370 | <library xil_pn:name="NoCLib"/> |
---|
| 371 | </file> |
---|
| 372 | <file xil_pn:name="../NOC/test_noc_tree.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 373 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> |
---|
| 374 | <association xil_pn:name="Implementation" xil_pn:seqID="27"/> |
---|
| 375 | </file> |
---|
| 376 | <file xil_pn:name="pinloc.ucf" xil_pn:type="FILE_UCF"> |
---|
[111] | 377 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
---|
| 378 | </file> |
---|
[139] | 379 | <file xil_pn:name="simu_tree.vhd" xil_pn:type="FILE_VHDL"> |
---|
| 380 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> |
---|
| 381 | <association xil_pn:name="PostMapSimulation" xil_pn:seqID="238"/> |
---|
| 382 | <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="238"/> |
---|
| 383 | <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="238"/> |
---|
| 384 | </file> |
---|
[111] | 385 | </files> |
---|
| 386 | |
---|
| 387 | <properties> |
---|
[137] | 388 | <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 389 | <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
---|
[111] | 390 | <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 391 | <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 392 | <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 393 | <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 394 | <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 395 | <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 396 | <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
---|
| 397 | <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 398 | <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 399 | <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> |
---|
| 400 | <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 401 | <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 402 | <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 403 | <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 404 | <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> |
---|
[111] | 405 | <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 406 | <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 407 | <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 408 | <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
---|
| 409 | <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
---|
| 410 | <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
[137] | 411 | <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> |
---|
| 412 | <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> |
---|
[111] | 413 | <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 414 | <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 415 | <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 416 | <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 417 | <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 418 | <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 419 | <property xil_pn:name="Compiled Library Directory" xil_pn:value="modelsim10.1c" xil_pn:valueState="non-default"/> |
---|
[137] | 420 | <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
[111] | 421 | <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 422 | <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
[137] | 423 | <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 424 | <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 425 | <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 426 | <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
[111] | 427 | <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
[137] | 428 | <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
[111] | 429 | <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 430 | <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 431 | <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 432 | <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 433 | <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 434 | <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[111] | 435 | <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 436 | <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 437 | <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 438 | <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 439 | <property xil_pn:name="Custom Do File Behavioral" xil_pn:value="wave.do" xil_pn:valueState="non-default"/> |
---|
[137] | 440 | <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 441 | <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
---|
[111] | 442 | <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 443 | <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 444 | <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
---|
| 445 | <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
---|
[139] | 446 | <property xil_pn:name="Device" xil_pn:value="xc7a100t" xil_pn:valueState="default"/> |
---|
| 447 | <property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/> |
---|
[137] | 448 | <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> |
---|
[111] | 449 | <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 450 | <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[111] | 451 | <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 452 | <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
---|
| 453 | <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 454 | <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 455 | <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[111] | 456 | <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 457 | <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> |
---|
[111] | 458 | <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 459 | <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[111] | 460 | <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 461 | <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
[137] | 462 | <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
[111] | 463 | <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
---|
[137] | 464 | <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 465 | <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
---|
[111] | 466 | <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 467 | <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 468 | <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
---|
| 469 | <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 470 | <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 471 | <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> |
---|
[111] | 472 | <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 473 | <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
---|
| 474 | <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 475 | <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
---|
[137] | 476 | <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> |
---|
[111] | 477 | <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 478 | <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 479 | <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 480 | <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 481 | <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 482 | <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 483 | <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[139] | 484 | <property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
[111] | 485 | <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 486 | <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 487 | <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 488 | <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 489 | <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 490 | <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 491 | <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 492 | <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 493 | <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 494 | <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 495 | <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 496 | <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 497 | <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 498 | <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 499 | <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 500 | <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 501 | <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
---|
[137] | 502 | <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
[111] | 503 | <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
---|
| 504 | <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
---|
| 505 | <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
[137] | 506 | <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> |
---|
[111] | 507 | <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
---|
[139] | 508 | <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="non-default"/> |
---|
[111] | 509 | <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 510 | <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 511 | <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 512 | <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[139] | 513 | <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 514 | <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|test_tree_8x8|behavior" xil_pn:valueState="non-default"/> |
---|
| 515 | <property xil_pn:name="Implementation Top File" xil_pn:value="../NOC/test_noc_tree.vhd" xil_pn:valueState="non-default"/> |
---|
| 516 | <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/test_tree_8x8" xil_pn:valueState="non-default"/> |
---|
[111] | 517 | <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 518 | <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 519 | <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 520 | <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 521 | <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 522 | <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 523 | <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 524 | <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 525 | <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 526 | <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 527 | <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
[137] | 528 | <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> |
---|
[111] | 529 | <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
| 530 | <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 531 | <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 532 | <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 533 | <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
---|
| 534 | <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
---|
| 535 | <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 536 | <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 537 | <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 538 | <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 539 | <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 540 | <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 541 | <property xil_pn:name="Log All Signals In Post-Fit Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 542 | <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 543 | <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 544 | <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 545 | <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 546 | <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 547 | <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
---|
| 548 | <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 549 | <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
---|
| 550 | <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
---|
| 551 | <property xil_pn:name="ModelSim Post-Fit UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 552 | <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 553 | <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 554 | <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 555 | <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[139] | 556 | <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> |
---|
[111] | 557 | <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 558 | <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
---|
| 559 | <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
---|
[137] | 560 | <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="non-default"/> |
---|
[111] | 561 | <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 562 | <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 563 | <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
---|
[137] | 564 | <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
---|
[111] | 565 | <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
---|
| 566 | <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 567 | <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
[111] | 568 | <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 569 | <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 570 | <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 571 | <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 572 | <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 573 | <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 574 | <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 575 | <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 576 | <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 577 | <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 578 | <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 579 | <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 580 | <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 581 | <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 582 | <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 583 | <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 584 | <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 585 | <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 586 | <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[139] | 587 | <property xil_pn:name="Output File Name" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/> |
---|
[111] | 588 | <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[136] | 589 | <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[111] | 590 | <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 591 | <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
[139] | 592 | <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/> |
---|
[111] | 593 | <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 594 | <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 595 | <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 596 | <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
---|
[137] | 597 | <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/> |
---|
[139] | 598 | <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[111] | 599 | <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
---|
| 600 | <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 601 | <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
---|
[139] | 602 | <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="test_tree_8x8_map.vhd" xil_pn:valueState="default"/> |
---|
| 603 | <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="test_tree_8x8_timesim.vhd" xil_pn:valueState="default"/> |
---|
| 604 | <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="test_tree_8x8_synthesis.vhd" xil_pn:valueState="default"/> |
---|
| 605 | <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="test_tree_8x8_translate.vhd" xil_pn:valueState="default"/> |
---|
[137] | 606 | <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 607 | <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
[111] | 608 | <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 609 | <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 610 | <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 611 | <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 612 | <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 613 | <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 614 | <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
---|
| 615 | <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 616 | <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 617 | <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 618 | <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 619 | <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 620 | <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 621 | <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
---|
| 622 | <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
| 623 | <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 624 | <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[137] | 625 | <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> |
---|
[111] | 626 | <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
---|
| 627 | <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 628 | <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
---|
[139] | 629 | <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="test_tree_8x8" xil_pn:valueState="default"/> |
---|
[111] | 630 | <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 631 | <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 632 | <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 633 | <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 634 | <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 635 | <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
---|
| 636 | <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
---|
| 637 | <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 638 | <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 639 | <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 640 | <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 641 | <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[137] | 642 | <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
---|
| 643 | <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> |
---|
[111] | 644 | <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 645 | <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 646 | <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 647 | <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 648 | <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[137] | 649 | <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
[111] | 650 | <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
| 651 | <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
---|
[139] | 652 | <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/simu_tree" xil_pn:valueState="non-default"/> |
---|
| 653 | <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="non-default"/> |
---|
[111] | 654 | <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 655 | <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 656 | <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 657 | <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
[137] | 658 | <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
[111] | 659 | <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[137] | 660 | <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> |
---|
[111] | 661 | <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 662 | <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 663 | <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 664 | <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/> |
---|
| 665 | <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 666 | <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 667 | <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/> |
---|
| 668 | <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 669 | <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 670 | <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/> |
---|
| 671 | <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 672 | <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 673 | <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 674 | <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/> |
---|
[139] | 675 | <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.simu_tree" xil_pn:valueState="default"/> |
---|
[111] | 676 | <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 677 | <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 678 | <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
[137] | 679 | <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
---|
| 680 | <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 681 | <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
[111] | 682 | <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 683 | <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
---|
| 684 | <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/> |
---|
[139] | 685 | <property xil_pn:name="Target UCF File Name" xil_pn:value="pinloc.ucf" xil_pn:valueState="non-default"/> |
---|
[111] | 686 | <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
---|
| 687 | <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
---|
| 688 | <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 689 | <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
---|
| 690 | <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 691 | <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
---|
| 692 | <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
---|
| 693 | <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 694 | <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 695 | <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 696 | <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 697 | <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 698 | <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 699 | <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 700 | <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 701 | <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 702 | <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 703 | <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 704 | <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 705 | <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 706 | <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 707 | <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 708 | <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 709 | <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 710 | <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 711 | <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 712 | <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[137] | 713 | <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
[111] | 714 | <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 715 | <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 716 | <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
[137] | 717 | <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
[111] | 718 | <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
[139] | 719 | <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
---|
| 720 | <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
---|
[111] | 721 | <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
[137] | 722 | <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
[111] | 723 | <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 724 | <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
---|
| 725 | <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
---|
| 726 | <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/> |
---|
| 727 | <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 728 | <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 729 | <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 730 | <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
---|
[137] | 731 | <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 732 | <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> |
---|
| 733 | <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 734 | <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
---|
[111] | 735 | <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 736 | <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
---|
| 737 | <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 738 | <!-- --> |
---|
| 739 | <!-- The following properties are for internal use only. These should not be modified.--> |
---|
| 740 | <!-- --> |
---|
[139] | 741 | <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|simu_tree|behavior" xil_pn:valueState="non-default"/> |
---|
[111] | 742 | <property xil_pn:name="PROP_DesignName" xil_pn:value="Test_Timer" xil_pn:valueState="non-default"/> |
---|
[139] | 743 | <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/> |
---|
[111] | 744 | <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
---|
| 745 | <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 746 | <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 747 | <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 748 | <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 749 | <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 750 | <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
---|
| 751 | <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-02-01T17:22:38" xil_pn:valueState="non-default"/> |
---|
| 752 | <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA1A3B7446F840C680AEF9E0B44A66F1" xil_pn:valueState="non-default"/> |
---|
| 753 | <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
---|
| 754 | <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
---|
| 755 | </properties> |
---|
| 756 | |
---|
[139] | 757 | <bindings> |
---|
| 758 | <binding xil_pn:location="/MultiMPITest" xil_pn:name="Nexys4_Master.ucf"/> |
---|
| 759 | <binding xil_pn:location="/test_tree_8x8" xil_pn:name="pinloc.ucf"/> |
---|
| 760 | </bindings> |
---|
[111] | 761 | |
---|
| 762 | <libraries> |
---|
| 763 | <library xil_pn:name="MPI_HCL"/> |
---|
| 764 | <library xil_pn:name="NoCLib"/> |
---|
| 765 | </libraries> |
---|
| 766 | |
---|
| 767 | <autoManagedFiles> |
---|
| 768 | <!-- The following files are identified by `include statements in verilog --> |
---|
| 769 | <!-- source files and are automatically managed by Project Navigator. --> |
---|
| 770 | <!-- --> |
---|
| 771 | <!-- Do not hand-edit this section, as it will be overwritten when the --> |
---|
| 772 | <!-- project is analyzed based on files automatically identified as --> |
---|
| 773 | <!-- include files. --> |
---|
| 774 | </autoManagedFiles> |
---|
| 775 | |
---|
| 776 | </project> |
---|