source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro

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Diff Rev Age Author Log Message
(edit) @89   11 years szahmed Added Headline comments for Verilog files explaining their brief …
(edit) @87   11 years lambert Adding generation simulation support for verilog
(add) @84   11 years lambert Adding hierarchical subdirectory for every component
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