[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[707] | 2 | // File: top.cpp (for tsar_generic_iob platform) |
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[718] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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[966] | 5 | // Date : august 2013 / updated march 2015 |
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[450] | 6 | // This program is released under the GNU public license |
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| 7 | /////////////////////////////////////////////////////////////////////////////// |
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[938] | 8 | // This file define a generic TSAR architecture with an external IO network |
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| 9 | // emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: |
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[450] | 10 | // |
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[472] | 11 | // - BROM : boot ROM |
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| 12 | // - FBUF : Frame Buffer |
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[730] | 13 | // - MTTY : multi TTY (one channel) |
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[472] | 14 | // - MNIC : Network controller (up to 2 channels) |
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[498] | 15 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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[965] | 16 | // - DISK : Block device controler (BDV / HBA / SDC) |
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[707] | 17 | // - IOPI : HWI to SWI translator. |
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[450] | 18 | // |
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[938] | 19 | // This I/0 bus is connected to internal address space through two IOB bridges |
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[966] | 20 | // located in cluster[0][0] and cluster[X_SIZE-1][Y_SIZE-1]. |
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[938] | 21 | // |
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[707] | 22 | // The internal physical address space is 40 bits, and the cluster index |
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| 23 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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[938] | 24 | // Y is encoded on 4 bits, whatever the actual mesh size. |
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[707] | 25 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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[450] | 26 | // |
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[607] | 27 | // It contains 3 networks: |
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| 28 | // |
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[707] | 29 | // 1) the "INT" network supports Read/Write transactions |
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[718] | 30 | // between processors and L2 caches or peripherals. |
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[450] | 31 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 32 | // It supports also coherence transactions between L1 & L2 caches. |
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[718] | 33 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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[472] | 34 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 35 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 36 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 37 | // 4) the IOX network connects the two IO bridge components to the |
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[707] | 38 | // 7 external peripheral controllers. |
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[450] | 39 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[718] | 40 | // |
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| 41 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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[707] | 42 | // external IOPIC component, that must be configured by the OS to route |
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[874] | 43 | // these WTI IRQS to one or several internal XICU components. |
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[707] | 44 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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[718] | 45 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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[707] | 46 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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[965] | 47 | // - IOPIC HWI[8] connected to IRQ_DISK |
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[874] | 48 | // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] |
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[450] | 49 | // |
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[730] | 50 | // Besides the external peripherals, each cluster contains one XICU component, |
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[707] | 51 | // and one multi channels DMA component. |
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[959] | 52 | // The XICU component is mainly used to handle WTI IRQs, as only |
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| 53 | // 1 + NB_PROCS_MAX HWI IRQs are connected to XICU in each cluster: |
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| 54 | // - IRQ_IN[0] : MMC |
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| 55 | // - IRQ_IN[1] : DMA channel 0 |
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| 56 | // - IRQ_IN[2] : DMA channel 1 |
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| 57 | // - ... ... |
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| 58 | // - IRQ_IN[NB_PROCS_MAX] : DMA channel NB_PROCS_MAX |
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[718] | 59 | // |
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[450] | 60 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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| 61 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 62 | // connected to the three networks (INT, RAM, IOX). |
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[718] | 63 | // |
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[450] | 64 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[718] | 65 | // local interconnect correponding to the INT network. |
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| 66 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 67 | // local interconnect correponding to the coherence INT network. |
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[450] | 68 | // - It uses two virtual_dspin_router per cluster to implement |
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| 69 | // the INT network (routing both the direct and coherence trafic). |
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| 70 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 71 | // - It uses the vci_cc_vcache_wrapper. |
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| 72 | // - It uses the vci_mem_cache. |
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| 73 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 74 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 75 | // |
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| 76 | // The TsarIobCluster component is defined in files |
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| 77 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 78 | // |
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| 79 | // The main hardware parameters must be defined in the hard_config.h file : |
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[966] | 80 | // - X_WIDTH : number of bits for x cluster coordinate |
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| 81 | // - Y_WIDTH : number of bits for y cluster coordinate |
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| 82 | // - P_WIDTH : number of bits for local processor coordinate |
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[718] | 83 | // - X_SIZE : number of clusters in a row |
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[707] | 84 | // - Y_SIZE : number of clusters in a column |
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[959] | 85 | // - NB_PROCS_MAX : number of processors per cluster (up to 8) |
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| 86 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) |
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[874] | 87 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) |
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[707] | 88 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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| 89 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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[714] | 90 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 91 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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[959] | 92 | // - XCU_NB_HWI : number of XCU HWIs (>= NB_PROCS_MAX + 1) |
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| 93 | // - XCU_NB_PTI : number of XCU PTIs (>= NB_PROCS_MAX) |
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| 94 | // - XCU_NB_WTI : number of XCU WTIs (>= 4*NB_PROCS_MAX) |
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| 95 | // - XCU_NB_OUT : number of XCU output IRQs (>= 4*NB_PROCS_MAX) |
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[966] | 96 | // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) |
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[718] | 97 | // |
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[966] | 98 | // Some other hardware parameters must be defined in this top.cpp file: |
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[718] | 99 | // - XRAM_LATENCY : external ram latency |
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[450] | 100 | // - MEMC_WAYS : L2 cache number of ways |
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| 101 | // - MEMC_SETS : L2 cache number of sets |
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[718] | 102 | // - L1_IWAYS |
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| 103 | // - L1_ISETS |
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| 104 | // - L1_DWAYS |
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| 105 | // - L1_DSETS |
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[965] | 106 | // - DISK_IMAGE_NAME : file pathname for block device |
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[450] | 107 | // |
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| 108 | // General policy for 40 bits physical address decoding: |
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| 109 | // All physical segments base addresses are multiple of 1 Mbytes |
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[718] | 110 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[450] | 111 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 112 | // the cluster index, and the LADR bits define the local index: |
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[707] | 113 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 114 | // | 4 | 4 | 8 | 24 | |
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[450] | 115 | // |
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| 116 | // General policy for 14 bits SRCID decoding: |
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| 117 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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[707] | 118 | // |X_ID|Y_ID| L_ID | |
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| 119 | // | 4 | 4 | 6 | |
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[450] | 120 | ///////////////////////////////////////////////////////////////////////// |
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| 121 | |
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| 122 | #include <systemc> |
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| 123 | #include <sys/time.h> |
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| 124 | #include <iostream> |
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| 125 | #include <sstream> |
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| 126 | #include <cstdlib> |
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| 127 | #include <cstdarg> |
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| 128 | #include <stdint.h> |
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| 129 | |
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| 130 | #include "gdbserver.h" |
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| 131 | #include "mapping_table.h" |
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| 132 | |
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| 133 | #include "tsar_iob_cluster.h" |
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| 134 | #include "vci_chbuf_dma.h" |
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| 135 | #include "vci_multi_tty.h" |
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| 136 | #include "vci_multi_nic.h" |
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| 137 | #include "vci_simple_rom.h" |
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[965] | 138 | #include "vci_multi_ahci.h" |
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[450] | 139 | #include "vci_block_device_tsar.h" |
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| 140 | #include "vci_framebuffer.h" |
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| 141 | #include "vci_iox_network.h" |
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[707] | 142 | #include "vci_iopic.h" |
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[450] | 143 | |
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| 144 | #include "alloc_elems.h" |
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| 145 | |
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| 146 | /////////////////////////////////////////////////// |
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| 147 | // OS |
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| 148 | /////////////////////////////////////////////////// |
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| 149 | #define USE_ALMOS 0 |
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| 150 | |
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| 151 | #define almos_bootloader_pathname "bootloader.bin" |
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| 152 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 153 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 154 | |
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| 155 | /////////////////////////////////////////////////// |
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| 156 | // Parallelisation |
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| 157 | /////////////////////////////////////////////////// |
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| 158 | |
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[762] | 159 | #define USING_OPENMP 0 |
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| 160 | |
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| 161 | #if USING_OPENMP |
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[450] | 162 | #include <omp.h> |
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| 163 | #endif |
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| 164 | |
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| 165 | /////////////////////////////////////////////////////////// |
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[718] | 166 | // DSPIN parameters |
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[450] | 167 | /////////////////////////////////////////////////////////// |
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| 168 | |
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| 169 | #define dspin_int_cmd_width 39 |
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| 170 | #define dspin_int_rsp_width 32 |
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| 171 | |
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| 172 | #define dspin_ram_cmd_width 64 |
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| 173 | #define dspin_ram_rsp_width 64 |
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| 174 | |
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| 175 | /////////////////////////////////////////////////////////// |
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[718] | 176 | // VCI fields width for the 3 VCI networks |
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[450] | 177 | /////////////////////////////////////////////////////////// |
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| 178 | |
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| 179 | #define vci_cell_width_int 4 |
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| 180 | #define vci_cell_width_ext 8 |
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| 181 | |
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| 182 | #define vci_plen_width 8 |
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| 183 | #define vci_address_width 40 |
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| 184 | #define vci_rerror_width 1 |
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| 185 | #define vci_clen_width 1 |
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| 186 | #define vci_rflag_width 1 |
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| 187 | #define vci_srcid_width 14 |
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| 188 | #define vci_pktid_width 4 |
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| 189 | #define vci_trdid_width 4 |
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| 190 | #define vci_wrplen_width 1 |
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| 191 | |
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| 192 | //////////////////////////////////////////////////////////// |
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[718] | 193 | // Main Hardware Parameters values |
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[450] | 194 | //////////////////////i///////////////////////////////////// |
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| 195 | |
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[802] | 196 | #include "hard_config.h" |
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[450] | 197 | |
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| 198 | //////////////////////////////////////////////////////////// |
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[718] | 199 | // Secondary Hardware Parameters values |
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[450] | 200 | //////////////////////i///////////////////////////////////// |
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| 201 | |
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[607] | 202 | #define XMAX X_SIZE |
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| 203 | #define YMAX Y_SIZE |
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[450] | 204 | |
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| 205 | #define XRAM_LATENCY 0 |
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| 206 | |
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| 207 | #define MEMC_WAYS 16 |
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| 208 | #define MEMC_SETS 256 |
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| 209 | |
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| 210 | #define L1_IWAYS 4 |
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| 211 | #define L1_ISETS 64 |
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| 212 | |
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| 213 | #define L1_DWAYS 4 |
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| 214 | #define L1_DSETS 64 |
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| 215 | |
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[965] | 216 | #define DISK_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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[450] | 217 | |
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[938] | 218 | #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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[450] | 219 | |
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| 220 | #define NORTH 0 |
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| 221 | #define SOUTH 1 |
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| 222 | #define EAST 2 |
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| 223 | #define WEST 3 |
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| 224 | |
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[693] | 225 | #define cluster(x,y) ((y) + ((x) << 4)) |
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[450] | 226 | |
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| 227 | //////////////////////////////////////////////////////////// |
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[718] | 228 | // DEBUG Parameters default values |
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[450] | 229 | //////////////////////i///////////////////////////////////// |
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| 230 | |
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[914] | 231 | #define MAX_FROZEN_CYCLES 1000000 |
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[450] | 232 | |
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| 233 | ///////////////////////////////////////////////////////// |
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| 234 | // Physical segments definition |
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| 235 | ///////////////////////////////////////////////////////// |
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| 236 | |
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[734] | 237 | // All physical segments base addresses and sizes are defined |
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| 238 | // in the hard_config.h file. For replicated segments, the |
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| 239 | // base address is incremented by a cluster offset: |
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| 240 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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[450] | 241 | |
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| 242 | //////////////////////////////////////////////////////////////////////// |
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| 243 | // SRCID definition |
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| 244 | //////////////////////////////////////////////////////////////////////// |
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| 245 | // All initiators are in the same indexing space (14 bits). |
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| 246 | // The SRCID is structured in two fields: |
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[764] | 247 | // - The 8 MSB bits define the cluster index (left aligned) |
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| 248 | // - The 6 LSB bits define the local index. |
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[718] | 249 | // Two different initiators cannot have the same SRCID, but a given |
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| 250 | // initiator can have two alias SRCIDs: |
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[450] | 251 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 252 | // and each initiator has one single SRCID. |
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[965] | 253 | // - External initiators (disk, cdma) are not replicated, but can be |
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[718] | 254 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 255 | // They have the same local index, but two different cluster indexes. |
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[707] | 256 | // |
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[450] | 257 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[718] | 258 | // and external initiators, they must have different local indexes. |
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[450] | 259 | // Consequence: For a local interconnect, the INI_ID port index |
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| 260 | // is NOT equal to the SRCID local index, and the local interconnect |
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[718] | 261 | // must make a translation: SRCID => INI_ID |
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[450] | 262 | //////////////////////////////////////////////////////////////////////// |
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| 263 | |
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[550] | 264 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 265 | #define MDMA_LOCAL_SRCID 0x8 |
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| 266 | #define IOBX_LOCAL_SRCID 0x9 |
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| 267 | #define MEMC_LOCAL_SRCID 0xA |
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[718] | 268 | #define CDMA_LOCAL_SRCID 0xB |
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[965] | 269 | #define DISK_LOCAL_SRCID 0xC |
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[707] | 270 | #define IOPI_LOCAL_SRCID 0xD |
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[450] | 271 | |
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[550] | 272 | /////////////////////////////////////////////////////////////////////// |
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[450] | 273 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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[550] | 274 | /////////////////////////////////////////////////////////////////////// |
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[450] | 275 | |
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| 276 | #define INT_MEMC_TGT_ID 0 |
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| 277 | #define INT_XICU_TGT_ID 1 |
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| 278 | #define INT_MDMA_TGT_ID 2 |
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| 279 | #define INT_IOBX_TGT_ID 3 |
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| 280 | |
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| 281 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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[707] | 282 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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[450] | 283 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 284 | |
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[550] | 285 | /////////////////////////////////////////////////////////////////////// |
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[450] | 286 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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[550] | 287 | /////////////////////////////////////////////////////////////////////// |
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[450] | 288 | |
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| 289 | #define RAM_XRAM_TGT_ID 0 |
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| 290 | |
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| 291 | #define RAM_MEMC_INI_ID 0 |
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| 292 | #define RAM_IOBX_INI_ID 1 |
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| 293 | |
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[550] | 294 | /////////////////////////////////////////////////////////////////////// |
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[450] | 295 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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[550] | 296 | /////////////////////////////////////////////////////////////////////// |
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[450] | 297 | |
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[718] | 298 | #define IOX_FBUF_TGT_ID 0 |
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[965] | 299 | #define IOX_DISK_TGT_ID 1 |
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[718] | 300 | #define IOX_MNIC_TGT_ID 2 |
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| 301 | #define IOX_CDMA_TGT_ID 3 |
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| 302 | #define IOX_BROM_TGT_ID 4 |
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| 303 | #define IOX_MTTY_TGT_ID 5 |
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| 304 | #define IOX_IOPI_TGT_ID 6 |
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| 305 | #define IOX_IOB0_TGT_ID 7 |
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| 306 | #define IOX_IOB1_TGT_ID 8 |
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[450] | 307 | |
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[965] | 308 | #define IOX_DISK_INI_ID 0 |
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[718] | 309 | #define IOX_CDMA_INI_ID 1 |
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| 310 | #define IOX_IOPI_INI_ID 2 |
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| 311 | #define IOX_IOB0_INI_ID 3 |
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| 312 | #define IOX_IOB1_INI_ID 4 |
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[450] | 313 | |
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[550] | 314 | //////////////////////////////////////////////////////////////////////// |
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[450] | 315 | int _main(int argc, char *argv[]) |
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[550] | 316 | //////////////////////////////////////////////////////////////////////// |
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[450] | 317 | { |
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| 318 | using namespace sc_core; |
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| 319 | using namespace soclib::caba; |
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| 320 | using namespace soclib::common; |
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| 321 | |
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[938] | 322 | char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code |
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| 323 | size_t ncycles = 4000000000; // simulated cycles |
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[965] | 324 | char disk_name[256] = DISK_IMAGE_NAME; // pathname: disk image |
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[966] | 325 | ssize_t threads = 1; // simulator's threads number |
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[938] | 326 | bool debug_ok = false; // trace activated |
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| 327 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 328 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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| 329 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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| 330 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 331 | uint32_t debug_from = 0; // trace start cycle |
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| 332 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 333 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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| 334 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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| 335 | size_t x_width = X_WIDTH; // # of bits for x |
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| 336 | size_t y_width = Y_WIDTH; // # of bits for y |
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| 337 | size_t p_width = P_WIDTH; // # of bits for lpid |
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[450] | 338 | |
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[762] | 339 | #if USING_OPENMP |
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| 340 | size_t simul_period = 1000000; |
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| 341 | #else |
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| 342 | size_t simul_period = 1; |
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| 343 | #endif |
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| 344 | |
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[607] | 345 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 346 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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[718] | 347 | |
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[818] | 348 | assert( P_WIDTH <= 4 and |
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| 349 | "ERROR: we must have P_WIDTH <= 4"); |
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[802] | 350 | |
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[450] | 351 | ////////////// command line arguments ////////////////////// |
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| 352 | if (argc > 1) |
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| 353 | { |
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| 354 | for (int n = 1; n < argc; n = n + 2) |
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| 355 | { |
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| 356 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 357 | { |
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| 358 | ncycles = atoi(argv[n+1]); |
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| 359 | } |
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| 360 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 361 | { |
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| 362 | debug_ok = true; |
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| 363 | debug_from = atoi(argv[n+1]); |
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| 364 | } |
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| 365 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 366 | { |
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| 367 | strcpy(disk_name, argv[n+1]); |
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| 368 | } |
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| 369 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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| 370 | { |
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| 371 | debug_memc_id = atoi(argv[n+1]); |
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[607] | 372 | size_t x = debug_memc_id >> 4; |
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| 373 | size_t y = debug_memc_id & 0xF; |
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| 374 | if( (x>=XMAX) || (y>=YMAX) ) |
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| 375 | { |
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[966] | 376 | std::cout << "MEMCID parameter doesn't fit XMAX/YMAX" << std::endl; |
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[914] | 377 | std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; |
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| 378 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
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| 379 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
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[607] | 380 | exit(0); |
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| 381 | } |
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[450] | 382 | } |
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[707] | 383 | else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1<argc) ) |
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| 384 | { |
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| 385 | debug_xram_id = atoi(argv[n+1]); |
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| 386 | size_t x = debug_xram_id >> 4; |
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| 387 | size_t y = debug_xram_id & 0xF; |
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| 388 | if( (x>=XMAX) || (y>=YMAX) ) |
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| 389 | { |
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| 390 | std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; |
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| 391 | exit(0); |
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| 392 | } |
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| 393 | } |
---|
[450] | 394 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
---|
| 395 | { |
---|
| 396 | debug_iob = atoi(argv[n+1]); |
---|
| 397 | } |
---|
| 398 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
---|
| 399 | { |
---|
[607] | 400 | debug_proc_id = atoi(argv[n+1]); |
---|
[802] | 401 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
[607] | 402 | size_t x = cluster_xy >> 4; |
---|
| 403 | size_t y = cluster_xy & 0xF; |
---|
| 404 | if( (x>=XMAX) || (y>=YMAX) ) |
---|
| 405 | { |
---|
| 406 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
---|
[914] | 407 | std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; |
---|
| 408 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
---|
| 409 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
---|
[607] | 410 | exit(0); |
---|
| 411 | } |
---|
[450] | 412 | } |
---|
| 413 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
---|
| 414 | { |
---|
[966] | 415 | threads = atoi(argv[n+1]); |
---|
| 416 | threads = (threads < 1) ? 1 : threads; |
---|
[450] | 417 | } |
---|
| 418 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
| 419 | { |
---|
| 420 | frozen_cycles = atoi(argv[n+1]); |
---|
| 421 | } |
---|
| 422 | else |
---|
| 423 | { |
---|
| 424 | std::cout << " Arguments are (key,value) couples." << std::endl; |
---|
| 425 | std::cout << " The order is not important." << std::endl; |
---|
| 426 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
[938] | 427 | std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 428 | std::cout << " - DEBUG debug_start_cycle" << std::endl; |
---|
| 429 | std::cout << " - THREADS simulator's threads number" << std::endl; |
---|
| 430 | std::cout << " - FROZEN max_number_of_lines" << std::endl; |
---|
| 431 | std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 432 | std::cout << " - PROCID index_proc_to_be_traced" << std::endl; |
---|
| 433 | std::cout << " - IOB non_zero_value" << std::endl; |
---|
[450] | 434 | exit(0); |
---|
| 435 | } |
---|
| 436 | } |
---|
| 437 | } |
---|
| 438 | |
---|
| 439 | // checking hardware parameters |
---|
[607] | 440 | assert( (XMAX <= 16) and |
---|
| 441 | "The XMAX parameter cannot be larger than 16" ); |
---|
[450] | 442 | |
---|
[607] | 443 | assert( (YMAX <= 16) and |
---|
| 444 | "The YMAX parameter cannot be larger than 16" ); |
---|
[450] | 445 | |
---|
[959] | 446 | assert( (NB_PROCS_MAX <= 8) and |
---|
| 447 | "NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
[450] | 448 | |
---|
[959] | 449 | assert( (XCU_NB_HWI > NB_PROCS_MAX) and |
---|
| 450 | "XCU_NB_HWI must be larger than NB_PROCS_MAX" ); |
---|
| 451 | |
---|
| 452 | assert( (XCU_NB_PTI >= NB_PROCS_MAX) and |
---|
| 453 | "XCU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); |
---|
| 454 | |
---|
| 455 | assert( (XCU_NB_WTI >= 4*NB_PROCS_MAX) and |
---|
| 456 | "XCU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
| 457 | |
---|
| 458 | assert( (XCU_NB_OUT >= 4*NB_PROCS_MAX) and |
---|
| 459 | "XCU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
| 460 | |
---|
| 461 | assert( (NB_DMA_CHANNELS >= NB_PROCS_MAX) and |
---|
[914] | 462 | "The NB_DMA_CHANNELS parameter cannot be larger than 8" ); |
---|
[450] | 463 | |
---|
[874] | 464 | assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and |
---|
| 465 | "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); |
---|
[450] | 466 | |
---|
[914] | 467 | assert( (NB_NIC_CHANNELS <= 2) and |
---|
| 468 | "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); |
---|
[450] | 469 | |
---|
[914] | 470 | assert( (NB_CMA_CHANNELS <= 4) and |
---|
| 471 | "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); |
---|
| 472 | |
---|
[966] | 473 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
---|
| 474 | "You must have X_WIDTH == Y_WIDTH == 4"); |
---|
| 475 | |
---|
[707] | 476 | std::cout << std::endl << std::dec |
---|
| 477 | << " - XMAX = " << XMAX << std::endl |
---|
| 478 | << " - YMAX = " << YMAX << std::endl |
---|
[802] | 479 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
[914] | 480 | << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl |
---|
[710] | 481 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
[707] | 482 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
[914] | 483 | << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl |
---|
[707] | 484 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 485 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 486 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 487 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[914] | 488 | << " - NCYCLES = " << ncycles << std::endl |
---|
[966] | 489 | << " - SOFT_FILENAME = " << soft_name << std::endl |
---|
| 490 | << " - DISK_IMAGENAME = " << disk_name << std::endl |
---|
| 491 | << " - OPENMP THREADS = " << threads << std::endl |
---|
[707] | 492 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
| 493 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
| 494 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
[450] | 495 | |
---|
| 496 | std::cout << std::endl; |
---|
| 497 | |
---|
[762] | 498 | #if USING_OPENMP |
---|
[450] | 499 | omp_set_dynamic(false); |
---|
[966] | 500 | omp_set_num_threads(threads); |
---|
[450] | 501 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 502 | #endif |
---|
| 503 | |
---|
| 504 | // Define VciParams objects |
---|
| 505 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 506 | vci_plen_width, |
---|
| 507 | vci_address_width, |
---|
| 508 | vci_rerror_width, |
---|
| 509 | vci_clen_width, |
---|
| 510 | vci_rflag_width, |
---|
| 511 | vci_srcid_width, |
---|
| 512 | vci_pktid_width, |
---|
| 513 | vci_trdid_width, |
---|
| 514 | vci_wrplen_width> vci_param_int; |
---|
| 515 | |
---|
| 516 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 517 | vci_plen_width, |
---|
| 518 | vci_address_width, |
---|
[718] | 519 | vci_rerror_width, |
---|
[450] | 520 | vci_clen_width, |
---|
| 521 | vci_rflag_width, |
---|
| 522 | vci_srcid_width, |
---|
| 523 | vci_pktid_width, |
---|
| 524 | vci_trdid_width, |
---|
| 525 | vci_wrplen_width> vci_param_ext; |
---|
| 526 | |
---|
| 527 | ///////////////////////////////////////////////////////////////////// |
---|
| 528 | // INT network mapping table |
---|
| 529 | // - two levels address decoding for commands |
---|
| 530 | // - two levels srcid decoding for responses |
---|
| 531 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 532 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 533 | ///////////////////////////////////////////////////////////////////// |
---|
[718] | 534 | MappingTable maptab_int( vci_address_width, |
---|
| 535 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
| 536 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 537 | 0x00FF000000); |
---|
| 538 | |
---|
| 539 | for (size_t x = 0; x < XMAX; x++) |
---|
| 540 | { |
---|
| 541 | for (size_t y = 0; y < YMAX; y++) |
---|
| 542 | { |
---|
[718] | 543 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 544 | << (vci_address_width-x_width-y_width); |
---|
[550] | 545 | bool config = true; |
---|
| 546 | bool cacheable = true; |
---|
[450] | 547 | |
---|
| 548 | // the four following segments are defined in all clusters |
---|
| 549 | |
---|
| 550 | std::ostringstream smemc_conf; |
---|
| 551 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
[718] | 552 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
| 553 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[450] | 554 | |
---|
| 555 | std::ostringstream smemc_xram; |
---|
| 556 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
[718] | 557 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
| 558 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
---|
[450] | 559 | |
---|
| 560 | std::ostringstream sxicu; |
---|
| 561 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
[718] | 562 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
| 563 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
---|
[450] | 564 | |
---|
| 565 | std::ostringstream smdma; |
---|
| 566 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
[718] | 567 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
| 568 | IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); |
---|
[450] | 569 | |
---|
| 570 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 571 | |
---|
[718] | 572 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
[450] | 573 | { |
---|
| 574 | std::ostringstream siobx; |
---|
| 575 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
[718] | 576 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[550] | 577 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[450] | 578 | |
---|
| 579 | std::ostringstream stty; |
---|
| 580 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
[718] | 581 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
[550] | 582 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 583 | |
---|
| 584 | std::ostringstream sfbf; |
---|
| 585 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
[718] | 586 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[550] | 587 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 588 | |
---|
[965] | 589 | std::ostringstream sdsk; |
---|
| 590 | sdsk << "int_seg_disk_" << x << "_" << y; |
---|
| 591 | maptab_int.add(Segment(sdsk.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[550] | 592 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 593 | |
---|
| 594 | std::ostringstream snic; |
---|
| 595 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
[718] | 596 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[550] | 597 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 598 | |
---|
| 599 | std::ostringstream srom; |
---|
| 600 | srom << "int_seg_brom_" << x << "_" << y; |
---|
[718] | 601 | maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[550] | 602 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); |
---|
[450] | 603 | |
---|
| 604 | std::ostringstream sdma; |
---|
| 605 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
[718] | 606 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
[550] | 607 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[707] | 608 | |
---|
| 609 | std::ostringstream spic; |
---|
| 610 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
[718] | 611 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[707] | 612 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 613 | } |
---|
| 614 | |
---|
| 615 | // This define the mapping between the SRCIDs |
---|
| 616 | // and the port index on the local interconnect. |
---|
| 617 | |
---|
[718] | 618 | maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), |
---|
[550] | 619 | IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); |
---|
[450] | 620 | |
---|
[550] | 621 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
---|
| 622 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
[450] | 623 | |
---|
[707] | 624 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
---|
| 625 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
| 626 | |
---|
[802] | 627 | for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) |
---|
[718] | 628 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
---|
[550] | 629 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
---|
[450] | 630 | } |
---|
| 631 | } |
---|
| 632 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 633 | |
---|
| 634 | ///////////////////////////////////////////////////////////////////////// |
---|
[718] | 635 | // RAM network mapping table |
---|
[450] | 636 | // - two levels address decoding for commands |
---|
| 637 | // - two levels srcid decoding for responses |
---|
[718] | 638 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
[450] | 639 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 640 | // - 1 local target (XRAM) per cluster |
---|
| 641 | //////////////////////////////////////////////////////////////////////// |
---|
| 642 | MappingTable maptab_ram( vci_address_width, |
---|
[718] | 643 | IntTab(x_width+y_width, 0), |
---|
| 644 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 645 | 0x00FF000000); |
---|
| 646 | |
---|
| 647 | for (size_t x = 0; x < XMAX; x++) |
---|
| 648 | { |
---|
| 649 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 650 | { |
---|
| 651 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 652 | << (vci_address_width-x_width-y_width); |
---|
| 653 | |
---|
| 654 | std::ostringstream sxram; |
---|
| 655 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
[718] | 656 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
| 657 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
[450] | 658 | } |
---|
| 659 | } |
---|
| 660 | |
---|
[550] | 661 | // This define the mapping between the initiators SRCID |
---|
| 662 | // and the port index on the RAM local interconnect. |
---|
[718] | 663 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
[450] | 664 | |
---|
[718] | 665 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
[550] | 666 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
[450] | 667 | |
---|
[718] | 668 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
[550] | 669 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
[450] | 670 | |
---|
[965] | 671 | maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), |
---|
[550] | 672 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
[450] | 673 | |
---|
[965] | 674 | maptab_ram.srcid_map( IntTab( cluster_iob1, DISK_LOCAL_SRCID ), |
---|
[550] | 675 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 676 | |
---|
[718] | 677 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 678 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 679 | |
---|
| 680 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 681 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 682 | |
---|
| 683 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 684 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 685 | |
---|
| 686 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
[550] | 687 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 688 | |
---|
[450] | 689 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 690 | |
---|
| 691 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 692 | // IOX network mapping table |
---|
| 693 | // - two levels address decoding for commands (9, 7) bits |
---|
[450] | 694 | // - two levels srcid decoding for responses |
---|
[965] | 695 | // - 5 initiators (IOB0, IOB1, DISK, CDMA, IOPI) |
---|
| 696 | // - 9 targets (IOB0, IOB1, DISK, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
[718] | 697 | // |
---|
| 698 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 699 | // IOB0 or IOB1. |
---|
[450] | 700 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 701 | MappingTable maptab_iox( |
---|
| 702 | vci_address_width, |
---|
| 703 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
---|
| 704 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
---|
| 705 | 0x00FF000000); |
---|
[450] | 706 | |
---|
[707] | 707 | // External peripherals segments |
---|
[718] | 708 | // When there is more than one cluster, external peripherals can be accessed |
---|
[707] | 709 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
[718] | 710 | |
---|
| 711 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 712 | << (vci_address_width - x_width - y_width); |
---|
| 713 | |
---|
| 714 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
| 715 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 716 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 717 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 718 | maptab_iox.add(Segment("iox_seg_disk_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 719 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 720 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 721 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 722 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
| 723 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 724 | maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, |
---|
| 725 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 726 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 727 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
| 728 | |
---|
[707] | 729 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 730 | { |
---|
[718] | 731 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 732 | << (vci_address_width - x_width - y_width); |
---|
| 733 | |
---|
| 734 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
| 735 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 736 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 737 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 738 | maptab_iox.add(Segment("iox_seg_disk_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 739 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 740 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 741 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 742 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
| 743 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 744 | maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, |
---|
| 745 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 746 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 747 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[707] | 748 | } |
---|
[450] | 749 | |
---|
[718] | 750 | // If there is more than one cluster, external peripherals |
---|
[707] | 751 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 752 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
[718] | 753 | // and the choice depends on address bit A[32]. |
---|
[450] | 754 | for (size_t x = 0; x < XMAX; x++) |
---|
| 755 | { |
---|
| 756 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 757 | { |
---|
| 758 | const bool wti = true; |
---|
| 759 | const bool cacheable = true; |
---|
[450] | 760 | |
---|
[718] | 761 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 762 | << (vci_address_width-x_width-y_width); |
---|
| 763 | |
---|
| 764 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
| 765 | |
---|
| 766 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
[450] | 767 | { |
---|
[718] | 768 | std::ostringstream sxcu0; |
---|
| 769 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
| 770 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 771 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 772 | |
---|
| 773 | std::ostringstream siob0; |
---|
| 774 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
| 775 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
| 776 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
[707] | 777 | } |
---|
[718] | 778 | else // USE IOB1 |
---|
[707] | 779 | { |
---|
[718] | 780 | std::ostringstream sxcu1; |
---|
| 781 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
| 782 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 783 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 784 | |
---|
| 785 | std::ostringstream siob1; |
---|
| 786 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
| 787 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
| 788 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
[450] | 789 | } |
---|
| 790 | } |
---|
| 791 | } |
---|
| 792 | |
---|
[707] | 793 | // This define the mapping between the external initiators (SRCID) |
---|
[450] | 794 | // and the port index on the IOX local interconnect. |
---|
[550] | 795 | |
---|
[718] | 796 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
| 797 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
[965] | 798 | maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , |
---|
| 799 | IntTab( 0, IOX_DISK_INI_ID ) ); |
---|
[718] | 800 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 801 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
| 802 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 803 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 804 | |
---|
[707] | 805 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 806 | { |
---|
[718] | 807 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 808 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
[707] | 809 | } |
---|
[550] | 810 | |
---|
[450] | 811 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 812 | |
---|
| 813 | //////////////////// |
---|
| 814 | // Signals |
---|
| 815 | /////////////////// |
---|
| 816 | |
---|
[550] | 817 | sc_clock signal_clk("clk"); |
---|
| 818 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 819 | |
---|
[584] | 820 | sc_signal<bool> signal_irq_false; |
---|
[965] | 821 | sc_signal<bool> signal_irq_disk; |
---|
[874] | 822 | sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; |
---|
[550] | 823 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 824 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
[707] | 825 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
[450] | 826 | |
---|
| 827 | // VCI signals for IOX network |
---|
[550] | 828 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 829 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
[965] | 830 | VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); |
---|
[550] | 831 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
[707] | 832 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
[450] | 833 | |
---|
[550] | 834 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 835 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 836 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 837 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 838 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 839 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
---|
[965] | 840 | VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); |
---|
[550] | 841 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
[953] | 842 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
---|
[450] | 843 | |
---|
[718] | 844 | // Horizontal inter-clusters INT network DSPIN |
---|
[450] | 845 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[468] | 846 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); |
---|
[450] | 847 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[468] | 848 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); |
---|
[450] | 849 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
| 850 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); |
---|
| 851 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
| 852 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); |
---|
| 853 | |
---|
| 854 | // Vertical inter-clusters INT network DSPIN |
---|
| 855 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[468] | 856 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); |
---|
[450] | 857 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[468] | 858 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); |
---|
[450] | 859 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
| 860 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); |
---|
| 861 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
| 862 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); |
---|
| 863 | |
---|
[718] | 864 | // Mesh boundaries INT network DSPIN |
---|
[450] | 865 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[468] | 866 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); |
---|
[450] | 867 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[468] | 868 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); |
---|
[450] | 869 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[468] | 870 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); |
---|
[450] | 871 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[468] | 872 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); |
---|
[450] | 873 | |
---|
| 874 | |
---|
[718] | 875 | // Horizontal inter-clusters RAM network DSPIN |
---|
[450] | 876 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
| 877 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
| 878 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
| 879 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
| 880 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
| 881 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
| 882 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
| 883 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
| 884 | |
---|
| 885 | // Vertical inter-clusters RAM network DSPIN |
---|
| 886 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
| 887 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
| 888 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
| 889 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
| 890 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
| 891 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
| 892 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
| 893 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
| 894 | |
---|
[718] | 895 | // Mesh boundaries RAM network DSPIN |
---|
[450] | 896 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
| 897 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
| 898 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
| 899 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
| 900 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
| 901 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
| 902 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
| 903 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
| 904 | |
---|
[965] | 905 | //////////////////////////// |
---|
| 906 | // Loader |
---|
| 907 | //////////////////////////// |
---|
[450] | 908 | |
---|
| 909 | #if USE_ALMOS |
---|
[965] | 910 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
[450] | 911 | almos_archinfo_pathname, |
---|
| 912 | almos_kernel_pathname); |
---|
| 913 | #else |
---|
[965] | 914 | soclib::common::Loader loader(soft_name); |
---|
[450] | 915 | #endif |
---|
| 916 | |
---|
[965] | 917 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 918 | proc_iss::set_loader(loader); |
---|
[450] | 919 | |
---|
[965] | 920 | //////////////////////////////////////// |
---|
| 921 | // Instanciated Hardware Components |
---|
| 922 | //////////////////////////////////////// |
---|
[450] | 923 | |
---|
[965] | 924 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
[450] | 925 | |
---|
[965] | 926 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
| 927 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; |
---|
[718] | 928 | |
---|
[965] | 929 | // IOX network |
---|
| 930 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 931 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 932 | maptab_iox, |
---|
| 933 | nb_iox_targets, |
---|
| 934 | nb_iox_initiators ); |
---|
| 935 | // boot ROM |
---|
| 936 | VciSimpleRom<vci_param_ext>* brom; |
---|
| 937 | brom = new VciSimpleRom<vci_param_ext>( "brom", |
---|
| 938 | IntTab(0, IOX_BROM_TGT_ID), |
---|
| 939 | maptab_iox, |
---|
| 940 | loader ); |
---|
| 941 | // Network Controller |
---|
| 942 | VciMultiNic<vci_param_ext>* mnic; |
---|
| 943 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
| 944 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
[550] | 945 | maptab_iox, |
---|
[965] | 946 | NB_NIC_CHANNELS, |
---|
| 947 | 0, // mac_4 address |
---|
| 948 | 0, // mac_2 address |
---|
| 949 | 1 ); // NIC_MODE_SYNTHESIS |
---|
[450] | 950 | |
---|
[965] | 951 | // Frame Buffer |
---|
| 952 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 953 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 954 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 955 | maptab_iox, |
---|
| 956 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 957 | |
---|
[965] | 958 | // Disk |
---|
| 959 | std::vector<std::string> filenames; |
---|
| 960 | filenames.push_back(disk_name); // one single disk |
---|
| 961 | |
---|
| 962 | #if ( USE_IOC_HBA ) |
---|
[966] | 963 | |
---|
[965] | 964 | VciMultiAhci<vci_param_ext>* disk; |
---|
| 965 | disk = new VciMultiAhci<vci_param_ext>( "disk", |
---|
| 966 | maptab_iox, |
---|
| 967 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 968 | IntTab(0, IOX_DISK_TGT_ID), |
---|
| 969 | filenames, |
---|
| 970 | 512, // block size |
---|
| 971 | 64, // burst size (bytes) |
---|
| 972 | 0 ); // disk latency |
---|
[966] | 973 | #elif ( USE_IOC_BDV or USE_IOC_SDC ) |
---|
| 974 | |
---|
[965] | 975 | VciBlockDeviceTsar<vci_param_ext>* disk; |
---|
| 976 | disk = new VciBlockDeviceTsar<vci_param_ext>( "disk", |
---|
[550] | 977 | maptab_iox, |
---|
[965] | 978 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 979 | IntTab(0, IOX_DISK_TGT_ID), |
---|
[550] | 980 | disk_name, |
---|
[714] | 981 | 512, // block size |
---|
[718] | 982 | 64, // burst size (bytes) |
---|
| 983 | 0 ); // disk latency |
---|
[965] | 984 | #endif |
---|
[450] | 985 | |
---|
[965] | 986 | // Chained Buffer DMA controller |
---|
| 987 | VciChbufDma<vci_param_ext>* cdma; |
---|
| 988 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
| 989 | maptab_iox, |
---|
| 990 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 991 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 992 | 64, // burst size (bytes) |
---|
| 993 | NB_CMA_CHANNELS ); |
---|
| 994 | // Multi-TTY controller |
---|
| 995 | std::vector<std::string> vect_names; |
---|
| 996 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
| 997 | { |
---|
| 998 | std::ostringstream term_name; |
---|
| 999 | term_name << "term" << tid; |
---|
| 1000 | |
---|
[707] | 1001 | vect_names.push_back(term_name.str().c_str()); |
---|
| 1002 | } |
---|
| 1003 | VciMultiTty<vci_param_ext>* mtty; |
---|
| 1004 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
| 1005 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
[718] | 1006 | maptab_iox, |
---|
[707] | 1007 | vect_names); |
---|
| 1008 | |
---|
[965] | 1009 | // IOPIC |
---|
| 1010 | VciIopic<vci_param_ext>* iopi; |
---|
| 1011 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 1012 | maptab_iox, |
---|
| 1013 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 1014 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 1015 | 32 ); // number of input HWI |
---|
| 1016 | // Clusters |
---|
| 1017 | TsarIobCluster<vci_param_int, |
---|
| 1018 | vci_param_ext, |
---|
| 1019 | dspin_int_cmd_width, |
---|
| 1020 | dspin_int_rsp_width, |
---|
| 1021 | dspin_ram_cmd_width, |
---|
| 1022 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
[450] | 1023 | |
---|
[762] | 1024 | #if USING_OPENMP |
---|
[450] | 1025 | #pragma omp parallel |
---|
| 1026 | { |
---|
| 1027 | #pragma omp for |
---|
| 1028 | #endif |
---|
| 1029 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
| 1030 | { |
---|
| 1031 | size_t x = i / YMAX; |
---|
| 1032 | size_t y = i % YMAX; |
---|
| 1033 | |
---|
[762] | 1034 | #if USING_OPENMP |
---|
[450] | 1035 | #pragma omp critical |
---|
| 1036 | { |
---|
| 1037 | #endif |
---|
| 1038 | std::cout << std::endl; |
---|
| 1039 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1040 | std::cout << std::endl; |
---|
| 1041 | |
---|
[718] | 1042 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
---|
| 1043 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
---|
| 1044 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1045 | |
---|
| 1046 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1047 | IOX_IOB0_INI_ID : |
---|
| 1048 | IOX_IOB1_INI_ID ; |
---|
| 1049 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1050 | IOX_IOB0_TGT_ID : |
---|
| 1051 | IOX_IOB1_TGT_ID ; |
---|
| 1052 | |
---|
[450] | 1053 | std::ostringstream sc; |
---|
| 1054 | sc << "cluster_" << x << "_" << y; |
---|
| 1055 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1056 | vci_param_ext, |
---|
| 1057 | dspin_int_cmd_width, |
---|
| 1058 | dspin_int_rsp_width, |
---|
| 1059 | dspin_ram_cmd_width, |
---|
| 1060 | dspin_ram_rsp_width> |
---|
| 1061 | ( |
---|
| 1062 | sc.str().c_str(), |
---|
| 1063 | NB_PROCS_MAX, |
---|
| 1064 | NB_DMA_CHANNELS, |
---|
| 1065 | x, |
---|
| 1066 | y, |
---|
| 1067 | XMAX, |
---|
| 1068 | YMAX, |
---|
| 1069 | |
---|
| 1070 | maptab_int, |
---|
| 1071 | maptab_ram, |
---|
| 1072 | maptab_iox, |
---|
| 1073 | |
---|
| 1074 | x_width, |
---|
| 1075 | y_width, |
---|
| 1076 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
[802] | 1077 | p_width, |
---|
[450] | 1078 | |
---|
| 1079 | INT_MEMC_TGT_ID, |
---|
| 1080 | INT_XICU_TGT_ID, |
---|
| 1081 | INT_MDMA_TGT_ID, |
---|
| 1082 | INT_IOBX_TGT_ID, |
---|
| 1083 | |
---|
| 1084 | INT_PROC_INI_ID, |
---|
| 1085 | INT_MDMA_INI_ID, |
---|
| 1086 | INT_IOBX_INI_ID, |
---|
| 1087 | |
---|
| 1088 | RAM_XRAM_TGT_ID, |
---|
| 1089 | |
---|
| 1090 | RAM_MEMC_INI_ID, |
---|
[550] | 1091 | RAM_IOBX_INI_ID, |
---|
[450] | 1092 | |
---|
[718] | 1093 | is_io_cluster, |
---|
| 1094 | iox_iob_tgt_id, |
---|
| 1095 | iox_iob_ini_id, |
---|
| 1096 | |
---|
[450] | 1097 | MEMC_WAYS, |
---|
| 1098 | MEMC_SETS, |
---|
| 1099 | L1_IWAYS, |
---|
| 1100 | L1_ISETS, |
---|
| 1101 | L1_DWAYS, |
---|
| 1102 | L1_DSETS, |
---|
| 1103 | XRAM_LATENCY, |
---|
[959] | 1104 | XCU_NB_HWI, |
---|
| 1105 | XCU_NB_PTI, |
---|
| 1106 | XCU_NB_WTI, |
---|
| 1107 | XCU_NB_OUT, |
---|
[450] | 1108 | |
---|
| 1109 | loader, |
---|
| 1110 | |
---|
| 1111 | frozen_cycles, |
---|
| 1112 | debug_from, |
---|
| 1113 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
| 1114 | debug_ok and (cluster(x,y) == debug_proc_id), |
---|
| 1115 | debug_ok and debug_iob |
---|
| 1116 | ); |
---|
| 1117 | |
---|
[762] | 1118 | #if USING_OPENMP |
---|
[450] | 1119 | } // end critical |
---|
| 1120 | #endif |
---|
| 1121 | } // end for |
---|
[762] | 1122 | #if USING_OPENMP |
---|
[450] | 1123 | } |
---|
| 1124 | #endif |
---|
| 1125 | |
---|
| 1126 | std::cout << std::endl; |
---|
| 1127 | |
---|
| 1128 | /////////////////////////////////////////////////////////////////////////////// |
---|
[718] | 1129 | // Net-list |
---|
[450] | 1130 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1131 | |
---|
| 1132 | // IOX network connexion |
---|
[584] | 1133 | iox_network->p_clk (signal_clk); |
---|
| 1134 | iox_network->p_resetn (signal_resetn); |
---|
| 1135 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
[965] | 1136 | iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); |
---|
[584] | 1137 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
[707] | 1138 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
| 1139 | |
---|
[584] | 1140 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1141 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1142 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1143 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1144 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
---|
[965] | 1145 | iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); |
---|
[584] | 1146 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
[707] | 1147 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[450] | 1148 | |
---|
[718] | 1149 | if (cluster_iob0 != cluster_iob1) |
---|
| 1150 | { |
---|
| 1151 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1152 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1153 | } |
---|
| 1154 | |
---|
[965] | 1155 | // DISK connexion |
---|
| 1156 | disk->p_clk (signal_clk); |
---|
| 1157 | disk->p_resetn (signal_resetn); |
---|
| 1158 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1159 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
| 1160 | #if ( USE_IOC_HBA ) |
---|
| 1161 | disk->p_channel_irq[0] (signal_irq_disk); |
---|
| 1162 | #else |
---|
| 1163 | disk->p_irq (signal_irq_disk); |
---|
| 1164 | #endif |
---|
[450] | 1165 | |
---|
[965] | 1166 | std::cout << " - DISK connected" << std::endl; |
---|
[450] | 1167 | |
---|
| 1168 | // FBUF connexion |
---|
[550] | 1169 | fbuf->p_clk (signal_clk); |
---|
| 1170 | fbuf->p_resetn (signal_resetn); |
---|
| 1171 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 1172 | |
---|
| 1173 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1174 | |
---|
| 1175 | // MNIC connexion |
---|
[550] | 1176 | mnic->p_clk (signal_clk); |
---|
| 1177 | mnic->p_resetn (signal_resetn); |
---|
| 1178 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
[450] | 1179 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1180 | { |
---|
[550] | 1181 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1182 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
[450] | 1183 | } |
---|
| 1184 | |
---|
| 1185 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1186 | |
---|
| 1187 | // BROM connexion |
---|
[550] | 1188 | brom->p_clk (signal_clk); |
---|
| 1189 | brom->p_resetn (signal_resetn); |
---|
| 1190 | brom->p_vci (signal_vci_tgt_brom); |
---|
[450] | 1191 | |
---|
| 1192 | std::cout << " - BROM connected" << std::endl; |
---|
| 1193 | |
---|
| 1194 | // MTTY connexion |
---|
[550] | 1195 | mtty->p_clk (signal_clk); |
---|
| 1196 | mtty->p_resetn (signal_resetn); |
---|
| 1197 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
[874] | 1198 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
| 1199 | { |
---|
| 1200 | mtty->p_irq[i] (signal_irq_mtty_rx[i]); |
---|
| 1201 | } |
---|
[450] | 1202 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1203 | |
---|
| 1204 | // CDMA connexion |
---|
[718] | 1205 | cdma->p_clk (signal_clk); |
---|
| 1206 | cdma->p_resetn (signal_resetn); |
---|
| 1207 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1208 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
[914] | 1209 | for ( size_t i=0 ; i<(NB_CMA_CHANNELS) ; i++) |
---|
[450] | 1210 | { |
---|
[718] | 1211 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
[450] | 1212 | } |
---|
| 1213 | |
---|
| 1214 | std::cout << " - CDMA connected" << std::endl; |
---|
| 1215 | |
---|
[707] | 1216 | // IOPI connexion |
---|
[718] | 1217 | iopi->p_clk (signal_clk); |
---|
| 1218 | iopi->p_resetn (signal_resetn); |
---|
| 1219 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1220 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
[707] | 1221 | for ( size_t i=0 ; i<32 ; i++) |
---|
[450] | 1222 | { |
---|
[707] | 1223 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1224 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1225 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 1226 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1227 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 1228 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
[965] | 1229 | else if(i < 9) iopi->p_hwi[i] (signal_irq_disk); |
---|
[874] | 1230 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1231 | else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
[707] | 1232 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1233 | } |
---|
[584] | 1234 | |
---|
[707] | 1235 | std::cout << " - IOPIC connected" << std::endl; |
---|
[584] | 1236 | |
---|
[718] | 1237 | |
---|
[707] | 1238 | // IOB0 cluster connexion to IOX network |
---|
[718] | 1239 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1240 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[584] | 1241 | |
---|
[718] | 1242 | // IOB1 cluster connexion to IOX network |
---|
[707] | 1243 | // (only when there is more than 1 cluster) |
---|
| 1244 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1245 | { |
---|
| 1246 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1247 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[450] | 1248 | } |
---|
| 1249 | |
---|
| 1250 | // All clusters Clock & RESET connexions |
---|
| 1251 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
| 1252 | { |
---|
| 1253 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1254 | { |
---|
| 1255 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1256 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1257 | } |
---|
| 1258 | } |
---|
| 1259 | |
---|
| 1260 | // Inter Clusters horizontal connections |
---|
| 1261 | if (XMAX > 1) |
---|
| 1262 | { |
---|
| 1263 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
| 1264 | { |
---|
| 1265 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1266 | { |
---|
[468] | 1267 | for (size_t k = 0; k < 3; k++) |
---|
| 1268 | { |
---|
| 1269 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1270 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1271 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1272 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1273 | } |
---|
| 1274 | |
---|
[450] | 1275 | for (size_t k = 0; k < 2; k++) |
---|
| 1276 | { |
---|
[468] | 1277 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1278 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1279 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1280 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
[450] | 1281 | } |
---|
| 1282 | |
---|
| 1283 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1284 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1285 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1286 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1287 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1288 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1289 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1290 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1291 | } |
---|
| 1292 | } |
---|
| 1293 | } |
---|
| 1294 | |
---|
[718] | 1295 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
[450] | 1296 | |
---|
| 1297 | // Inter Clusters vertical connections |
---|
[718] | 1298 | if (YMAX > 1) |
---|
[450] | 1299 | { |
---|
| 1300 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
| 1301 | { |
---|
| 1302 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1303 | { |
---|
[468] | 1304 | for (size_t k = 0; k < 3; k++) |
---|
| 1305 | { |
---|
| 1306 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1307 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1308 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1309 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1310 | } |
---|
| 1311 | |
---|
[450] | 1312 | for (size_t k = 0; k < 2; k++) |
---|
| 1313 | { |
---|
[468] | 1314 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1315 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1316 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1317 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
[450] | 1318 | } |
---|
| 1319 | |
---|
| 1320 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1321 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1322 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1323 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1324 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1325 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1326 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1327 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1328 | } |
---|
| 1329 | } |
---|
| 1330 | } |
---|
| 1331 | |
---|
| 1332 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1333 | |
---|
| 1334 | // East & West boundary cluster connections |
---|
| 1335 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1336 | { |
---|
[468] | 1337 | for (size_t k = 0; k < 3; k++) |
---|
| 1338 | { |
---|
| 1339 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1340 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
| 1341 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); |
---|
| 1342 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); |
---|
| 1343 | } |
---|
| 1344 | |
---|
[450] | 1345 | for (size_t k = 0; k < 2; k++) |
---|
| 1346 | { |
---|
[468] | 1347 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1348 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
| 1349 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); |
---|
| 1350 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); |
---|
[450] | 1351 | } |
---|
| 1352 | |
---|
[718] | 1353 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1354 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1355 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1356 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[450] | 1357 | |
---|
[718] | 1358 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
| 1359 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
| 1360 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
| 1361 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
[450] | 1362 | } |
---|
| 1363 | |
---|
| 1364 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1365 | |
---|
| 1366 | // North & South boundary clusters connections |
---|
| 1367 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1368 | { |
---|
[468] | 1369 | for (size_t k = 0; k < 3; k++) |
---|
| 1370 | { |
---|
| 1371 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1372 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
| 1373 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); |
---|
| 1374 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); |
---|
| 1375 | } |
---|
| 1376 | |
---|
[450] | 1377 | for (size_t k = 0; k < 2; k++) |
---|
| 1378 | { |
---|
[468] | 1379 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1380 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
| 1381 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); |
---|
| 1382 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); |
---|
[450] | 1383 | } |
---|
| 1384 | |
---|
[718] | 1385 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1386 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1387 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1388 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[450] | 1389 | |
---|
[718] | 1390 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
| 1391 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
| 1392 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
| 1393 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
[450] | 1394 | } |
---|
| 1395 | |
---|
[550] | 1396 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
[450] | 1397 | |
---|
| 1398 | //////////////////////////////////////////////////////// |
---|
| 1399 | // Simulation |
---|
| 1400 | /////////////////////////////////////////////////////// |
---|
| 1401 | |
---|
| 1402 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
[584] | 1403 | |
---|
[450] | 1404 | signal_resetn = false; |
---|
[584] | 1405 | signal_irq_false = false; |
---|
| 1406 | |
---|
[450] | 1407 | // network boundaries signals |
---|
| 1408 | for (size_t x = 0; x < XMAX ; x++) |
---|
| 1409 | { |
---|
| 1410 | for (size_t y = 0; y < YMAX ; y++) |
---|
| 1411 | { |
---|
| 1412 | for (size_t a = 0; a < 4; a++) |
---|
| 1413 | { |
---|
[468] | 1414 | for (size_t k = 0; k < 3; k++) |
---|
| 1415 | { |
---|
| 1416 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1417 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
| 1418 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
| 1419 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
| 1420 | } |
---|
| 1421 | |
---|
[450] | 1422 | for (size_t k = 0; k < 2; k++) |
---|
| 1423 | { |
---|
[468] | 1424 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1425 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
| 1426 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
| 1427 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
[450] | 1428 | } |
---|
| 1429 | |
---|
| 1430 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1431 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
| 1432 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
| 1433 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
| 1434 | |
---|
| 1435 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1436 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
| 1437 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
| 1438 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
| 1439 | } |
---|
| 1440 | } |
---|
| 1441 | } |
---|
| 1442 | |
---|
[550] | 1443 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1444 | signal_resetn = true; |
---|
[450] | 1445 | |
---|
[707] | 1446 | |
---|
| 1447 | // simulation loop |
---|
[693] | 1448 | struct timeval t1,t2; |
---|
| 1449 | gettimeofday(&t1, NULL); |
---|
[707] | 1450 | |
---|
[762] | 1451 | |
---|
| 1452 | for ( size_t n = 0; n < ncycles ; n += simul_period ) |
---|
[550] | 1453 | { |
---|
[693] | 1454 | // stats display |
---|
[714] | 1455 | if( (n % 1000000) == 0) |
---|
[693] | 1456 | { |
---|
| 1457 | gettimeofday(&t2, NULL); |
---|
| 1458 | |
---|
| 1459 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
| 1460 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1461 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
| 1462 | (uint64_t) t2.tv_usec / 1000; |
---|
[817] | 1463 | std::cerr << "### cycle = " << std::dec << n |
---|
[718] | 1464 | << " / frequency = " |
---|
| 1465 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
---|
[693] | 1466 | << std::endl; |
---|
| 1467 | |
---|
| 1468 | gettimeofday(&t1, NULL); |
---|
| 1469 | } |
---|
| 1470 | |
---|
[607] | 1471 | // Monitor a specific address for one L1 cache |
---|
[959] | 1472 | // clusters[0][0]->proc[0]->cache_monitor(0x800080ULL); |
---|
[450] | 1473 | |
---|
[607] | 1474 | // Monitor a specific address for one L2 cache |
---|
[959] | 1475 | // clusters[0][0]->memc->cache_monitor( 0x800080ULL, false ); // full line |
---|
[607] | 1476 | |
---|
| 1477 | // Monitor a specific address for one XRAM |
---|
[943] | 1478 | // clusters[0][0]->xram->start_monitor( 0x600800ULL , 64); |
---|
[607] | 1479 | |
---|
[764] | 1480 | if ( debug_ok and (n > debug_from) ) |
---|
[450] | 1481 | { |
---|
[550] | 1482 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1483 | std::cout << " ************************************************" << std::endl; |
---|
[450] | 1484 | |
---|
[718] | 1485 | // trace proc[debug_proc_id] |
---|
[607] | 1486 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
[550] | 1487 | { |
---|
[802] | 1488 | size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; |
---|
| 1489 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
[607] | 1490 | size_t x = cluster_xy >> 4; |
---|
| 1491 | size_t y = cluster_xy & 0xF; |
---|
[764] | 1492 | |
---|
| 1493 | clusters[x][y]->proc[l]->print_trace(0x1); |
---|
[550] | 1494 | std::ostringstream proc_signame; |
---|
| 1495 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1496 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
[450] | 1497 | |
---|
[959] | 1498 | clusters[x][y]->xicu->print_trace(1); |
---|
| 1499 | std::ostringstream xicu_signame; |
---|
| 1500 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1501 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
[584] | 1502 | |
---|
[965] | 1503 | // clusters[x][y]->mdma->print_trace(); |
---|
| 1504 | // std::ostringstream mdma_tgt_signame; |
---|
| 1505 | // mdma_tgt_signame << "[SIG]MDMA_TGT_" << x << "_" << y; |
---|
| 1506 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_tgt_signame.str()); |
---|
| 1507 | // std::ostringstream mdma_ini_signame; |
---|
| 1508 | // mdma_ini_signame << "[SIG]MDMA_INI_" << x << "_" << y; |
---|
| 1509 | // clusters[x][y]->signal_int_vci_ini_mdma.print_trace(mdma_ini_signame.str()); |
---|
[714] | 1510 | |
---|
[739] | 1511 | // local interrupts in cluster(x,y) |
---|
| 1512 | if( clusters[x][y]->signal_irq_memc.read() ) |
---|
[802] | 1513 | std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y |
---|
[739] | 1514 | << " ACTIVE" << std::endl; |
---|
| 1515 | |
---|
| 1516 | for ( size_t c = 0 ; c < NB_DMA_CHANNELS ; c++ ) |
---|
| 1517 | { |
---|
| 1518 | if( clusters[x][y]->signal_irq_mdma[c].read() ) |
---|
[802] | 1519 | std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << c |
---|
[739] | 1520 | << " ACTIVE" << std::endl; |
---|
| 1521 | } |
---|
[802] | 1522 | |
---|
[739] | 1523 | for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) |
---|
| 1524 | { |
---|
| 1525 | if( clusters[x][y]->signal_proc_it[c].read() ) |
---|
[802] | 1526 | std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c |
---|
[739] | 1527 | << " ACTIVE" << std::endl; |
---|
| 1528 | } |
---|
[718] | 1529 | } |
---|
[450] | 1530 | |
---|
[718] | 1531 | // trace memc[debug_memc_id] |
---|
[607] | 1532 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
[550] | 1533 | { |
---|
[607] | 1534 | size_t x = debug_memc_id >> 4; |
---|
| 1535 | size_t y = debug_memc_id & 0xF; |
---|
[718] | 1536 | |
---|
[550] | 1537 | clusters[x][y]->memc->print_trace(0); |
---|
| 1538 | std::ostringstream smemc_tgt; |
---|
| 1539 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1540 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
| 1541 | std::ostringstream smemc_ini; |
---|
| 1542 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1543 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
[707] | 1544 | |
---|
[550] | 1545 | clusters[x][y]->xram->print_trace(); |
---|
| 1546 | std::ostringstream sxram_tgt; |
---|
| 1547 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1548 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
| 1549 | } |
---|
[450] | 1550 | |
---|
[707] | 1551 | |
---|
| 1552 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
| 1553 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
| 1554 | { |
---|
| 1555 | size_t x = debug_xram_id >> 4; |
---|
| 1556 | size_t y = debug_xram_id & 0xF; |
---|
[718] | 1557 | |
---|
[707] | 1558 | clusters[x][y]->xram->print_trace(); |
---|
| 1559 | std::ostringstream sxram_tgt; |
---|
| 1560 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1561 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
| 1562 | |
---|
| 1563 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1564 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
| 1565 | } |
---|
[718] | 1566 | |
---|
| 1567 | // trace iob, iox and external peripherals |
---|
[550] | 1568 | if ( debug_iob ) |
---|
| 1569 | { |
---|
[914] | 1570 | // clusters[0][0]->iob->print_trace(); |
---|
[718] | 1571 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
| 1572 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
| 1573 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
[730] | 1574 | // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1575 | // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[450] | 1576 | |
---|
[965] | 1577 | cdma->print_trace(); |
---|
| 1578 | signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); |
---|
| 1579 | signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); |
---|
[450] | 1580 | |
---|
[710] | 1581 | // brom->print_trace(); |
---|
[914] | 1582 | // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); |
---|
[450] | 1583 | |
---|
[550] | 1584 | // mtty->print_trace(); |
---|
[914] | 1585 | // signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); |
---|
[450] | 1586 | |
---|
[965] | 1587 | // disk->print_trace(); |
---|
| 1588 | // signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); |
---|
| 1589 | // signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); |
---|
[450] | 1590 | |
---|
[965] | 1591 | mnic->print_trace( 0x000 ); |
---|
| 1592 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
[714] | 1593 | |
---|
[550] | 1594 | // fbuf->print_trace(); |
---|
[914] | 1595 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); |
---|
[498] | 1596 | |
---|
[874] | 1597 | // iopi->print_trace(); |
---|
| 1598 | // signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
| 1599 | // signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
[965] | 1600 | |
---|
[874] | 1601 | // iox_network->print_trace(); |
---|
[450] | 1602 | |
---|
[550] | 1603 | // interrupts |
---|
[965] | 1604 | if (signal_irq_disk) std::cout << "### IRQ_DISK ACTIVE" << std::endl; |
---|
[874] | 1605 | if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; |
---|
[714] | 1606 | if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
| 1607 | if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; |
---|
| 1608 | if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
| 1609 | if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; |
---|
[550] | 1610 | } |
---|
| 1611 | } |
---|
[450] | 1612 | |
---|
[762] | 1613 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
[550] | 1614 | } |
---|
| 1615 | return EXIT_SUCCESS; |
---|
[450] | 1616 | } |
---|
| 1617 | |
---|
| 1618 | int sc_main (int argc, char *argv[]) |
---|
| 1619 | { |
---|
| 1620 | try { |
---|
| 1621 | return _main(argc, argv); |
---|
| 1622 | } catch (std::exception &e) { |
---|
| 1623 | std::cout << e.what() << std::endl; |
---|
| 1624 | } catch (...) { |
---|
| 1625 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1626 | throw; |
---|
| 1627 | } |
---|
| 1628 | return 1; |
---|
| 1629 | } |
---|
| 1630 | |
---|
| 1631 | |
---|
| 1632 | // Local Variables: |
---|
| 1633 | // tab-width: 3 |
---|
| 1634 | // c-basic-offset: 3 |
---|
| 1635 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1636 | // indent-tabs-mode: nil |
---|
| 1637 | // End: |
---|
| 1638 | |
---|
| 1639 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1640 | |
---|
| 1641 | |
---|
| 1642 | |
---|