Changeset 468 for trunk/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Jul 24, 2013, 8:47:40 AM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache
-
Property
svn:mergeinfo
set to
/branches/v5/modules/vci_mem_cache merged eligible
-
Property
svn:mergeinfo
set to
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r449 r468 54 54 #define TRT_ENTRIES 4 // Number of entries in TRT 55 55 #define UPT_ENTRIES 4 // Number of entries in UPT 56 #define IVT_ENTRIES 4 // Number of entries in IVT 56 57 #define HEAP_ENTRIES 1024 // Number of entries in HEAP 57 58 … … 122 123 CC_SEND_WRITE_IDLE, 123 124 CC_SEND_CAS_IDLE, 124 CC_SEND_CLEANUP_IDLE,125 125 CC_SEND_CONFIG_INVAL_HEADER, 126 126 CC_SEND_CONFIG_INVAL_NLINE, 127 127 CC_SEND_CONFIG_BRDCAST_HEADER, 128 128 CC_SEND_CONFIG_BRDCAST_NLINE, 129 CC_SEND_CLEANUP_ACK,130 129 CC_SEND_XRAM_RSP_BRDCAST_HEADER, 131 130 CC_SEND_XRAM_RSP_BRDCAST_NLINE, … … 163 162 CONFIG_DIR_REQ, 164 163 CONFIG_DIR_ACCESS, 165 CONFIG_DIR_ UPT_LOCK,164 CONFIG_DIR_IVT_LOCK, 166 165 CONFIG_BC_SEND, 167 166 CONFIG_BC_WAIT, … … 211 210 WRITE_MISS_XRAM_REQ, 212 211 WRITE_BC_TRT_LOCK, 213 WRITE_BC_ UPT_LOCK,212 WRITE_BC_IVT_LOCK, 214 213 WRITE_BC_DIR_INVAL, 215 214 WRITE_BC_CC_SEND, … … 274 273 CAS_UPT_NEXT, 275 274 CAS_BC_TRT_LOCK, 276 CAS_BC_ UPT_LOCK,275 CAS_BC_IVT_LOCK, 277 276 CAS_BC_DIR_INVAL, 278 277 CAS_BC_CC_SEND, … … 299 298 CLEANUP_HEAP_CLEAN, 300 299 CLEANUP_HEAP_FREE, 301 CLEANUP_ UPT_LOCK,302 CLEANUP_ UPT_DECREMENT,303 CLEANUP_ UPT_CLEAR,300 CLEANUP_IVT_LOCK, 301 CLEANUP_IVT_DECREMENT, 302 CLEANUP_IVT_CLEAR, 304 303 CLEANUP_WRITE_RSP, 305 304 CLEANUP_CONFIG_ACK, … … 332 331 enum alloc_upt_fsm_state_e 333 332 { 334 ALLOC_UPT_CONFIG,335 333 ALLOC_UPT_WRITE, 336 ALLOC_UPT_XRAM_RSP, 337 ALLOC_UPT_MULTI_ACK, 338 ALLOC_UPT_CLEANUP, 339 ALLOC_UPT_CAS 334 ALLOC_UPT_CAS, 335 ALLOC_UPT_MULTI_ACK 336 }; 337 338 /* States of the ALLOC_IVT fsm */ 339 enum alloc_ivt_fsm_state_e 340 { 341 ALLOC_IVT_WRITE, 342 ALLOC_IVT_XRAM_RSP, 343 ALLOC_IVT_CLEANUP, 344 ALLOC_IVT_CAS, 345 ALLOC_IVT_CONFIG 340 346 }; 341 347 … … 451 457 soclib::caba::VciTarget<vci_param_int> p_vci_tgt; 452 458 soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; 453 soclib::caba::DspinInput<dspin_in_width> p_dspin_in; 454 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 459 soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; 460 soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; 461 soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; 455 462 456 463 VciMemCache( … … 468 475 const size_t trt_lines=TRT_ENTRIES, 469 476 const size_t upt_lines=UPT_ENTRIES, 477 const size_t ivt_lines=IVT_ENTRIES, 470 478 const size_t debug_start_cycle=0, 471 479 const bool debug_ok=false ); … … 502 510 TransactionTab m_trt; // xram transaction table 503 511 uint32_t m_upt_lines; 504 UpdateTab m_upt; // pending update & invalidate 512 UpdateTab m_upt; // pending update 513 UpdateTab m_ivt; // pending invalidate 505 514 CacheDirectory m_cache_directory; // data cache directory 506 515 CacheData m_cache_data; // data array[set][way][word] … … 591 600 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 592 601 593 sc_signal<size_t> r_config_ upt_index; // UPT index602 sc_signal<size_t> r_config_ivt_index; // IVT index 594 603 595 604 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 780 789 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 781 790 782 // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)783 sc_signal<bool> r_cleanup_to_cc_send_req; // valid request784 sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid785 sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index786 sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index787 sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack788 789 791 /////////////////////////////////////////////////////// 790 792 // Registers controlled by CAS fsm … … 872 874 sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap 873 875 sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data 874 sc_signal<size_t> r_xram_rsp_ upt_index; // UPT entry index876 sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index 875 877 sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap 876 878 … … 953 955 954 956 //////////////////////////////////////////////////// 957 // Registers controlled by ALLOC_IVT fsm 958 //////////////////////////////////////////////////// 959 960 sc_signal<int> r_alloc_ivt_fsm; 961 962 //////////////////////////////////////////////////// 955 963 // Registers controlled by ALLOC_HEAP fsm 956 964 ////////////////////////////////////////////////////
Note: See TracChangeset
for help on using the changeset viewer.