Changeset 468 for trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster

Timestamp:

Jul 24, 2013, 8:47:40 AM (11 years ago)

Author:

cfuguet

Message:

Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

• Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p

• Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

• Introducing third port for the CLACK network.
• CLEANUP FSM is no more a CC_SEND FSM client.
• CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

• Adding missing "strings" for print_trace() function
• Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

• Renaming FROM_MC DSPIN flits fields in M2P
• Renaming FROM_L1 DSPIN flits fields in P2M
• Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

• Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.

• Adding third port for the clack coherence network.

• Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

• In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

• Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

• Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.

Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

• This platform contains a third local crossbar interconnect for the CLACK network.

• It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

• Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

• Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

• Adding preprocessor conditional statements for ALMOS support

Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

• Renaming FROM_MC fields in M2P
• Renaming FROM_L1 fields in P2M
• Renaming CLEANUP_ACK fields in CLACK

Location:

trunk/platforms/tsar_generic_xbar

Files:

• . (modified) (1 prop)
• tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (2 diffs)
• tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (modified) (3 diffs)
• tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (modified) (9 diffs)

trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd

@@ -57 +57 @@
         Uses('caba:virtual_dspin_router', 
               flit_width      = parameter.Reference('dspin_rsp_width')),
-            
+
         Uses('caba:vci_multi_tty',
               cell_size       = parameter.Reference('vci_data_width_int')),
@@ -85 +85 @@
                 Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
                 Port('caba:clock_in', 'p_clk', auto = 'clock'),
-                Port('caba:dspin_output', 'p_cmd_out', [2, 4], 
+                Port('caba:dspin_output', 'p_cmd_out', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_cmd_width')),
-                Port('caba:dspin_input', 'p_cmd_in', [2, 4], 
+                Port('caba:dspin_input', 'p_cmd_in', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_cmd_width')),
-                Port('caba:dspin_output', 'p_rsp_out', [2, 4], 
+                Port('caba:dspin_output', 'p_rsp_out', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_rsp_width')), 
-                Port('caba:dspin_input', 'p_rsp_in', [2, 4], 
+                Port('caba:dspin_input', 'p_rsp_in', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_rsp_width')),
                 ],

trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h

@@ -69 +69 @@
     DspinSignals<dspin_cmd_width>   signal_dspin_m2p_l2g_c;
     DspinSignals<dspin_cmd_width>   signal_dspin_m2p_g2l_c;
+    DspinSignals<dspin_cmd_width>   signal_dspin_clack_l2g_c;
+    DspinSignals<dspin_cmd_width>   signal_dspin_clack_g2l_c;
     DspinSignals<dspin_rsp_width>   signal_dspin_rsp_l2g_d;
     DspinSignals<dspin_rsp_width>   signal_dspin_rsp_g2l_d;
@@ -115 +117 @@
     // Coherence DSPIN signals to local crossbar
     DspinSignals<dspin_cmd_width>     signal_dspin_m2p_memc;
+    DspinSignals<dspin_cmd_width>     signal_dspin_clack_memc;
     DspinSignals<dspin_rsp_width>     signal_dspin_p2m_memc;
     DspinSignals<dspin_cmd_width>     signal_dspin_m2p_proc[8];
+    DspinSignals<dspin_cmd_width>     signal_dspin_clack_proc[8];
     DspinSignals<dspin_rsp_width>     signal_dspin_p2m_proc[8];
 
@@ -198 +202 @@
     DspinLocalCrossbar<dspin_cmd_width>*          xbar_m2p_c;
     DspinLocalCrossbar<dspin_rsp_width>*          xbar_p2m_c;
+    DspinLocalCrossbar<dspin_cmd_width>*          xbar_clack_c;
 
     VirtualDspinRouter<dspin_cmd_width>*          router_cmd;

trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp

@@ -85 +85 @@
 {
     // Vectors of ports definition
-    p_cmd_in        = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 2);
-    p_cmd_out       = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 2);
+    p_cmd_in        = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 3);
+    p_cmd_out       = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 3);
     p_rsp_in        = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 4, 2);
     p_rsp_out       = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 4, 2);
@@ -148 +148 @@
                      8,                                  // TRANSACTION TABLE DEPTH
                      8,                                  // UPDATE TABLE DEPTH
+                     8,                                  // INVALIDATE TABLE DEPTH
                      debug_start_cycle,
                      memc_debug_ok );
@@ -269 +270 @@
 
     /////////////////////////////////////////////////////////////////////////////
+    xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
+                     "xbar_clack_c",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, l_width,
+                     1,                            // number of local sources
+                     nb_procs,                     // number of local targets 
+                     1, 1,                         // fifo depths
+                     true,                         // CMD
+                     false,                        // don't use local routing table
+                     false);                       // broadcast
+
+    /////////////////////////////////////////////////////////////////////////////
     router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
                      "router_cmd",
                      x_id,y_id,                    // coordinate in the mesh
                      x_width, y_width,             // x & y fields width
-                     2,                            // nb virtual channels
+                     3,                            // nb virtual channels
                      4,4);                         // input & output fifo depths
 
@@ -385 +399 @@
     for(int i = 0; i < 4; i++)
     {
-        for (int k = 0; k < 2; k++)
+        for (int k = 0; k < 3; k++)
         {
             router_cmd->p_out[i][k]          (this->p_cmd_out[i][k]);
             router_cmd->p_in[i][k]           (this->p_cmd_in[i][k]);
+        }
+
+        for (int k = 0; k < 2; k++)
+        {
             router_rsp->p_out[i][k]          (this->p_rsp_out[i][k]);
             router_rsp->p_in[i][k]           (this->p_rsp_in[i][k]);
@@ -396 +414 @@
     router_cmd->p_out[4][0]                  (signal_dspin_cmd_g2l_d);
     router_cmd->p_out[4][1]                  (signal_dspin_m2p_g2l_c);
+    router_cmd->p_out[4][2]                  (signal_dspin_clack_g2l_c);
     router_cmd->p_in[4][0]                   (signal_dspin_cmd_l2g_d);
     router_cmd->p_in[4][1]                   (signal_dspin_m2p_l2g_c);
+    router_cmd->p_in[4][2]                   (signal_dspin_clack_l2g_c);
 
     router_rsp->p_out[4][0]                  (signal_dspin_rsp_g2l_d);
@@ -403 +423 @@
     router_rsp->p_in[4][0]                   (signal_dspin_rsp_l2g_d);
     router_rsp->p_in[4][1]                   (signal_dspin_p2m_l2g_c);
+
 
     std::cout << "  - CMD & RSP routers connected" << std::endl;
@@ -473 +494 @@
     std::cout << "  - M2P Coherence crossbar connected" << std::endl;
 
+    ////////////////////// CLACK DSPIN local crossbar coherence
+    xbar_clack_c->p_clk                          (this->p_clk);
+    xbar_clack_c->p_resetn                       (this->p_resetn);
+    xbar_clack_c->p_global_out                   (signal_dspin_clack_l2g_c);
+    xbar_clack_c->p_global_in                    (signal_dspin_clack_g2l_c);
+    xbar_clack_c->p_local_in[0]                  (signal_dspin_clack_memc);
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_clack_c->p_local_out[p]               (signal_dspin_clack_proc[p]);
+
+    std::cout << "  - Clack Coherence crossbar connected" << std::endl;
+
     ////////////////////////// P2M DSPIN local crossbar coherence
     xbar_p2m_c->p_clk                            (this->p_clk);
@@ -491 +523 @@
         proc[p]->p_resetn                   (this->p_resetn);
         proc[p]->p_vci                      (signal_vci_ini_proc[p]);
-        proc[p]->p_dspin_in                 (signal_dspin_m2p_proc[p]);
-        proc[p]->p_dspin_out                (signal_dspin_p2m_proc[p]);
+        proc[p]->p_dspin_m2p                (signal_dspin_m2p_proc[p]);
+        proc[p]->p_dspin_p2m                (signal_dspin_p2m_proc[p]);
+        proc[p]->p_dspin_clack              (signal_dspin_clack_proc[p]);
         proc[p]->p_irq[0]                   (signal_proc_it[p]);
         for ( size_t j = 1 ; j < 6 ; j++)
@@ -549 +582 @@
     memc->p_vci_ixr                    (signal_vci_xram);
     memc->p_vci_tgt                    (signal_vci_tgt_memc);
-    memc->p_dspin_in                   (signal_dspin_p2m_memc);
-    memc->p_dspin_out                  (signal_dspin_m2p_memc);
+    memc->p_dspin_p2m                  (signal_dspin_p2m_memc);
+    memc->p_dspin_m2p                  (signal_dspin_m2p_memc);
+    memc->p_dspin_clack                (signal_dspin_clack_memc);
 
     // wrapper MEMC