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[99]1\begin{table}\leavevmode\center
2\begin{small}\begin{tabular}{|l|l|l|l|}\hline
3Segment                 & 2010   & 2011    & 2012 \\\hline\hline
4Communications          & 1,867  & 1,946   & 2,096 \\
5High end                & 467    & 511     & 550 \\\hline
6Consumer                & 550    & 592     & 672 \\
7High end                & 53     & 62      & 75 \\\hline
8Automotive              & 243    & 286     & 358 \\
9High end                & -      & -       & - \\\hline
10Industrial              & 1,102  & 1,228   & 1,406 \\
11High end                & 177    & 188     & 207 \\\hline
12Military/Aereo          & 566    & 636     & 717 \\
13High end                & 56     & 65      & 82 \\\hline\hline
14Total FPGA/PLD          & 4,659  & 5,015   & 5,583 \\
15Total High-End  FPGA    & 753    & 826     & 914 \\\hline
16\end{tabular}\end{small}
17\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)}
18\end{table}
19%
[171]20Microelectronic components allow the integration of complex functions into products, increases
[38]21commercial attractivity of these products and improves their competitivity.
[97]22Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
23thanks to the developpment of design methodologies and tools for embedded systems.
[171]24Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
[97]25and manufacturing ASICs is very high.
[38]26An IC foundry costs several billions of euros and the fabrication of a specific circuit
27costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
28million USD.
[171]29Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
[97]30volume markets.
[99]31\parlf
[18]32Today, FPGAs become important actors in the computational domain that was originally dominated
[32]33by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed
[97]34on a per-application basis. For many applications, FPGAs offer significant performance benefits over
35microprocessors implementation. There is still a performance degradation of one order
36of magnitude versus an equivalent ASIC implementations, but low cost
[171]37(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive
[18]38choice for low-to-medium volume applications.
39Since their introduction in the mid eighties, FPGAs evolved from a simple,
[134]40low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
[18]41provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
42on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
43complex systems like multi-processors platform with application dedicated coprocessors.
[32]44Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
[99]45various application domains. The ``high end'' lines concern only FPGA with high logic
46capacity for complex system implementations.
[18]47This market is in significant expansion and is estimated to 914\,M\$ in 2012.
[99]48The HPC market size is estimated today by FPGA providers at 214\,M\$.
49Using FPGA limits the NRE costs to the design cost.
50This boosts the developpment of automatic design tools and methodologies.
51%
52%Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp,
53%Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand
54%for very high performance (HPC) primes over other requirements. They tend to use the highest
55%performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative
56%architectures and algorithms. These companies show up in different "traditional" applications and market
57%segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC
58%emulation and prototyping, military/aereo etc. The HPC market size is estimated today by FPGA providers
59%at 214\,M\$.
60%%%
61\parlf
62This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
[171]63of FPGA-based solutions is limited by the lack of design automation.
[99]64Nowadays, there are neither commercial nor academic tools covering the whole design process
65from the system level specification to the bit stream generation.
66% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
67%              au dessous n'a pas de sens.
68% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
[171]69By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
[99]70parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
71processor,  bus core, ...) as well as incorporate their own IP.
72Designers can then generate a synthesized netlist, simulation test bench and custom
73software library that reflect the hardware configuration.
74%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
[134]75%% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite.
[99]76Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
77simulate the platform at a high design level (systemC).
78In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
79tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
[171]80PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
[99]81coprocessors from a C++ description.
82Nevertheless, they can only deal with data dominated applications and they do not handle
83the platform level.
84Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
85Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
86Designers can design and simulate a system using MATLAB and Simulink. The tool will then
87automatically generate synthesizable Hardware Description Language (HDL) code mapped to
88\xilinx pre-optimized macro-cells.
89However, this tool targets only DSP based algorithms.
90\\
91Consequently, a designer developping an embedded system needs to master four different
92design environments:
93\begin{enumerate}
[173]94  \item a virtual prototyping environment such as SoCLib for system level exploration,
[134]95  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
96  from \xilinx) to define the hardware architecture,
[99]97  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
98        coprocessor synthesis,
99  \item and finally backend synthesis tools (such as Quartus or Synopsys) for the bit-stream generation.
100\end{enumerate}
101Furthermore, mixing these tools requires an important interfacing effort and this makes
102the design process very complex and achievable only by designers skilled in many domains.
103\begin{center}\begin{minipage}{.8\linewidth}\textit{
[171]104The aim of the COACH project is to integrate all these design steps into a single design framework
[97]105and to allow \textbf{pure software} developpers to develop embedded systems.
[99]106}\end{minipage}\end{center}
107\parlf
108We believe that the combination of a design environment dedicated to software developpers
[171]109and FPGA targets,
110will allow small and even very small companies to propose embedded system and accelerating solutions
111for standard software applications with attractive and competitive prices.
[97]112This new market may explode in the same way as the micro-computer market in the eighties,
113whose success was due to the low cost of the first micro-processors (compared to main frames)
114and the advent of high level programming languages which allowed a high number of programmers
115to launch start-ups in software engineering.
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