source: anr/section-2.2.tex @ 199

% Relevance of the proposal 
The COACH proposal addresses directly the \emph{Embedded Systems} item of
the ARPEGE program. It aims to propose solutions to the societal/economical challenges by
providing SMEs novel design capabilities enabling them to increase their
design productivity with design exploration and synthesis methods that are placed on top 
of the state-of-the-art methods.
This project proposes an open-source framework for mapping multi-tasks software applications
on Field Programmable Gate Array circuits (FPGA).
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\parlf
COACH will contribute to build an open development and run-time
environment, including communication middleware and tools to support
developers in the production of embedded software, through all phases of the software lifecycle,
from requirements analysis downto deployment and maintenance.
More specifically, COACH focuses on:
\begin{itemize}
\item High level methods and concepts (esp. requirements and architectural level) for system
design, development and integration, addressing complexity aspects and modularity.
\item Open and modular development environments, enabling flexibility and extensibility by
means of new or sector-specific tools and ensuring consistency and traceability along the
development lifecycle.
\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive
environment, suitable for co-operative and distributed development.
\end{itemize}
COACH outcome will contribute to strengthen Europe's competitive position by developing
technologies and methodologies for product development, focusing (in compliance with the
scope of the above program) on technologies, engineering methodologies, novel tools,
methods which facilitate resource use efficiency. The approaches and tools to be developed 
in COACH will enable new and emerging information technologies for the development,
manufacturing and integration of devices and related software into end-products.
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\parlf\noindent
The COACH project will benefit from a number of previous recent projects:
\begin{description}
  \item[SOCLIB]
    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
    10 academic laboratories and and 6 industrial companies.
    (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 
    industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). 
    It supports system level virtual prototyping of shared memory, multi-processors
    architectures, and provides tools to map multi-tasks software application on these
    architectures, for reliable performance evaluation.
    The core of this platform is a library of SystemC simulation models for 
    general purpose IP cores such as processors, buses, networks, memories, IO controller.
    The platform provides also embedded operating systems and software/hardware
    communication middleware.
    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    this project enhances SoCLib by providing the synthesisable VHDL models required
    for FPGA synthesis.
  \item[ROMA] The ROMA ANR project (2007-2010)
    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
    proposes to develop a reconfigurable processor, exhibiting high
    silicon density and power efficiency, able to adapt its computing
    structure to computation patterns that can be speed-up and/or
    power efficient.  The ROMA project study a pipeline-based of
    evolved low-power coarse grain reconfigurable operators to avoid
    traditional overhead, in reconfigurable devices, related to the
    interconnection network.  The project will borrow from the ROMA
    ANR project and the ongoing joint INRIA-STMicro
    Nano2012 project to adapt existing pattern extraction algorithms
    and datapath merging techniques to the synthesis of customized
    ASIP processors.
  \item[TSAR]
    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL 
    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
  \item[BioWic]
    On the HPC application side, we also hope to benefit from the experience in
    hardware acceleration of bioinformatic algorithms/workfows gathered by the
    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    be able to validate the framework on real-life HPC applications.
\end{description}
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\parlf\noindent
The laboratories involved in the COACH project have a well estabished expertise
in the following domains:
\begin{itemize}
  \item 
    In the field of High Level Synthesis (HLS), the project
    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
    by the \upmc and \tima laboratories. 
  \item
    Regarding system level architecture, the project is based on the know-how
    acquired by the \upmc and \tima laboratories in the framework of various projects  
    in the field of communication architectures for shared memory multi-processors systems
    (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA).
    As an example, the DSPIN project is now used in the TSAR project.
  \item
    Regarding Application Specific Instruction Processor (ASIP) design, the
    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
    expertise in the domain of retargetable compiler
    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
    compilers~\cite{ASAP05} since 2002).
\item
    In the field of compilers, the Compsys group was founded in 2002 
    by several senior researchers with experience in
    high performance computing and automatic parallelization. They have been
    among the initiators of the polyhedral model, a theory which serve to
    unify many parallelism detection and exploitation techniques for regular
    programs. It is expected that the techniques developped by Compsys for
    parallelism detection, scheduling, process construction and memory management
    will be very useful as a front-end for the a high-level synthesis tools.
\end{itemize}
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\parlf\noindent
The COACH project answers to several of the challenges found in different axis of the 
call for proposals.%Keywords of the call are indicated below in italic writing.
\begin{description}
\item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\
COACH will address new embedded systems architectures by allowing the design of 
Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 
constraints and objectives (real-time, low-power). It will permit to design  complex SoC 
based on IP cores (memory, peripherals, network controllers, communication processors), 
running Embedded Software, as well as an Operating System with associated middleware and 
API and using hardware accelerator automatically generated. It will also permit to use 
efficiently different dynamic system management techniques and re-configuration mechanisms.
\textbf{Thereby COACH well corresponds to axis 1}.
%
\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
COACH will address High-Performance Computing (HPC) by helping designer to accelerate an 
application running on a PC by migrating critical parts into a SoC implemented on an FPGA 
plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer 
effort through the development of tools that translate high level language programs to FPGA 
configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance 
as well as reducing the required area.
\textbf{Thereby COACH partially corresponds to axis 2}.
%
% IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et
% IA2PC: secondaire.
\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
%VERS 1
%Future control applications employ more and more SoC.
%Application domains for such systems are for example the automotive domain, as well as the
%aerospace and avionics domains.
%In all cases, high performance and real time requirements are combined with 
%requirements to low power, low temperature, high dependability, and low cost.\\
%Similary manufacturing, security and safety technologies require also more and more
%computation power. 
%VERS 2 pour gagner de la place
Manufacturing, controling, security and safety technologies employ more and more SoC.
COACH will permit to design such complex digital systems.
\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
\end{description}
%Axis 3 "Robotique et contr\^{o}le/commande}"
%
%COACH will permit to design complex digital systems based on high-performance multi-core systems.
%Like in the consumer electronics domain (telecommunication, multimedia), future control applications 
%will employ more and more SoC not just for typical consumer functionality, but also for safety and 
%security applications (by performing complex analyses on data gathered with intelligent sensors, 
%by initiating appropriate responses to dangerous phenomena...). Application domains for such systems 
%are for example the automotive domain, as well as the aerospace and avionics domains (i.e. sophisticated on-board 
%radar systems, collision-detection, intelligent navigation...). 
%Manufacturing technology will also increasingly need high-end vision analysis and high-speed 
%robot control. In all cases, high performance and real time requirements are combined with 
%requirements to low power, low temperature, high dependability, and low cost.
%
%Axis 5 "S\'{e}curit\'{e} et suret\'{e}" :
%
%The results of the COACH project will help users to build cryptographic secure systems implemented in
%hardware or both in software/ hardware in an effective way, substantially enhancing the
%process productivity of the cryptographic algorithms hardware synthesis, improving the
%quality and reducing the design time and the cost of synthesised cryptographic devices.

% IA2PC: 1) je ne vois pas trop ce que ca fait la.
% IA2PC: 2) c'est deja dans le 2.1 pour le small business.
% IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense
% IA2PC     toujours que le large business est encore vise par COACH.
% IA2PC     Alain a enleve toute reference sur ce large business. Sa raison est +
% IA2PC     politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille
% IA2PC     le message. Je partage assez son avis, la version actuelle est + claire que
% IA2PC     celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses
% IA2PC     boites.
% IA2PC
% IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large
% IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans
% IA2PC les sections precedentes.
%
% VERS 2 pour gagner de la place je l'enleve
% COACH technologies can be used in both large and small business, as they will permit users to design
% embedded systems which meet a wide range of requirements: from low cost and low power consuming
% devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
% systems designed via the approaches and tools targeted by COACH, there is the potential for greater
% efficiency, improved business processes and models. The net results: lower costs, faster response times,
% better service, and higher revenue.
\parlf
Finally, it is worth to note that this project covers priorities defined by the commission 
experts in the field of Information Technolgies Society (IST) for Embedded
Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity
and allowing to apply efficiently applications and various products on embedded platforms,
considering resources constraints (delays, power, memory, etc.), security and quality
services$>>$}.