[25] | 1 | % Relevance of the proposal |
---|
[97] | 2 | The COACH proposal addresses directly the \emph{Embedded Systems} item of |
---|
[67] | 3 | the ARPEGE program. It aims to propose solutions to the societal/economical challenges by |
---|
[97] | 4 | providing SMEs novel design capabilities enabling them to increase their |
---|
[25] | 5 | design productivity with design exploration and synthesis methods that are placed on top |
---|
[97] | 6 | of the state-of-the-art methods. |
---|
| 7 | This project proposes an open-source framework for mapping multi-tasks software applications |
---|
| 8 | on Field Programmable Gate Array circuits (FPGA). |
---|
[99] | 9 | %%% |
---|
| 10 | \parlf |
---|
[97] | 11 | COACH will contribute to build an open development and run-time |
---|
| 12 | environment, including communication middleware and tools to support |
---|
[25] | 13 | developers in the production of embedded software, through all phases of the software lifecycle, |
---|
[177] | 14 | from requirements analysis downto deployment and maintenance. |
---|
[25] | 15 | More specifically, COACH focuses on: |
---|
| 16 | \begin{itemize} |
---|
| 17 | \item High level methods and concepts (esp. requirements and architectural level) for system |
---|
| 18 | design, development and integration, addressing complexity aspects and modularity. |
---|
| 19 | \item Open and modular development environments, enabling flexibility and extensibility by |
---|
| 20 | means of new or sector-specific tools and ensuring consistency and traceability along the |
---|
| 21 | development lifecycle. |
---|
| 22 | \item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive |
---|
| 23 | environment, suitable for co-operative and distributed development. |
---|
| 24 | \end{itemize} |
---|
| 25 | COACH outcome will contribute to strengthen Europe's competitive position by developing |
---|
| 26 | technologies and methodologies for product development, focusing (in compliance with the |
---|
[204] | 27 | %scope of the above program) on technologies, engineering methodologies, novel tools, |
---|
| 28 | %methods which facilitate resource use efficiency. The approaches and tools to be developed |
---|
| 29 | %in COACH will enable new and emerging information technologies for the development, |
---|
| 30 | %methods which facilitate resource use efficiency. The COACH approaches and tools |
---|
| 31 | scope of the above program) on technologies, engineering methodologies, novel tools |
---|
| 32 | which facilitate resource use efficiency. The COACH approaches and tools |
---|
| 33 | will enable new and emerging information technologies for the development, |
---|
[25] | 34 | manufacturing and integration of devices and related software into end-products. |
---|
[99] | 35 | %%% |
---|
[191] | 36 | \parlf\noindent |
---|
[177] | 37 | The COACH project will benefit from a number of previous recent projects: |
---|
[99] | 38 | \begin{description} |
---|
| 39 | \item[SOCLIB] |
---|
[233] | 40 | The SoCLib ANR platform (2007-2009) is an open infrastructure developped by |
---|
| 41 | 10 academic laboratories and and 6 industrial companies. It supports |
---|
| 42 | system level virtual prototyping of shared memory, multi-processors |
---|
[204] | 43 | architectures. It provides tools to map multi-tasks software application on these |
---|
[199] | 44 | (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 |
---|
| 45 | industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). |
---|
[233] | 46 | It supports system level virtual prototyping of shared memory, multi-processors |
---|
| 47 | architectures, and provides tools to map multi-tasks software application on these |
---|
| 48 | architectures, for reliable performance evaluation. |
---|
[99] | 49 | The core of this platform is a library of SystemC simulation models for |
---|
| 50 | general purpose IP cores such as processors, buses, networks, memories, IO controller. |
---|
| 51 | The platform provides also embedded operating systems and software/hardware |
---|
| 52 | communication middleware. |
---|
| 53 | The synthesisable VHDL models of IPs are not part of the SoCLib platform, and |
---|
[233] | 54 | this project enhances SoCLib by providing the synthesisable VHDL models required |
---|
| 55 | for FPGA synthesis. |
---|
| 56 | The synthesisable VHDL models of IPs are not part of the SoCLib platform, and |
---|
[204] | 57 | this project enhances SoCLib by providing them. |
---|
[233] | 58 | \item[ROMA] The ROMA ANR project \cite{roma} |
---|
| 59 | involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D, |
---|
[120] | 60 | proposes to develop a reconfigurable processor, exhibiting high |
---|
| 61 | silicon density and power efficiency, able to adapt its computing |
---|
| 62 | structure to computation patterns that can be speed-up and/or |
---|
| 63 | power efficient. The ROMA project study a pipeline-based of |
---|
| 64 | evolved low-power coarse grain reconfigurable operators to avoid |
---|
| 65 | traditional overhead, in reconfigurable devices, related to the |
---|
| 66 | interconnection network. The project will borrow from the ROMA |
---|
| 67 | ANR project and the ongoing joint INRIA-STMicro |
---|
| 68 | Nano2012 project to adapt existing pattern extraction algorithms |
---|
[204] | 69 | and datapath merging techniques to ASIP synthesis. |
---|
| 70 | % and datapath merging techniques to the synthesis of customized |
---|
| 71 | % ASIP processors. |
---|
[99] | 72 | \item[TSAR] |
---|
[233] | 73 | The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a |
---|
| 74 | % The TSAR MEDEA+ project (2008-2010) targets the design of a |
---|
[99] | 75 | scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib |
---|
| 76 | plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL |
---|
| 77 | models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect). |
---|
| 78 | \item[BioWic] |
---|
| 79 | On the HPC application side, we also hope to benefit from the experience in |
---|
| 80 | hardware acceleration of bioinformatic algorithms/workfows gathered by the |
---|
| 81 | CAIRN group in the context of the ANR BioWic project (2009-2011), so as to |
---|
| 82 | be able to validate the framework on real-life HPC applications. |
---|
| 83 | \end{description} |
---|
| 84 | %%% |
---|
[191] | 85 | \parlf\noindent |
---|
[97] | 86 | The laboratories involved in the COACH project have a well estabished expertise |
---|
[204] | 87 | %in the following domains: |
---|
| 88 | in the domains: |
---|
[97] | 89 | \begin{itemize} |
---|
[99] | 90 | \item |
---|
| 91 | In the field of High Level Synthesis (HLS), the project |
---|
| 92 | leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project |
---|
| 93 | developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped |
---|
| 94 | by the \upmc and \tima laboratories. |
---|
| 95 | \item |
---|
| 96 | Regarding system level architecture, the project is based on the know-how |
---|
| 97 | acquired by the \upmc and \tima laboratories in the framework of various projects |
---|
[135] | 98 | in the field of communication architectures for shared memory multi-processors systems |
---|
| 99 | (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). |
---|
| 100 | As an example, the DSPIN project is now used in the TSAR project. |
---|
[99] | 101 | \item |
---|
| 102 | Regarding Application Specific Instruction Processor (ASIP) design, the |
---|
[120] | 103 | CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of |
---|
[99] | 104 | expertise in the domain of retargetable compiler |
---|
| 105 | (Armor/Calife~\cite{CODES99} since 1996, and the Gecos |
---|
| 106 | compilers~\cite{ASAP05} since 2002). |
---|
[97] | 107 | \item |
---|
[99] | 108 | In the field of compilers, the Compsys group was founded in 2002 |
---|
| 109 | by several senior researchers with experience in |
---|
| 110 | high performance computing and automatic parallelization. They have been |
---|
| 111 | among the initiators of the polyhedral model, a theory which serve to |
---|
| 112 | unify many parallelism detection and exploitation techniques for regular |
---|
| 113 | programs. It is expected that the techniques developped by Compsys for |
---|
| 114 | parallelism detection, scheduling, process construction and memory management |
---|
| 115 | will be very useful as a front-end for the a high-level synthesis tools. |
---|
[97] | 116 | \end{itemize} |
---|
[99] | 117 | %%% |
---|
[191] | 118 | \parlf\noindent |
---|
[177] | 119 | The COACH project answers to several of the challenges found in different axis of the |
---|
[191] | 120 | call for proposals.%Keywords of the call are indicated below in italic writing. |
---|
| 121 | \begin{description} |
---|
| 122 | \item[Axis 1] \textit{Architectures des syst\`{e}mes embarqu\'{e}s} \\ |
---|
[177] | 123 | COACH will address new embedded systems architectures by allowing the design of |
---|
| 124 | Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design |
---|
| 125 | constraints and objectives (real-time, low-power). It will permit to design complex SoC |
---|
| 126 | based on IP cores (memory, peripherals, network controllers, communication processors), |
---|
| 127 | running Embedded Software, as well as an Operating System with associated middleware and |
---|
| 128 | API and using hardware accelerator automatically generated. It will also permit to use |
---|
[191] | 129 | efficiently different dynamic system management techniques and re-configuration mechanisms. |
---|
| 130 | \textbf{Thereby COACH well corresponds to axis 1}. |
---|
| 131 | % |
---|
| 132 | \item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\ |
---|
[177] | 133 | COACH will address High-Performance Computing (HPC) by helping designer to accelerate an |
---|
| 134 | application running on a PC by migrating critical parts into a SoC implemented on an FPGA |
---|
| 135 | plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer |
---|
| 136 | effort through the development of tools that translate high level language programs to FPGA |
---|
| 137 | configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance |
---|
| 138 | as well as reducing the required area. |
---|
[191] | 139 | \textbf{Thereby COACH partially corresponds to axis 2}. |
---|
| 140 | % |
---|
| 141 | % IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et |
---|
| 142 | % IA2PC: secondaire. |
---|
[204] | 143 | %VERS 3 |
---|
[233] | 144 | %\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\ |
---|
| 145 | %Manufacturing technology employs more and more SoC. |
---|
| 146 | %COACH will permit to design such complex digital systems. |
---|
| 147 | %\textbf{Thereby COACH indirectly answers to axis 3 too}. |
---|
| 148 | |
---|
| 149 | |
---|
[204] | 150 | %\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\ |
---|
[191] | 151 | %VERS 1 |
---|
| 152 | %Future control applications employ more and more SoC. |
---|
| 153 | %Application domains for such systems are for example the automotive domain, as well as the |
---|
| 154 | %aerospace and avionics domains. |
---|
| 155 | %In all cases, high performance and real time requirements are combined with |
---|
| 156 | %requirements to low power, low temperature, high dependability, and low cost.\\ |
---|
| 157 | %Similary manufacturing, security and safety technologies require also more and more |
---|
| 158 | %computation power. |
---|
| 159 | %VERS 2 pour gagner de la place |
---|
[204] | 160 | %Manufacturing, controling, security and safety technologies employ more and more SoC. |
---|
| 161 | %COACH will permit to design such complex digital systems. |
---|
| 162 | %\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}. |
---|
[233] | 163 | |
---|
| 164 | %\end{description} |
---|
| 165 | |
---|
| 166 | \item [Axis 3] \textit {Robotique et contr\^{o}le/commande}: |
---|
| 167 | |
---|
| 168 | COACH will address robotic and control applications domains by |
---|
| 169 | allowing to design complex digital systems based on MPSoC architecture. |
---|
| 170 | Like in the consumer electronics domain, future control applications |
---|
| 171 | will employ more and more SoC for safety and security applications. |
---|
| 172 | Application domains for such systems are for example automotive, |
---|
| 173 | aerospace or avionics domains (e.g. collision-detection, intelligent navigation...). |
---|
| 174 | Manufacturing technology will also increasingly need high-end vision analysis and high-speed |
---|
| 175 | robot control. |
---|
| 176 | \textbf{Thereby COACH indirectly answers to axis 3}. |
---|
| 177 | |
---|
| 178 | \item [Axis 5] \textit {S\'{e}curit\'{e} et suret\'{e}}: |
---|
| 179 | |
---|
| 180 | The results of the COACH project will help users to build cryptographic secure systems implemented in |
---|
| 181 | hardware or both in software/hardware in an effective way, substantially enhancing the |
---|
| 182 | process productivity of the cryptographic algorithms hardware synthesis, improving the |
---|
| 183 | quality and reducing the design time and the cost of synthesised cryptographic devices. |
---|
| 184 | \textbf{Thereby COACH indirectly answers to axis 5}. |
---|
| 185 | |
---|
[191] | 186 | \end{description} |
---|
[177] | 187 | |
---|
[191] | 188 | % IA2PC: 1) je ne vois pas trop ce que ca fait la. |
---|
| 189 | % IA2PC: 2) c'est deja dans le 2.1 pour le small business. |
---|
| 190 | % IA2PC: 3) Pour le large business, on avait mis ca dans la premiere version et je pense |
---|
| 191 | % IA2PC toujours que le large business est encore vise par COACH. |
---|
| 192 | % IA2PC Alain a enleve toute reference sur ce large business. Sa raison est + |
---|
| 193 | % IA2PC politico/stylistique: en parlant des 2 on n'est pas tres clair et on brouille |
---|
| 194 | % IA2PC le message. Je partage assez son avis, la version actuelle est + claire que |
---|
| 195 | % IA2PC celle d'avant. De plus on ne dit jamais que l'on ne vise pas les grosses |
---|
| 196 | % IA2PC boites. |
---|
| 197 | % IA2PC |
---|
| 198 | % IA2PC Bref je serai assez pour enlever ce paragraphe, et ne pas faire reference au large |
---|
| 199 | % IA2PC business meme dans les section precedente. Par contre d'essayer de recaser le reste dans |
---|
| 200 | % IA2PC les sections precedentes. |
---|
| 201 | % |
---|
| 202 | % VERS 2 pour gagner de la place je l'enleve |
---|
[233] | 203 | |
---|
| 204 | %PC2IA ok pas de probleme |
---|
| 205 | |
---|
[191] | 206 | % COACH technologies can be used in both large and small business, as they will permit users to design |
---|
| 207 | % embedded systems which meet a wide range of requirements: from low cost and low power consuming |
---|
| 208 | % devices to very high speed devices, based on parallel computing. For enterprises that will use embedded |
---|
| 209 | % systems designed via the approaches and tools targeted by COACH, there is the potential for greater |
---|
| 210 | % efficiency, improved business processes and models. The net results: lower costs, faster response times, |
---|
| 211 | % better service, and higher revenue. |
---|
[204] | 212 | %\parlf |
---|
[177] | 213 | Finally, it is worth to note that this project covers priorities defined by the commission |
---|
[19] | 214 | experts in the field of Information Technolgies Society (IST) for Embedded |
---|
[199] | 215 | Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity |
---|
[19] | 216 | and allowing to apply efficiently applications and various products on embedded platforms, |
---|
[191] | 217 | considering resources constraints (delays, power, memory, etc.), security and quality |
---|
[199] | 218 | services$>>$}. |
---|