source: anr/task-3.tex @ 272

\begin{taskinfo}
\let\LIP\leader
\let\IRISA\enable
\let\UBS\enable
\let\UPMC\enable
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
The objective of this task is to convert the input specification of
an hardware accelerator, which must be written in a familiar language
(C/C++) with as few constraints as possible, into a form suitable for
the HLS tools (i.e. HAS back-end tools of the COACH project). If the 
target is an ASIP, the frontend has to extract 
patterns from the source code and convert them into the definition
of an extensible processor. If the target is a process network, the
front end has to distribute the workload and the data sets as fairly
as possible, identify communication channels, and output an \xcoach
description.
\end{objectif}
%
\begin{workpackage}
  \subtask This sub-task aims at providing compiler support for custom instructions 
  within the HAS front-end. It will take as input the COACH intermediate 
  representation, and will output an annotated COACH IR containing the custom
  instructions definitions along with their occurrence in the application.
    \begin{livrable}
      \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow}
        In this first version of the software, the computations patterns corresponding to
        custom instructions are specified by the user, and then automatically extracted (when
        beneficial) from the application intermediate representation. 
      \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0}
        In this second version, the software will also be able to automatically identify 
        interesting pattern candidates in the application code, and use them as custom 
        instructions.  
    \end{livrable}
 
 \subtask In this sub-task, we provide micro-architectural template models for the two target
 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. 
 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
 of the architecture, along with its architectural extensions 
    \begin{livrable}
      \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS }
      { A SystemC simulation model for a simple extensible MIPS architectural template }
      \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
      its instruction set extensions}
      \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
          { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
          already available from \altera}
      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
      \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
      its instruction set extensions}
      \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
      the different approaches}
    \end{livrable}

  \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.

   \begin{livrable}
    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
      Description and specification of a process construction method for programs with 
      polyhedral loops. 
    \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9}
      Final assessment of the method and improved version of the specification.
    \itemV{6}{12}{x}{\Slip}{Process construction}
      Preliminary implementation in the Syntol framework. 
      At this step the software will just implement a single constructor.
    \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
      Implementation of the array contraction and FIFO construction algorithm. 
      Conversion of the input and output to the \xcoach format.
    \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension}
      Extension of automatic parallelization and array contraction
      to non-polyhedral loops. Implementation in the Bee framework.
    \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{10:20:12}
      Final release taking into account the feedbacks from the 
      demonstrator \STs.
   \end{livrable}

\end{workpackage}