Changeset 52 for anr/task-5.tex
- Timestamp:
- Jan 31, 2010, 10:17:25 PM (15 years ago)
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anr/task-5.tex
r40 r52 24 24 \end{objectif} 25 25 % 26 \begin{workpackage} {D5}26 \begin{workpackage} 27 27 \item This \ST is the definition of the communication schemes as a software API 28 28 (Application Programing Interface) between the application part running on the PC and 29 29 the application part running on the FPGA-SoC. 30 30 \begin{livrable} 31 \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. 32 \global\edef\hpcCommApi{\name} 31 \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} 32 \setMacroInAuxFile{hpcCommApi} 33 User refernce manual describing the API. 33 34 \end{livrable} 34 35 \item This \ST consists in helping to partition the application. … … 36 37 the partitioned application. 37 38 \begin{livrable} 38 \item {}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication39 A PI defined in the {\hpcCommApi} delivrable.39 \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} 40 A library implementing the communication API defined in the {\hpcCommApi} delivrable. 40 41 \end{livrable} 41 42 \item This \ST deals with the implementation of the communication API on the both sides (PC 42 43 part and FPGA-SoC). 43 44 \begin{livrable} 44 \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API 45 that comminicates with the FPGA-SOC, a library and probably a LINUX module. 46 \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a 47 driver.\global\edef\hpcMutekDriver{\name} 48 \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS. 45 \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0} 46 The PC part of the HPC communication API that comminicates with the FPGA-SOC, a 47 library and probably a LINUX module. 48 \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0} 49 \setMacroInAuxFile{hpcMutekDriver} 50 The FPGA-SoC part of the communication API, a driver. 51 \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:0:0} 52 Port of the {\hpcMutekDriver} driver on the DNA OS. 53 \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} 54 Maintenance work of HPC API for both Lunix PC and MUTEK OS. 49 55 \end{livrable} 50 56 \item This \ST deals with the implementation of hardware required by the COACH 51 57 architectural template for using the PCI/X IP of \altera and \xilinx. 52 58 \begin{livrable} 53 \item {}{9}{18}{h}{\Stima}{HPC hardware \xilinx}59 \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{0:0:0} 54 60 \setMacroInAuxFile{hpcPlbBridge} 55 61 The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. 56 \item {}{9}{18}{h}{\Saltera}{HPC hardware \altera}62 \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0} 57 63 \setMacroInAuxFile{hpcAvalonBridge} 58 64 The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. … … 60 66 \item This \ST deals with the dynamic reconfiguration of an FPGA. 61 67 \begin{livrable} 62 \item {}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}63 \ global\edef\hpcDynconfDriver{\name}68 \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0} 69 \setMacroInAuxFile{hpcDynconfDriver} 64 70 \mustbecompleted{FIXME:TIMA ....} 65 \item {}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}71 \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} 66 72 Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. 67 \item {}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}73 \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2} 68 74 \mustbecompleted{FIXME:TIMA ....} 69 \item {}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}75 \itemL{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}{0:0:0} 70 76 \mustbecompleted{FIXME:TIMA ....} 71 77 \end{livrable} … … 74 80 They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. 75 81 \begin{livrable} 76 \item {}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards.82 \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. 77 83 \end{livrable} 78 84 \end{workpackage}
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