[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 117 2009-05-16 14:42:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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| 18 | |
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[111] | 19 | #define get_priority(x) \ |
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| 20 | (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ |
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| 21 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ |
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| 22 | (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ |
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| 23 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ |
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| 24 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \ |
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| 25 | (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ |
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| 26 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ |
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| 27 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?2: \ |
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| 28 | ((state == EVENT_TYPE_EXCEPTION)?1: \ |
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| 29 | 0))) |
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| 30 | |
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[83] | 31 | #undef FUNCTION |
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| 32 | #define FUNCTION "Context_State::transition" |
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| 33 | void Context_State::transition (void) |
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| 34 | { |
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| 35 | log_begin(Context_State,FUNCTION); |
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[88] | 36 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 37 | |
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| 38 | if (PORT_READ(in_NRESET) == 0) |
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| 39 | { |
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[88] | 40 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 41 | { |
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| 42 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 43 | reg_INTERRUPT_ENABLE [i] = 0; |
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| 44 | } |
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[83] | 45 | } |
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| 46 | else |
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| 47 | { |
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[88] | 48 | // ------------------------------------------------------------------- |
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[101] | 49 | // -----[ next state ]------------------------------------------------ |
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| 50 | // ------------------------------------------------------------------- |
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| 51 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 52 | { |
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| 53 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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| 54 | |
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| 55 | Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 56 | // Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 57 | |
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| 58 | context_state_t state = reg_STATE [i]; |
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| 59 | |
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| 60 | switch (state) |
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| 61 | { |
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| 62 | case CONTEXT_STATE_OK : |
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| 63 | { |
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| 64 | // nothing, wait an event |
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| 65 | break; |
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| 66 | } |
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| 67 | case CONTEXT_STATE_KO_EXCEP : |
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| 68 | { |
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| 69 | // Wait end of all instruction |
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| 70 | if (inst_all == 0) |
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| 71 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 72 | break; |
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| 73 | } |
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| 74 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 75 | { |
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| 76 | // nothing, wait the update of internal register (pc) |
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| 77 | break; |
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| 78 | } |
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[111] | 79 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
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| 80 | { |
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| 81 | // nothing : wait end of update upt |
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| 82 | break; |
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| 83 | } |
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[105] | 84 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
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[101] | 85 | { |
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| 86 | // Wait end of all instruction |
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| 87 | if (inst_all == 0) |
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| 88 | |
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| 89 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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[105] | 90 | state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[101] | 91 | break; |
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| 92 | } |
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[105] | 93 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : |
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| 94 | { |
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| 95 | // Wait end of all instruction |
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| 96 | if (inst_all == 0) |
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| 97 | state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 98 | |
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| 99 | break; |
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| 100 | } |
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[101] | 101 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 102 | { |
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| 103 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 104 | break; |
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| 105 | } |
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[105] | 106 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
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[101] | 107 | { |
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| 108 | // nothing, wait the update of internal register (pc) |
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| 109 | break; |
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| 110 | } |
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[105] | 111 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 112 | { |
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| 113 | // nothing, wait the update of internal register (pc) |
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| 114 | break; |
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| 115 | } |
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[111] | 116 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : |
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[108] | 117 | { |
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[111] | 118 | // nothing : wait end of update upt |
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| 119 | break; |
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| 120 | } |
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| 121 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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| 122 | { |
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[108] | 123 | // nothing, wait the update of internal register (pc) |
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| 124 | break; |
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| 125 | } |
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[111] | 126 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
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| 127 | { |
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| 128 | // Wait end of all instruction |
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| 129 | if (inst_all == 0) |
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| 130 | |
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| 131 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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| 132 | state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 133 | break; |
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| 134 | } |
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[101] | 135 | // case CONTEXT_STATE_KO_PSYNC : |
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| 136 | // { |
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| 137 | // // Wait end of all instruction |
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| 138 | // if (inst_all == 0) |
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| 139 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 140 | // break; |
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| 141 | // } |
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| 142 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 143 | { |
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| 144 | // nothing, wait end of flush (ifetch) |
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| 145 | if (inst_all == 0) |
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| 146 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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| 147 | state = CONTEXT_STATE_OK; |
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| 148 | |
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| 149 | break; |
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| 150 | } |
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| 151 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 152 | { |
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| 153 | // nothing, wait the pc write |
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| 154 | break; |
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| 155 | } |
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| 156 | // case CONTEXT_STATE_KO_CSYNC : |
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| 157 | // { |
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| 158 | // // Wait end of all instruction |
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| 159 | // if (inst_all == 0) |
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| 160 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 161 | // break; |
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| 162 | // } |
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| 163 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 164 | { |
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| 165 | // nothing, wait end of flush (all internal structure) |
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| 166 | if (inst_all == 0) |
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| 167 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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| 168 | break; |
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| 169 | } |
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| 170 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 171 | { |
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| 172 | // nothing, wait the pc write |
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| 173 | break; |
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| 174 | } |
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| 175 | // case CONTEXT_STATE_KO_MSYNC : |
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| 176 | // { |
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| 177 | // // Wait end of memory instruction |
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| 178 | // if (inst_mem == 0) |
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| 179 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 180 | // break; |
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| 181 | // } |
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| 182 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 183 | // { |
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| 184 | // // Wait the msync issue |
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| 185 | // if (inst_mem != 0) |
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| 186 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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| 187 | // break; |
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| 188 | // } |
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| 189 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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| 190 | { |
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| 191 | // Wait the end of msync |
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| 192 | if (inst_all == 0) |
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| 193 | state = CONTEXT_STATE_OK; |
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| 194 | break; |
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| 195 | } |
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| 196 | // case CONTEXT_STATE_KO_SPR : |
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| 197 | // { |
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| 198 | // // Wait end of all instruction |
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| 199 | // if (inst_all == 0) |
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| 200 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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| 201 | // break; |
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| 202 | // } |
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| 203 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 204 | // { |
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| 205 | // // Wait the spr_access issue |
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| 206 | // if (inst_all != 0) |
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| 207 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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| 208 | // break; |
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| 209 | // } |
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| 210 | case CONTEXT_STATE_KO_SPR_EXEC : |
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| 211 | { |
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| 212 | // Wait the spr_access execution |
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| 213 | if (inst_all == 0) |
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| 214 | state = CONTEXT_STATE_OK; |
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| 215 | break; |
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| 216 | } |
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| 217 | |
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| 218 | default : |
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| 219 | { |
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| 220 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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| 221 | } |
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| 222 | } |
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| 223 | reg_STATE [i] = state; |
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| 224 | } |
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| 225 | |
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| 226 | // ------------------------------------------------------------------- |
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[111] | 227 | // -----[ EVENT ]----------------------------------------------------- |
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| 228 | // ------------------------------------------------------------------- |
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| 229 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 230 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 231 | { |
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| 232 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
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| 233 | // Write pc |
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| 234 | context_state_t state = reg_STATE [i]; |
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| 235 | |
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| 236 | switch (state) |
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| 237 | { |
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| 238 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 239 | { |
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| 240 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 241 | break; |
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| 242 | } |
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| 243 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: |
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| 244 | |
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| 245 | // { |
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| 246 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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| 247 | // break; |
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| 248 | // } |
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| 249 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 250 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 251 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 252 | { |
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| 253 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 254 | break; |
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| 255 | } |
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| 256 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
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| 257 | { |
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| 258 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 259 | break; |
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| 260 | } |
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| 261 | default : |
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| 262 | { |
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| 263 | #ifdef DEBUG_TEST |
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| 264 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 265 | #endif |
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| 266 | break; |
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| 267 | } |
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| 268 | } |
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| 269 | } |
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| 270 | |
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| 271 | // ------------------------------------------------------------------- |
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[88] | 272 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 273 | // ------------------------------------------------------------------- |
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| 274 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 275 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 276 | { |
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[98] | 277 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 278 | |
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[88] | 279 | context_state_t state = reg_STATE [i]; |
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[83] | 280 | |
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[98] | 281 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 282 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 283 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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[106] | 284 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; |
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[88] | 285 | |
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[106] | 286 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 287 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 288 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 289 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 290 | |
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[111] | 291 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 292 | uint8_t priority0 = get_priority(state); |
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[88] | 293 | uint8_t priority1 = 2; // miss |
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[83] | 294 | |
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[88] | 295 | // is_valid = can modify local information |
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| 296 | // if context_state_ok : yes |
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[98] | 297 | // if context_state_ko : test the depth, and the priority of event |
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[88] | 298 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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[111] | 299 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or |
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| 300 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or |
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[88] | 301 | (depth1< depth0) or |
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[98] | 302 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 303 | |
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[111] | 304 | #ifdef DEBUG_TEST |
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| 305 | if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and |
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| 306 | (depth0 != depth1)) |
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| 307 | throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 308 | #endif |
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| 309 | |
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[106] | 310 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 311 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 312 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 313 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 314 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 315 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 316 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 317 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 318 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 319 | |
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[88] | 320 | if (is_valid) |
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| 321 | { |
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[105] | 322 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[111] | 323 | |
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| 324 | if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) |
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| 325 | { |
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| 326 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
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| 327 | } |
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| 328 | else |
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| 329 | { |
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| 330 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
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| 331 | |
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| 332 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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| 333 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 334 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 335 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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| 336 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 337 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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| 338 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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| 339 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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| 340 | reg_EVENT_DEPTH [i] = depth; |
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| 341 | } |
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| 342 | } |
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| 343 | } |
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| 344 | |
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| 345 | // ------------------------------------------------------------------- |
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| 346 | // -----[ BRANCH_COMPLETE ]---------------------------------------------- |
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| 347 | // ------------------------------------------------------------------- |
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| 348 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 349 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] |
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| 350 | and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 351 | { |
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| 352 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 353 | |
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[117] | 354 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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[111] | 355 | |
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[117] | 356 | context_state_t state = reg_STATE [context_id]; |
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| 357 | |
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[111] | 358 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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[117] | 359 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; |
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| 360 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; |
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| 361 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; |
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[111] | 362 | |
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| 363 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 364 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 365 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 366 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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| 367 | |
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| 368 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 369 | uint8_t priority0 = get_priority(state); |
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| 370 | uint8_t priority1 = 2; // miss |
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| 371 | |
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| 372 | // is_valid = can modify local information |
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| 373 | // if context_state_ok : yes |
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| 374 | // if context_state_ko : test the depth, and the priority of event |
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| 375 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 376 | (depth1< depth0) or |
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| 377 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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| 378 | |
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[117] | 379 | log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); |
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[111] | 380 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 381 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 382 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 383 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 384 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 385 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 386 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 387 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 388 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 389 | |
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| 390 | if (is_valid) |
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| 391 | { |
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[117] | 392 | // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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| 393 | reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; |
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| 394 | reg_EVENT_DEPTH [context_id] = depth; |
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[88] | 395 | } |
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| 396 | } |
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| 397 | |
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| 398 | // ------------------------------------------------------------------- |
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| 399 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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| 400 | // ------------------------------------------------------------------- |
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[83] | 401 | |
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[88] | 402 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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| 403 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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| 404 | { |
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[98] | 405 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
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| 406 | |
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[88] | 407 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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| 408 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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| 409 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 410 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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[106] | 411 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
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[88] | 412 | |
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[106] | 413 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 414 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 415 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 416 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 417 | |
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[88] | 418 | context_state_t state = reg_STATE [context]; |
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| 419 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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| 420 | |
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[111] | 421 | // miss_load > miss_branch > excep > spr/sync |
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| 422 | uint8_t priority0 = get_priority(state); |
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[88] | 423 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
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[83] | 424 | |
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[88] | 425 | // is_valid = can modify local information |
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| 426 | // if context_state_ok : yes |
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| 427 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 428 | |
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[88] | 429 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 430 | (depth1< depth0) or |
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[105] | 431 | ((depth1==depth0) and (priority1>=priority0))); |
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[83] | 432 | |
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[106] | 433 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 434 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 435 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 436 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 437 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 438 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 439 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 440 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 441 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 442 | |
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[88] | 443 | if (is_valid) |
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| 444 | { |
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[101] | 445 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
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| 446 | |
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[88] | 447 | // decod : |
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| 448 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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| 449 | context_state_t state_next = state; |
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| 450 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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| 451 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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[83] | 452 | |
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[88] | 453 | switch (type) |
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| 454 | { |
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| 455 | case EVENT_TYPE_EXCEPTION : |
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| 456 | { |
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[101] | 457 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
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| 458 | |
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[88] | 459 | state_next = CONTEXT_STATE_KO_EXCEP; |
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[83] | 460 | |
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[88] | 461 | break; |
---|
| 462 | } |
---|
| 463 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 464 | { |
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[101] | 465 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
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| 466 | |
---|
| 467 | // state_next = CONTEXT_STATE_KO_SPR ; |
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| 468 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
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[88] | 469 | address++; // take next address |
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[101] | 470 | // if (is_delay_slot) |
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| 471 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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[88] | 472 | break; |
---|
| 473 | } |
---|
| 474 | case EVENT_TYPE_MSYNC : |
---|
| 475 | { |
---|
[101] | 476 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
---|
| 477 | |
---|
| 478 | // state_next = CONTEXT_STATE_KO_MSYNC; |
---|
| 479 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
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[88] | 480 | address++; // take next address |
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[101] | 481 | // if (is_delay_slot) |
---|
| 482 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
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[88] | 483 | break; |
---|
| 484 | } |
---|
| 485 | case EVENT_TYPE_PSYNC : |
---|
| 486 | { |
---|
[101] | 487 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
---|
| 488 | |
---|
| 489 | // state_next = CONTEXT_STATE_KO_PSYNC; |
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| 490 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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[88] | 491 | address++; // take next address |
---|
| 492 | if (is_delay_slot) |
---|
[101] | 493 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
---|
[88] | 494 | break; |
---|
| 495 | } |
---|
| 496 | case EVENT_TYPE_CSYNC : |
---|
| 497 | { |
---|
[101] | 498 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
---|
| 499 | |
---|
| 500 | // state_next = CONTEXT_STATE_KO_CSYNC; |
---|
| 501 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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[88] | 502 | address++; // take next address |
---|
| 503 | if (is_delay_slot) |
---|
[101] | 504 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
---|
[88] | 505 | break; |
---|
| 506 | } |
---|
| 507 | case EVENT_TYPE_NONE : |
---|
[105] | 508 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 509 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 510 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 511 | default : |
---|
| 512 | { |
---|
| 513 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
---|
| 514 | } |
---|
| 515 | } |
---|
[83] | 516 | |
---|
[88] | 517 | reg_STATE [context] = state_next; |
---|
| 518 | reg_EVENT_ADDRESS [context] = address; |
---|
| 519 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
---|
| 520 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
---|
| 521 | //reg_EVENT_ADDRESS_EEAR [context] |
---|
| 522 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
---|
| 523 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
---|
| 524 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
| 525 | reg_EVENT_DEPTH [context] = depth; |
---|
| 526 | } |
---|
| 527 | } |
---|
[83] | 528 | |
---|
[88] | 529 | // ------------------------------------------------------------------- |
---|
| 530 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
---|
| 531 | // ------------------------------------------------------------------- |
---|
[83] | 532 | |
---|
[88] | 533 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
---|
| 534 | { |
---|
[98] | 535 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
---|
| 536 | |
---|
[88] | 537 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
---|
| 538 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
---|
[111] | 539 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 540 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
| 541 | // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 542 | |
---|
[111] | 543 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 544 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 545 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 546 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 547 | |
---|
[88] | 548 | context_state_t state = reg_STATE [context]; |
---|
| 549 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
---|
| 550 | |
---|
[111] | 551 | // // miss > excep > spr/sync |
---|
| 552 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or |
---|
| 553 | // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
---|
| 554 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or |
---|
| 555 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or |
---|
| 556 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or |
---|
| 557 | // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or |
---|
| 558 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
---|
| 559 | // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) |
---|
[88] | 560 | |
---|
[111] | 561 | // // is_valid = can modify local information |
---|
| 562 | // // if context_state_ok : yes |
---|
| 563 | // // if context_state_ko : test the depth, and the priority of envent |
---|
[88] | 564 | |
---|
[111] | 565 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 566 | // (depth1< depth0) or |
---|
| 567 | // ((depth1==depth0) and (priority1>=priority0))); |
---|
[88] | 568 | |
---|
[111] | 569 | // if commit send an event, also they have not yet event previous this instruction |
---|
| 570 | bool is_valid = true; |
---|
| 571 | |
---|
[106] | 572 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
[111] | 573 | // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 574 | // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 575 | // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 576 | // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 577 | // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 578 | // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 579 | // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
[106] | 580 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 581 | |
---|
[88] | 582 | if (is_valid) |
---|
| 583 | { |
---|
| 584 | // commit |
---|
| 585 | // type : exception |
---|
| 586 | context_state_t state_next = state; |
---|
| 587 | switch (type) |
---|
| 588 | { |
---|
[105] | 589 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
---|
[108] | 590 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 591 | { |
---|
| 592 | // Test if previous branch occure |
---|
[111] | 593 | switch (state) |
---|
| 594 | { |
---|
| 595 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 596 | { |
---|
| 597 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; |
---|
| 598 | break; |
---|
| 599 | } |
---|
| 600 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 601 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
---|
| 602 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 603 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
---|
| 604 | { |
---|
| 605 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
---|
| 606 | break; |
---|
| 607 | } |
---|
| 608 | default : |
---|
| 609 | { |
---|
| 610 | state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; |
---|
| 611 | break; |
---|
| 612 | } |
---|
| 613 | } |
---|
[108] | 614 | break; |
---|
| 615 | } |
---|
[105] | 616 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 617 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 618 | case EVENT_TYPE_MSYNC : |
---|
| 619 | case EVENT_TYPE_PSYNC : |
---|
| 620 | case EVENT_TYPE_CSYNC : |
---|
| 621 | case EVENT_TYPE_NONE : |
---|
| 622 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 623 | default : |
---|
| 624 | { |
---|
| 625 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
---|
| 626 | } |
---|
| 627 | } |
---|
| 628 | reg_STATE [context] = state_next; |
---|
| 629 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
---|
| 630 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
---|
[105] | 631 | reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
---|
[88] | 632 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
---|
| 633 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
---|
| 634 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
---|
[105] | 635 | reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
[88] | 636 | reg_EVENT_DEPTH [context] = depth; |
---|
| 637 | } |
---|
| 638 | } |
---|
| 639 | |
---|
| 640 | // ------------------------------------------------------------------- |
---|
| 641 | // -----[ SPR_EVENT ]------------------------------------------------- |
---|
| 642 | // ------------------------------------------------------------------- |
---|
| 643 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 644 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
---|
| 645 | { |
---|
[98] | 646 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
---|
| 647 | |
---|
[88] | 648 | // Write spr |
---|
[83] | 649 | #ifdef DEBUG_TEST |
---|
[88] | 650 | context_state_t state = reg_STATE [i]; |
---|
| 651 | |
---|
| 652 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
---|
| 653 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
[83] | 654 | #endif |
---|
[88] | 655 | |
---|
| 656 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
| 657 | } |
---|
[83] | 658 | |
---|
[88] | 659 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 660 | { |
---|
| 661 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 662 | |
---|
| 663 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 664 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 665 | } |
---|
[83] | 666 | } |
---|
| 667 | |
---|
| 668 | #if DEBUG >= DEBUG_TRACE |
---|
| 669 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 670 | { |
---|
[88] | 671 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
| 672 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
---|
| 673 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
| 674 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
| 675 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
| 676 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
| 677 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
| 678 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
| 679 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
| 680 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
[83] | 681 | } |
---|
| 682 | #endif |
---|
| 683 | |
---|
| 684 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 685 | end_cycle (); |
---|
| 686 | #endif |
---|
| 687 | |
---|
| 688 | log_end(Context_State,FUNCTION); |
---|
| 689 | }; |
---|
| 690 | |
---|
| 691 | }; // end namespace context_state |
---|
| 692 | }; // end namespace front_end |
---|
| 693 | }; // end namespace multi_front_end |
---|
| 694 | }; // end namespace core |
---|
| 695 | |
---|
| 696 | }; // end namespace behavioural |
---|
| 697 | }; // end namespace morpheo |
---|
| 698 | #endif |
---|