[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 98 2008-12-31 10:18:08Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Context_State::transition" |
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| 21 | void Context_State::transition (void) |
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| 22 | { |
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| 23 | log_begin(Context_State,FUNCTION); |
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[88] | 24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[88] | 28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 29 | { |
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| 30 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 31 | reg_INTERRUPT_ENABLE [i] = 0; |
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| 32 | } |
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[83] | 33 | } |
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| 34 | else |
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| 35 | { |
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[88] | 36 | // ------------------------------------------------------------------- |
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| 37 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 38 | // ------------------------------------------------------------------- |
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| 39 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 40 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 41 | { |
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[98] | 42 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 43 | |
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[88] | 44 | // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); |
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[83] | 45 | |
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[88] | 46 | context_state_t state = reg_STATE [i]; |
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[83] | 47 | |
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[98] | 48 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 49 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 50 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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| 51 | Tdepth_t depth_max = _param->_array_size_depth [i]; |
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| 52 | |
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| 53 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 54 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 55 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 56 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 57 | |
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[88] | 58 | // priority : miss > excep > spr/sync |
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| 59 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); |
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| 60 | uint8_t priority1 = 2; // miss |
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[83] | 61 | |
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[88] | 62 | // is_valid = can modify local information |
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| 63 | // if context_state_ok : yes |
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[98] | 64 | // if context_state_ko : test the depth, and the priority of event |
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[83] | 65 | |
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[88] | 66 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 67 | (depth1< depth0) or |
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[98] | 68 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 69 | |
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[88] | 70 | if (is_valid) |
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| 71 | { |
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[95] | 72 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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[88] | 73 | reg_STATE [i] = CONTEXT_STATE_KO_MISS; |
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[95] | 74 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 75 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 76 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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[88] | 77 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 78 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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[98] | 79 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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[95] | 80 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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[88] | 81 | reg_EVENT_DEPTH [i] = depth; |
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| 82 | } |
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| 83 | } |
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| 84 | |
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| 85 | // ------------------------------------------------------------------- |
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| 86 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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| 87 | // ------------------------------------------------------------------- |
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[83] | 88 | |
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[88] | 89 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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| 90 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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| 91 | { |
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[98] | 92 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
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| 93 | |
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[88] | 94 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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| 95 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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| 96 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 97 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 98 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 99 | |
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| 100 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 101 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 102 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 103 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 104 | |
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[88] | 105 | context_state_t state = reg_STATE [context]; |
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| 106 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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| 107 | |
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| 108 | // miss > excep > spr/sync |
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| 109 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 110 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
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[83] | 111 | |
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[88] | 112 | // is_valid = can modify local information |
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| 113 | // if context_state_ok : yes |
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| 114 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 115 | |
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[88] | 116 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 117 | (depth1< depth0) or |
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| 118 | ((depth1==depth0) and (priority1>priority0))); |
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[83] | 119 | |
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[88] | 120 | if (is_valid) |
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| 121 | { |
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| 122 | // decod : |
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| 123 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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| 124 | context_state_t state_next = state; |
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| 125 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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| 126 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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[83] | 127 | |
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[88] | 128 | switch (type) |
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| 129 | { |
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| 130 | case EVENT_TYPE_EXCEPTION : |
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| 131 | { |
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| 132 | state_next = CONTEXT_STATE_KO_EXCEP; |
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[83] | 133 | |
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[88] | 134 | break; |
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| 135 | } |
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| 136 | case EVENT_TYPE_SPR_ACCESS : |
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| 137 | { |
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| 138 | state_next = CONTEXT_STATE_KO_SPR ; |
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| 139 | address++; // take next address |
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| 140 | if (is_delay_slot) |
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| 141 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 142 | break; |
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| 143 | } |
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| 144 | case EVENT_TYPE_MSYNC : |
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| 145 | { |
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| 146 | state_next = CONTEXT_STATE_KO_MSYNC; |
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| 147 | address++; // take next address |
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| 148 | if (is_delay_slot) |
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| 149 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 150 | break; |
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| 151 | } |
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| 152 | case EVENT_TYPE_PSYNC : |
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| 153 | { |
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| 154 | state_next = CONTEXT_STATE_KO_PSYNC; |
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| 155 | address++; // take next address |
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| 156 | if (is_delay_slot) |
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| 157 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 158 | break; |
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| 159 | } |
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| 160 | case EVENT_TYPE_CSYNC : |
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| 161 | { |
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| 162 | state_next = CONTEXT_STATE_KO_CSYNC; |
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| 163 | address++; // take next address |
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| 164 | if (is_delay_slot) |
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| 165 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 166 | break; |
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| 167 | } |
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| 168 | case EVENT_TYPE_NONE : |
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| 169 | case EVENT_TYPE_MISS_SPECULATION : |
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| 170 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 171 | default : |
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| 172 | { |
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| 173 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
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| 174 | } |
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| 175 | } |
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[83] | 176 | |
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[88] | 177 | reg_STATE [context] = state_next; |
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| 178 | reg_EVENT_ADDRESS [context] = address; |
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| 179 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
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| 180 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 181 | //reg_EVENT_ADDRESS_EEAR [context] |
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| 182 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 183 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
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| 184 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 185 | reg_EVENT_DEPTH [context] = depth; |
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| 186 | } |
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| 187 | } |
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[83] | 188 | |
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[88] | 189 | // ------------------------------------------------------------------- |
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| 190 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
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| 191 | // ------------------------------------------------------------------- |
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[83] | 192 | |
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[88] | 193 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
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| 194 | { |
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[98] | 195 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
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| 196 | |
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[88] | 197 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
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| 198 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
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| 199 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 200 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 201 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 202 | |
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| 203 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 204 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 205 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 206 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 207 | |
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[88] | 208 | context_state_t state = reg_STATE [context]; |
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| 209 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
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| 210 | |
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| 211 | // miss > excep > spr/sync |
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| 212 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 213 | uint8_t priority1 = 1; // exception |
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| 214 | |
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| 215 | // is_valid = can modify local information |
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| 216 | // if context_state_ok : yes |
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| 217 | // if context_state_ko : test the depth, and the priority of envent |
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| 218 | |
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| 219 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 220 | (depth1< depth0) or |
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| 221 | ((depth1==depth0) and (priority1>priority0))); |
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| 222 | |
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| 223 | if (is_valid) |
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| 224 | { |
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| 225 | // commit |
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| 226 | // type : exception |
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| 227 | context_state_t state_next = state; |
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| 228 | switch (type) |
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| 229 | { |
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| 230 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
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| 231 | case EVENT_TYPE_SPR_ACCESS : |
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| 232 | case EVENT_TYPE_MSYNC : |
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| 233 | case EVENT_TYPE_PSYNC : |
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| 234 | case EVENT_TYPE_CSYNC : |
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| 235 | case EVENT_TYPE_NONE : |
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| 236 | case EVENT_TYPE_MISS_SPECULATION : |
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| 237 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 238 | default : |
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| 239 | { |
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| 240 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
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| 241 | } |
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| 242 | } |
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| 243 | reg_STATE [context] = state_next; |
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| 244 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
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| 245 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
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| 246 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 247 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
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| 248 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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| 249 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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| 250 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 251 | reg_EVENT_DEPTH [context] = depth; |
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| 252 | } |
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| 253 | } |
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| 254 | |
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| 255 | // ------------------------------------------------------------------- |
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| 256 | // -----[ BRANCH_COMPLETE ]------------------------------------------- |
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| 257 | // ------------------------------------------------------------------- |
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| 258 | |
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[98] | 259 | // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 260 | // if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) |
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| 261 | // { |
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| 262 | // log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
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| 263 | // if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 264 | // { |
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| 265 | // Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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| 266 | // Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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| 267 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 268 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 269 | // Tdepth_t depth_max = _param->_array_size_depth [context]; |
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[88] | 270 | |
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[98] | 271 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 272 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 273 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 274 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[88] | 275 | |
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[98] | 276 | // context_state_t state = reg_STATE [context]; |
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[88] | 277 | |
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[98] | 278 | // // miss > excep > spr/sync |
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| 279 | // uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 280 | // uint8_t priority1 = 2; // miss |
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[88] | 281 | |
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[98] | 282 | // // is_valid = can modify local information |
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| 283 | // // if context_state_ok : yes |
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| 284 | // // if context_state_ko : test the depth, and the priority of envent |
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[88] | 285 | |
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[98] | 286 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 287 | // (depth1< depth0) or |
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| 288 | // ((depth1==depth0) and (priority1>priority0))); |
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[88] | 289 | |
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[98] | 290 | // if (is_valid) |
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| 291 | // { |
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| 292 | // // commit |
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| 293 | // Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); |
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| 294 | // reg_STATE [context] = CONTEXT_STATE_KO_MISS; |
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| 295 | // reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT |
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| 296 | // reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); |
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| 297 | // reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence |
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| 298 | // //reg_EVENT_ADDRESS_EEAR [context]; |
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| 299 | // reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 300 | // reg_EVENT_IS_DELAY_SLOT [context] = take; |
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| 301 | // reg_EVENT_IS_DS_TAKE [context] = take; |
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| 302 | // reg_EVENT_DEPTH [context] = depth; |
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| 303 | // } |
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| 304 | // } |
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| 305 | // } |
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[88] | 306 | |
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| 307 | // ------------------------------------------------------------------- |
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| 308 | // -----[ EVENT ]----------------------------------------------------- |
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| 309 | // ------------------------------------------------------------------- |
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| 310 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 311 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 312 | { |
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[98] | 313 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
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[88] | 314 | // Write pc |
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| 315 | context_state_t state = reg_STATE [i]; |
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| 316 | |
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| 317 | switch (state) |
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| 318 | { |
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| 319 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 320 | { |
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| 321 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 322 | break; |
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| 323 | } |
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| 324 | case CONTEXT_STATE_KO_MISS_ADDR : |
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| 325 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 326 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 327 | { |
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| 328 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 329 | break; |
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| 330 | } |
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| 331 | default : |
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| 332 | { |
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[83] | 333 | #ifdef DEBUG_TEST |
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[88] | 334 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 335 | #endif |
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[88] | 336 | break; |
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| 337 | } |
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| 338 | } |
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| 339 | } |
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[83] | 340 | |
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[88] | 341 | // ------------------------------------------------------------------- |
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| 342 | // -----[ SPR_EVENT ]------------------------------------------------- |
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| 343 | // ------------------------------------------------------------------- |
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| 344 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 345 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
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| 346 | { |
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[98] | 347 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
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| 348 | |
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[88] | 349 | // Write spr |
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[83] | 350 | #ifdef DEBUG_TEST |
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[88] | 351 | context_state_t state = reg_STATE [i]; |
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| 352 | |
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| 353 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
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| 354 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 355 | #endif |
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[88] | 356 | |
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| 357 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 358 | } |
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[83] | 359 | |
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[88] | 360 | // ------------------------------------------------------------------- |
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| 361 | // -----[ next state ]------------------------------------------------ |
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| 362 | // ------------------------------------------------------------------- |
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| 363 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 364 | { |
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| 365 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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[83] | 366 | |
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[88] | 367 | Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 368 | Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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[83] | 369 | |
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[88] | 370 | context_state_t state = reg_STATE [i]; |
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[83] | 371 | |
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[88] | 372 | switch (state) |
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| 373 | { |
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| 374 | case CONTEXT_STATE_OK : |
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| 375 | { |
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| 376 | // nothing, wait an event |
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| 377 | break; |
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| 378 | } |
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| 379 | case CONTEXT_STATE_KO_EXCEP : |
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| 380 | { |
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| 381 | // Wait end of all instruction |
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| 382 | if (inst_all == 0) |
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| 383 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 384 | break; |
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| 385 | } |
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| 386 | case CONTEXT_STATE_KO_MISS : |
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| 387 | { |
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| 388 | // Wait end of all instruction |
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| 389 | if (inst_all == 0) |
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| 390 | state = CONTEXT_STATE_KO_MISS_ADDR; |
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| 391 | break; |
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| 392 | } |
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| 393 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 394 | { |
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| 395 | // nothing, wait the update of internal register (pc) |
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| 396 | break; |
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| 397 | } |
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| 398 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 399 | { |
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| 400 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 401 | break; |
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| 402 | } |
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| 403 | case CONTEXT_STATE_KO_MISS_ADDR : |
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| 404 | { |
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| 405 | // nothing, wait the update of internal register (pc) |
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| 406 | break; |
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| 407 | } |
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| 408 | case CONTEXT_STATE_KO_PSYNC : |
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| 409 | { |
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| 410 | // Wait end of all instruction |
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| 411 | if (inst_all == 0) |
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| 412 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 413 | state = CONTEXT_STATE_KO_PSYNC_ADDR ; |
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| 414 | break; |
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| 415 | } |
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| 416 | // case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 417 | // { |
---|
| 418 | // // nothing, wait end of flush (ifetch) |
---|
| 419 | // break; |
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| 420 | // } |
---|
| 421 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
---|
| 422 | { |
---|
| 423 | // nothing, wait the pc write |
---|
| 424 | break; |
---|
| 425 | } |
---|
| 426 | case CONTEXT_STATE_KO_CSYNC : |
---|
| 427 | { |
---|
| 428 | // Wait end of all instruction |
---|
| 429 | if (inst_all == 0) |
---|
| 430 | state = CONTEXT_STATE_KO_CSYNC_ADDR ; |
---|
| 431 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
---|
| 432 | break; |
---|
| 433 | } |
---|
| 434 | // case CONTEXT_STATE_KO_CSYNC_FLUSH : |
---|
| 435 | // { |
---|
| 436 | // // nothing, wait end of flush (all internal structure) |
---|
| 437 | // break; |
---|
| 438 | // } |
---|
| 439 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
---|
| 440 | { |
---|
| 441 | // nothing, wait the pc write |
---|
| 442 | break; |
---|
| 443 | } |
---|
| 444 | case CONTEXT_STATE_KO_MSYNC : |
---|
| 445 | { |
---|
| 446 | // Wait end of memory instruction |
---|
| 447 | if (inst_mem == 0) |
---|
| 448 | state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
---|
| 449 | break; |
---|
| 450 | } |
---|
| 451 | case CONTEXT_STATE_KO_MSYNC_ISSUE : |
---|
| 452 | { |
---|
| 453 | // Wait the msync issue |
---|
| 454 | if (inst_mem != 0) |
---|
| 455 | state = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
| 456 | break; |
---|
| 457 | } |
---|
| 458 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
---|
| 459 | { |
---|
| 460 | // Wait the end of msync |
---|
| 461 | if (inst_mem == 0) |
---|
| 462 | state = CONTEXT_STATE_OK; |
---|
| 463 | break; |
---|
| 464 | } |
---|
| 465 | case CONTEXT_STATE_KO_SPR : |
---|
| 466 | { |
---|
| 467 | // Wait end of all instruction |
---|
| 468 | if (inst_all == 0) |
---|
| 469 | state = CONTEXT_STATE_KO_SPR_ISSUE; |
---|
| 470 | break; |
---|
| 471 | } |
---|
| 472 | case CONTEXT_STATE_KO_SPR_ISSUE : |
---|
| 473 | { |
---|
| 474 | // Wait the spr_access issue |
---|
| 475 | if (inst_all != 0) |
---|
| 476 | state = CONTEXT_STATE_KO_SPR_EXEC; |
---|
| 477 | break; |
---|
| 478 | } |
---|
| 479 | case CONTEXT_STATE_KO_SPR_EXEC : |
---|
| 480 | { |
---|
| 481 | // Wait the spr_access execution |
---|
| 482 | if (inst_all == 0) |
---|
| 483 | state = CONTEXT_STATE_OK; |
---|
| 484 | break; |
---|
| 485 | } |
---|
[83] | 486 | |
---|
[88] | 487 | default : |
---|
| 488 | { |
---|
| 489 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
---|
| 490 | } |
---|
| 491 | } |
---|
| 492 | reg_STATE [i] = state; |
---|
| 493 | } |
---|
| 494 | |
---|
| 495 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 496 | { |
---|
| 497 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 498 | |
---|
| 499 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 500 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 501 | } |
---|
[83] | 502 | } |
---|
| 503 | |
---|
| 504 | #if DEBUG >= DEBUG_TRACE |
---|
| 505 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 506 | { |
---|
[88] | 507 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
| 508 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
---|
| 509 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
| 510 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
| 511 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
| 512 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
| 513 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
| 514 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
| 515 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
| 516 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
[83] | 517 | } |
---|
| 518 | #endif |
---|
| 519 | |
---|
| 520 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 521 | end_cycle (); |
---|
| 522 | #endif |
---|
| 523 | |
---|
| 524 | log_end(Context_State,FUNCTION); |
---|
| 525 | }; |
---|
| 526 | |
---|
| 527 | }; // end namespace context_state |
---|
| 528 | }; // end namespace front_end |
---|
| 529 | }; // end namespace multi_front_end |
---|
| 530 | }; // end namespace core |
---|
| 531 | |
---|
| 532 | }; // end namespace behavioural |
---|
| 533 | }; // end namespace morpheo |
---|
| 534 | #endif |
---|