[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_transition.cpp 139 2010-07-30 14:47:27Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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[110] | 10 | #include "Behavioural/include/Simulation.h" |
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[88] | 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_ooo_engine { |
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| 16 | namespace ooo_engine { |
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| 17 | namespace commit_unit { |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::transition" |
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| 21 | void Commit_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[100] | 28 | // Clear all bank |
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[115] | 29 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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[88] | 30 | { |
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[115] | 31 | while(not _rob[i].empty()) |
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| 32 | { |
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| 33 | delete _rob[i].front(); |
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| 34 | _rob[i].pop_front(); |
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| 35 | } |
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[88] | 36 | reg_BANK_PTR [i] = 0; |
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| 37 | } |
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| 38 | |
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[100] | 39 | // Reset pointer |
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[88] | 40 | reg_NUM_BANK_HEAD = 0; |
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| 41 | reg_NUM_BANK_TAIL = 0; |
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[122] | 42 | reg_NUM_PTR_TAIL = 0; |
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[88] | 43 | |
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[100] | 44 | // Reset counter |
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[88] | 45 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 46 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 47 | { |
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[109] | 48 | _nb_cycle_idle [i][j] = 0; |
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| 49 | |
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[104] | 50 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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| 51 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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| 52 | |
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[122] | 53 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 54 | // reg_EVENT_FLUSH [i][j] = false; |
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[123] | 55 | // reg_EVENT_STOP [i][j] = false; |
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[139] | 56 | // reg_EVENT_NUM_BANK [i][j] = 0; // not necessary |
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| 57 | // reg_EVENT_NUM_PTR [i][j] = 0; // not necessary |
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| 58 | // reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary |
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[128] | 59 | reg_EVENT_PACKET [i][j] = 0; // not necessary |
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[139] | 60 | reg_EVENT_DEPTH [i][j] = 0; // not necessary |
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[124] | 61 | reg_EVENT_NB_INST [i][j] = 0; |
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[122] | 62 | reg_EVENT_LAST [i][j] = false; |
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[128] | 63 | reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary |
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| 64 | reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary |
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[100] | 65 | |
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[123] | 66 | reg_EVENT_NEXT_STOP [i][j] = false; |
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[128] | 67 | reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary |
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[123] | 68 | |
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[104] | 69 | // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; |
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| 70 | reg_PC_CURRENT [i][j] = (0x100 )>>2; |
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| 71 | reg_PC_CURRENT_IS_DS [i][j] = 0; |
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| 72 | reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; |
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[105] | 73 | reg_PC_NEXT [i][j] = (0x100+4)>>2; |
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[88] | 74 | } |
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| 75 | |
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[139] | 76 | // Resert RAT_UPDATE_TABLE |
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| 77 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 78 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 79 | { |
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| 80 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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| 81 | rat_gpr_update_table [i][j][k] = false; // not necessary |
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| 82 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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| 83 | rat_spr_update_table [i][j][k] = false; // not necessary |
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| 84 | } |
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| 85 | |
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[100] | 86 | // Reset priority algorithm |
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[88] | 87 | _priority_insert->reset(); |
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| 88 | } |
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| 89 | else |
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| 90 | { |
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[109] | 91 | // Increase number idle cycle |
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| 92 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 93 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 94 | _nb_cycle_idle [i][j] ++; |
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| 95 | |
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[100] | 96 | // Compute next priority |
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[88] | 97 | _priority_insert->transition(); |
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| 98 | |
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| 99 | // =================================================================== |
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[100] | 100 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 101 | // =================================================================== |
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| 102 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 103 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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[122] | 104 | { |
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| 105 | // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty) |
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| 106 | // * no previous can_restart (trap for one) |
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| 107 | // * and decod_queue is empty |
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| 108 | // * and have an event or have a futur event |
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[123] | 109 | // if (not reg_EVENT_CAN_RESTART [i][j] and |
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| 110 | // (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and |
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| 111 | // (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT))) |
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| 112 | // reg_EVENT_CAN_RESTART [i][j] = true; |
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[122] | 113 | |
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| 114 | // Test event state |
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| 115 | switch (reg_EVENT_STATE [i][j]) |
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[104] | 116 | { |
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[122] | 117 | case COMMIT_EVENT_STATE_EVENT : |
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| 118 | { |
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| 119 | // Have an event, test if all composant have ack |
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| 120 | if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) |
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| 121 | { |
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| 122 | // A minor optimisation : test if wait_decod is previously empty. |
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[123] | 123 | // if (not reg_EVENT_CAN_RESTART [i][j]) |
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| 124 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD; |
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| 125 | // else |
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[122] | 126 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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[139] | 127 | |
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| 128 | // Reset update_table |
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| 129 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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| 130 | rat_gpr_update_table [i][j][k] = false; |
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| 131 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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| 132 | rat_spr_update_table [i][j][k] = false; |
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[122] | 133 | } |
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| 134 | |
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| 135 | break; |
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| 136 | } |
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[123] | 137 | // case COMMIT_EVENT_STATE_WAIT_DECOD : |
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| 138 | // { |
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| 139 | // // Wait flush of decod_queue. |
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| 140 | // // Test if can restart now |
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| 141 | // if (reg_EVENT_CAN_RESTART [i][j]) |
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| 142 | // { |
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| 143 | // //reg_EVENT_FLUSH [i][j] = false; |
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[122] | 144 | |
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[123] | 145 | // // A minor optimisation : test if the last element is already retire |
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| 146 | // if (not reg_EVENT_LAST [i][j]) |
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| 147 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; |
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| 148 | // else |
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| 149 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; |
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| 150 | // } |
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| 151 | // break; |
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| 152 | // } |
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[124] | 153 | |
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| 154 | // case COMMIT_EVENT_STATE_WAIT_END : |
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| 155 | // { |
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| 156 | // // Wait the flush of Re Order Buffer. |
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| 157 | // // Test if the last element is retire |
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| 158 | // if (reg_EVENT_LAST [i][j]) |
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| 159 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; |
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| 160 | |
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| 161 | // break; |
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| 162 | // } |
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| 163 | // case COMMIT_EVENT_STATE_END : |
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| 164 | // { |
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| 165 | // // Just one cycle |
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| 166 | |
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| 167 | // // flush of re order buffer is finish |
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| 168 | // reg_EVENT_LAST [i][j] = false; |
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| 169 | |
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| 170 | // if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 171 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 172 | // else |
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| 173 | // { |
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| 174 | // reg_EVENT_NEXT_STOP [i][j] = false; |
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| 175 | // reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j]; |
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| 176 | // reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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| 177 | // // reg_EVENT_STOP [i][j] = true; |
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| 178 | // reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 179 | // reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 180 | // } |
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| 181 | |
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| 182 | // break; |
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| 183 | // } |
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| 184 | |
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| 185 | |
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[122] | 186 | case COMMIT_EVENT_STATE_WAIT_END : |
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| 187 | { |
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| 188 | // Wait the flush of Re Order Buffer. |
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| 189 | // Test if the last element is retire |
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| 190 | if (reg_EVENT_LAST [i][j]) |
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[124] | 191 | { |
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| 192 | // flush of re order buffer is finish |
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| 193 | reg_EVENT_LAST [i][j] = false; |
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| 194 | |
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| 195 | if (not reg_EVENT_NEXT_STOP [i][j]) |
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| 196 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; |
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| 197 | else |
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| 198 | { |
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[139] | 199 | uint32_t next_packet = reg_EVENT_NEXT_PACKET [i][j]; |
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| 200 | |
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[124] | 201 | reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
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[123] | 202 | |
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[124] | 203 | reg_EVENT_NEXT_STOP [i][j] = false; |
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[139] | 204 | reg_EVENT_PACKET [i][j] = next_packet; |
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| 205 | // reg_EVENT_DEPTH [i][j] = _rob[next_packet].depth; |
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[124] | 206 | reg_EVENT_NB_INST [i][j] = reg_NB_INST_COMMIT_ALL [i][j]; |
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| 207 | //reg_EVENT_STOP [i][j] = true; |
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| 208 | reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
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| 209 | reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL; |
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| 210 | } |
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[123] | 211 | } |
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[122] | 212 | break; |
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| 213 | } |
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[124] | 214 | |
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[122] | 215 | //case COMMIT_EVENT_STATE_NO_EVENT : |
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[123] | 216 | //case COMMIT_EVENT_STATE_NOT_YET_EVENT : |
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[122] | 217 | default : break; |
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[104] | 218 | } |
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[122] | 219 | } |
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[100] | 220 | |
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| 221 | // =================================================================== |
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[88] | 222 | // =====[ INSERT ]==================================================== |
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| 223 | // =================================================================== |
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[122] | 224 | { |
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[124] | 225 | // for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 226 | // for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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| 227 | // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL [%d][%d] : %d",i,j,PORT_READ(in_INSERT_VAL [i][j])); |
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| 228 | |
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[122] | 229 | // variable to count instruction insert |
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| 230 | uint32_t nb_insert = 0; |
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[124] | 231 | |
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[122] | 232 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 233 | { |
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| 234 | // compute first bank number |
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| 235 | uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; |
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| 236 | |
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| 237 | if (internal_BANK_INSERT_VAL [num_bank]) |
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| 238 | { |
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| 239 | // get rename unit source and instruction. |
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| 240 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank]; |
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| 241 | uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank]; |
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| 242 | |
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| 243 | // Test if an instruction is valid |
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| 244 | // (all in_order insert combinatory is in rename_unit ) |
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| 245 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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| 246 | { |
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| 247 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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| 248 | |
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| 249 | // get information |
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| 250 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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| 251 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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| 252 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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| 253 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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| 254 | bool is_store = is_operation_memory_store(operation); |
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| 255 | |
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| 256 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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| 257 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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| 258 | |
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| 259 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 260 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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| 261 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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| 262 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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| 263 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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| 264 | |
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| 265 | // Create new entry and write information |
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| 266 | entry_t * entry = new entry_t; |
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| 267 | uint32_t ptr = reg_BANK_PTR [num_bank]; |
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[88] | 268 | |
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[122] | 269 | entry->ptr = ptr; |
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| 270 | entry->front_end_id = front_end_id; |
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| 271 | entry->context_id = context_id ; |
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| 272 | entry->rename_unit_id = x; |
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| 273 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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[137] | 274 | #ifdef STATISTICS |
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| 275 | entry->instruction = PORT_READ(in_INSERT_INSTRUCTION [x][y]); |
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| 276 | #endif |
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[122] | 277 | entry->type = type; |
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| 278 | entry->operation = operation; |
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| 279 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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| 280 | // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 281 | entry->exception = exception; |
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| 282 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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| 283 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); |
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| 284 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); |
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| 285 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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| 286 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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| 287 | #ifdef DEBUG |
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| 288 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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| 289 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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| 290 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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[137] | 291 | #endif |
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[122] | 292 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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[137] | 293 | #ifdef DEBUG |
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[122] | 294 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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| 295 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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| 296 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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| 297 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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| 298 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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| 299 | #endif |
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| 300 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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| 301 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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| 302 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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| 303 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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| 304 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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| 305 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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| 306 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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| 307 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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[128] | 308 | |
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| 309 | entry->flags = 0; // not necessary |
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[122] | 310 | entry->no_sequence = type == TYPE_BRANCH; |
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[124] | 311 | // entry->speculative = true; |
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[122] | 312 | #ifdef DEBUG |
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| 313 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 314 | #endif |
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| 315 | entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); |
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| 316 | #ifdef DEBUG |
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| 317 | entry->cycle_rob_in = simulation_cycle(); |
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| 318 | entry->cycle_commit = simulation_cycle(); |
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| 319 | #endif |
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| 320 | |
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| 321 | // Test if exception : |
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| 322 | // * yes : no execute instruction, wait ROB Head |
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| 323 | // * no : test if no_execute (== instruction is flushed) |
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| 324 | // else test type |
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| 325 | // * BRANCH : l.j -> branch is ended |
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| 326 | // other -> wait the execution end of branchment |
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| 327 | // * MEMORY : store -> wait store is at head of ROB |
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| 328 | // other -> wait end of instruction |
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| 329 | // * OTHER |
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| 330 | |
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| 331 | { |
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| 332 | if (exception == EXCEPTION_NONE) |
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| 333 | { |
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| 334 | // no_execute : l.j, l.nop, l.rfe |
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| 335 | |
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| 336 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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| 337 | |
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| 338 | switch (type) |
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| 339 | { |
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| 340 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} |
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| 341 | case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;} |
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| 342 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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| 343 | } |
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| 344 | } |
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| 345 | else |
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| 346 | { |
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| 347 | // Have an exception : wait head of ROB |
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| 348 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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| 349 | |
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| 350 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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| 351 | } |
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| 352 | } |
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[100] | 353 | |
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[122] | 354 | #ifdef STATISTICS |
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| 355 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 356 | (*_stat_nb_inst_insert [x]) ++; |
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[121] | 357 | #endif |
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[122] | 358 | |
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| 359 | // Push entry in rob |
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| 360 | _rob[num_bank].push_back(entry); |
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| 361 | |
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| 362 | // Update counter and pointer |
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| 363 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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| 364 | if (type == TYPE_MEMORY) |
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| 365 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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| 366 | |
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[88] | 367 | |
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[122] | 368 | // flush = present event or future event. |
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| 369 | // * present event = don't can restart |
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[88] | 370 | |
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[122] | 371 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
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[88] | 372 | |
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[122] | 373 | // bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
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| 374 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or |
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| 375 | // (reg_EVENT_STOP [front_end_id][context_id])); |
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| 376 | |
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| 377 | // New instruction from decod_queue. Flush if : |
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| 378 | // * future event (instruction don't need execute because they are a previous event (miss load/branch or exception)) |
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| 379 | // * or present_event |
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| 380 | // * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured. |
---|
[123] | 381 | // bool flush = ((// present event |
---|
| 382 | // ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 383 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) |
---|
| 384 | // ) or |
---|
| 385 | // futur event |
---|
| 386 | // reg_EVENT_STOP [front_end_id][context_id]) |
---|
| 387 | // // can't restart |
---|
| 388 | // and not reg_EVENT_CAN_RESTART[front_end_id][context_id] |
---|
| 389 | // ); |
---|
[100] | 390 | |
---|
[123] | 391 | // if (flush) |
---|
| 392 | // { |
---|
| 393 | // // A new invalid instruction is push in rob -> new last instruction |
---|
| 394 | // reg_EVENT_LAST [front_end_id][context_id] = false; |
---|
| 395 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; |
---|
| 396 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; |
---|
| 397 | // } |
---|
[122] | 398 | |
---|
| 399 | // Update pointer |
---|
| 400 | reg_NUM_PTR_TAIL = ptr; |
---|
| 401 | reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank; |
---|
| 402 | nb_insert ++; |
---|
[108] | 403 | } |
---|
[122] | 404 | } |
---|
| 405 | } |
---|
| 406 | // Update pointer |
---|
| 407 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank; |
---|
| 408 | } |
---|
[88] | 409 | |
---|
| 410 | // =================================================================== |
---|
| 411 | // =====[ COMMIT ]==================================================== |
---|
| 412 | // =================================================================== |
---|
| 413 | |
---|
| 414 | #ifdef STATISTICS |
---|
| 415 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 416 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
---|
| 417 | #endif |
---|
| 418 | |
---|
[122] | 419 | // For each commit instruction ... |
---|
[88] | 420 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 421 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
---|
[122] | 422 | // ... test if an instruction have finish this execution |
---|
[88] | 423 | if (internal_BANK_COMMIT_VAL [i][j]) |
---|
| 424 | { |
---|
[122] | 425 | // An instruction is executed -> Change state of this instruction |
---|
[100] | 426 | |
---|
[122] | 427 | // Get information |
---|
[88] | 428 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
---|
| 429 | |
---|
[122] | 430 | // Test if instruction is valid and is enable |
---|
| 431 | // (can be disable if this instruction is reexecute) |
---|
[88] | 432 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
---|
| 433 | { |
---|
| 434 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
---|
| 435 | |
---|
| 436 | #ifdef STATISTICS |
---|
| 437 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 438 | (*_stat_nb_inst_commit) ++; |
---|
| 439 | #endif |
---|
| 440 | |
---|
[124] | 441 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
---|
[88] | 442 | |
---|
| 443 | // find the good entry !!! |
---|
[100] | 444 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
---|
[123] | 445 | |
---|
[124] | 446 | log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr); |
---|
[100] | 447 | |
---|
| 448 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
---|
[122] | 449 | Ttype_t type = entry->type; |
---|
| 450 | Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
---|
[136] | 451 | // Tcontrol_t cancel = PORT_READ(in_COMMIT_CANCEL [x]); |
---|
[122] | 452 | |
---|
| 453 | #if 0 |
---|
| 454 | if ((type == TYPE_MEMORY) and no_sequence) |
---|
| 455 | continue; |
---|
| 456 | #endif |
---|
| 457 | |
---|
[100] | 458 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
---|
[88] | 459 | |
---|
[100] | 460 | rob_state_t state = entry->state; |
---|
| 461 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 462 | Tcontext_t context_id = entry->context_id; |
---|
[88] | 463 | |
---|
[100] | 464 | // change state : test exception_use |
---|
[88] | 465 | |
---|
[100] | 466 | bool have_exception = false; |
---|
| 467 | bool have_miss_speculation = false; |
---|
| 468 | |
---|
[122] | 469 | // Test if have an exception ... |
---|
[88] | 470 | if (exception != EXCEPTION_NONE) |
---|
[100] | 471 | { |
---|
[122] | 472 | // Test if the instruction is a load and is a miss speculation |
---|
| 473 | // (load is commit, but they have an dependence with a previous store -> need restart pipeline) |
---|
| 474 | |
---|
[100] | 475 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
---|
[88] | 476 | |
---|
[122] | 477 | // * Test if the exception generated can be trap by this exception |
---|
[100] | 478 | switch (entry->exception_use) |
---|
| 479 | { |
---|
| 480 | // Have overflow exception if bit overflow enable is set. |
---|
| 481 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
---|
| 482 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 483 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 484 | (exception == EXCEPTION_DATA_PAGE) or |
---|
| 485 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
---|
| 486 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
---|
| 487 | (exception == EXCEPTION_DATA_TLB ) or |
---|
| 488 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
---|
| 489 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
---|
| 490 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
---|
| 491 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
---|
| 492 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
---|
| 493 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
---|
| 494 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
---|
| 495 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
---|
| 496 | // Case already manage (decod stage -> in insert in ROB) |
---|
| 497 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 498 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 499 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 500 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
---|
| 501 | default : |
---|
| 502 | { |
---|
| 503 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
---|
| 504 | break; |
---|
| 505 | } |
---|
| 506 | } |
---|
| 507 | } |
---|
[124] | 508 | |
---|
| 509 | log_printf(TRACE,Commit_unit,FUNCTION," * have_exception : %d",have_exception ); |
---|
| 510 | log_printf(TRACE,Commit_unit,FUNCTION," * have_miss_speculation : %d",have_miss_speculation); |
---|
| 511 | |
---|
[100] | 512 | |
---|
[122] | 513 | // Next state depends of previous state |
---|
[100] | 514 | switch (state) |
---|
| 515 | { |
---|
[122] | 516 | // Branch : if no exception, the branchement can be completed |
---|
| 517 | case ROB_BRANCH_WAIT_END : |
---|
| 518 | { |
---|
| 519 | if (not have_exception) |
---|
| 520 | state = ROB_BRANCH_COMPLETE; |
---|
| 521 | else |
---|
| 522 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 523 | break; |
---|
| 524 | } |
---|
| 525 | // Previous event -> set state as execute |
---|
| 526 | case ROB_STORE_KO_WAIT_END : |
---|
| 527 | case ROB_EVENT_WAIT_END : |
---|
| 528 | { |
---|
| 529 | state = ROB_END_KO_SPECULATIVE; |
---|
| 530 | break; |
---|
| 531 | } |
---|
| 532 | // No previous event - Load and other instruction |
---|
| 533 | case ROB_STORE_OK_WAIT_END : |
---|
| 534 | case ROB_OTHER_WAIT_END : |
---|
| 535 | { |
---|
| 536 | if (not have_exception) |
---|
| 537 | { |
---|
| 538 | if (not have_miss_speculation) |
---|
| 539 | state = ROB_END_OK_SPECULATIVE; |
---|
| 540 | else |
---|
| 541 | state = ROB_END_LOAD_MISS_SPECULATIVE; |
---|
| 542 | } |
---|
| 543 | else |
---|
| 544 | state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 545 | break; |
---|
| 546 | } |
---|
| 547 | case ROB_STORE_WAIT_END_OK : |
---|
| 548 | { |
---|
| 549 | if (not have_exception) |
---|
| 550 | state = ROB_STORE_OK; |
---|
| 551 | else |
---|
| 552 | state = ROB_STORE_EVENT; |
---|
| 553 | break; |
---|
| 554 | } |
---|
| 555 | case ROB_STORE_WAIT_END_KO : |
---|
| 556 | { |
---|
| 557 | // if (not have_exception) |
---|
| 558 | state = ROB_STORE_KO; |
---|
| 559 | // else |
---|
| 560 | // state = ROB_END_EXCEPTION_WAIT_HEAD; |
---|
| 561 | break; |
---|
| 562 | } |
---|
| 563 | |
---|
| 564 | |
---|
[100] | 565 | default : |
---|
| 566 | { |
---|
[115] | 567 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str())); |
---|
[100] | 568 | break; |
---|
| 569 | } |
---|
| 570 | } |
---|
[88] | 571 | |
---|
[122] | 572 | // Commit an instruction ... |
---|
[123] | 573 | // Test if have an event (miss_speculation or exception) |
---|
[112] | 574 | |
---|
[123] | 575 | if (have_exception or have_miss_speculation) |
---|
[122] | 576 | { |
---|
[123] | 577 | // Two case : |
---|
| 578 | // if no previous manage event -> generate an event |
---|
| 579 | // if previous manage event -> next generate an event |
---|
| 580 | |
---|
| 581 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
| 582 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
| 583 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[124] | 584 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)// or |
---|
| 585 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END) |
---|
[123] | 586 | ); |
---|
| 587 | |
---|
[122] | 588 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i); |
---|
[123] | 589 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
[124] | 590 | |
---|
| 591 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
| 592 | log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet); |
---|
[123] | 593 | |
---|
| 594 | if (not flush) |
---|
[122] | 595 | { |
---|
[123] | 596 | bool can = true; |
---|
| 597 | // test have a previous event detected (event_stop = 1) |
---|
| 598 | // if yes, test if the actual event if "before (in order)" that the previous event |
---|
| 599 | if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
| 600 | { |
---|
| 601 | // Compare packet_id (by construction instruction is insert in order by increase packet_id) |
---|
| 602 | |
---|
| 603 | uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id]; |
---|
| 604 | uint32_t _new = packet; |
---|
| 605 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 606 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 607 | if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 608 | else can = false; |
---|
| 609 | } |
---|
| 610 | else |
---|
| 611 | reg_EVENT_PACKET [front_end_id][context_id] = packet; |
---|
| 612 | |
---|
| 613 | if (can) |
---|
| 614 | { |
---|
| 615 | // have an error, stop issue instruction |
---|
| 616 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[124] | 617 | |
---|
[139] | 618 | // reg_EVENT_DEPTH [front_end_id][context_id] = _rob[packet].depth; |
---|
[124] | 619 | reg_EVENT_NB_INST [front_end_id][context_id] = reg_NB_INST_COMMIT_ALL [front_end_id][context_id]; |
---|
| 620 | |
---|
| 621 | //reg_EVENT_STOP [front_end_id][context_id] = true; |
---|
[123] | 622 | |
---|
| 623 | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 624 | reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 625 | } |
---|
[122] | 626 | } |
---|
| 627 | else |
---|
[123] | 628 | { |
---|
| 629 | bool find = true; |
---|
[122] | 630 | |
---|
[124] | 631 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [front_end_id][context_id]); |
---|
| 632 | log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[front_end_id][context_id]); |
---|
| 633 | |
---|
[123] | 634 | // already manage an event. |
---|
| 635 | if (reg_EVENT_NEXT_STOP [front_end_id][context_id]) |
---|
| 636 | { |
---|
| 637 | // after last ? |
---|
| 638 | uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id]; |
---|
| 639 | uint32_t _new = packet; |
---|
[124] | 640 | |
---|
| 641 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 642 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 643 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 644 | |
---|
[123] | 645 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 646 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 647 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 648 | else find = false; |
---|
| 649 | |
---|
| 650 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 651 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 652 | } |
---|
| 653 | else |
---|
| 654 | { |
---|
| 655 | // after last ? |
---|
| 656 | uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]); |
---|
| 657 | uint32_t _new = packet; |
---|
[124] | 658 | |
---|
| 659 | log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top ); |
---|
| 660 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old ); |
---|
| 661 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new ); |
---|
| 662 | |
---|
[123] | 663 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 664 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 665 | if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet; |
---|
[124] | 666 | else find = false; |
---|
| 667 | |
---|
| 668 | log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old ); |
---|
| 669 | log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new ); |
---|
[123] | 670 | } |
---|
| 671 | |
---|
[124] | 672 | log_printf(TRACE,Commit_unit,FUNCTION," * find : %d",find); |
---|
| 673 | |
---|
[123] | 674 | if (find) |
---|
| 675 | reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop |
---|
| 676 | } |
---|
[122] | 677 | } |
---|
[123] | 678 | |
---|
[122] | 679 | // Update Re Order Buffer |
---|
[105] | 680 | entry->state = state; |
---|
| 681 | entry->exception = exception; |
---|
| 682 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
---|
[122] | 683 | entry->no_sequence = no_sequence; |
---|
[105] | 684 | // jalr, jr : address_dest is in register |
---|
[122] | 685 | if (( type == TYPE_BRANCH) and |
---|
[105] | 686 | (entry->operation == OPERATION_BRANCH_L_JALR) and |
---|
| 687 | (entry->read_rb)) |
---|
| 688 | entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
[111] | 689 | |
---|
| 690 | #ifdef DEBUG |
---|
[122] | 691 | entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]); |
---|
| 692 | entry->cycle_commit = simulation_cycle(); |
---|
[111] | 693 | #endif |
---|
[88] | 694 | } |
---|
| 695 | } |
---|
| 696 | |
---|
| 697 | // =================================================================== |
---|
| 698 | // =====[ RETIRE ]==================================================== |
---|
| 699 | // =================================================================== |
---|
| 700 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[110] | 701 | { |
---|
[122] | 702 | // Compute bank number |
---|
[110] | 703 | uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; |
---|
| 704 | |
---|
[122] | 705 | // Test if have an request |
---|
[110] | 706 | if (internal_BANK_RETIRE_VAL [num_bank]) |
---|
| 707 | { |
---|
[122] | 708 | // Take num instruction |
---|
[110] | 709 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; |
---|
| 710 | uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; |
---|
| 711 | |
---|
| 712 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
---|
[112] | 713 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); |
---|
[110] | 714 | |
---|
[88] | 715 | #ifdef DEBUG_TEST |
---|
[110] | 716 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
---|
| 717 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
---|
[88] | 718 | #endif |
---|
| 719 | |
---|
[122] | 720 | #ifdef STATISTICS |
---|
[139] | 721 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 722 | (*_stat_nb_inst_retire [x]) ++; |
---|
[111] | 723 | #endif |
---|
[110] | 724 | |
---|
[122] | 725 | // Read information |
---|
| 726 | entry_t * entry = _rob [num_bank].front(); |
---|
[105] | 727 | |
---|
[122] | 728 | entry->state_old = entry->state; |
---|
| 729 | entry->state = ROB_END; |
---|
[139] | 730 | |
---|
| 731 | |
---|
| 732 | // Update RAT_UPDATE_TABLE |
---|
| 733 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 734 | Tcontext_t context_id = entry->context_id ; |
---|
| 735 | |
---|
| 736 | if (entry->write_rd and internal_BANK_RETIRE_RESTORE_RD_PHY_OLD [num_bank]) |
---|
| 737 | rat_gpr_update_table [front_end_id][context_id][entry->num_reg_rd_log] = true; |
---|
| 738 | if (entry->write_re and internal_BANK_RETIRE_RESTORE_RE_PHY_OLD [num_bank]) |
---|
| 739 | rat_spr_update_table [front_end_id][context_id][entry->num_reg_re_log] = true; |
---|
[110] | 740 | } |
---|
| 741 | } |
---|
[109] | 742 | |
---|
[122] | 743 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[88] | 744 | { |
---|
[122] | 745 | // Compute bank number |
---|
| 746 | bool can_continue = false; |
---|
| 747 | uint32_t num_bank = reg_NUM_BANK_HEAD; |
---|
| 748 | |
---|
| 749 | if (not _rob [num_bank].empty ()) |
---|
| 750 | { |
---|
| 751 | entry_t * entry = _rob [num_bank].front(); |
---|
| 752 | |
---|
| 753 | if (entry->state == ROB_END) |
---|
| 754 | { |
---|
| 755 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank); |
---|
| 756 | |
---|
| 757 | can_continue = true; |
---|
[101] | 758 | |
---|
[122] | 759 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 760 | Tcontext_t context_id = entry->context_id ; |
---|
| 761 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; |
---|
| 762 | rob_state_t state = entry->state_old; |
---|
| 763 | Ttype_t type = entry->type ; |
---|
| 764 | bool retire_ok = false; |
---|
| 765 | uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
| 766 | |
---|
| 767 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); |
---|
| 768 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
---|
| 769 | log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id ); |
---|
| 770 | log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); |
---|
| 771 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
---|
| 772 | log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); |
---|
| 773 | |
---|
| 774 | // Test if the instruction is valid |
---|
| 775 | // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction) |
---|
| 776 | // (LOAD_MISS = instruction load is valid, but have make an invalid result) |
---|
| 777 | if ((state == ROB_END_OK ) or |
---|
| 778 | // (state == ROB_END_KO ) or |
---|
| 779 | (state == ROB_END_BRANCH_MISS) or |
---|
| 780 | (state == ROB_END_LOAD_MISS )// or |
---|
| 781 | // (state == ROB_END_MISS ) or |
---|
| 782 | // (state == ROB_END_EXCEPTION ) |
---|
| 783 | ) |
---|
| 784 | { |
---|
| 785 | log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); |
---|
| 786 | |
---|
| 787 | retire_ok = true; |
---|
| 788 | |
---|
| 789 | // Update PC information |
---|
| 790 | // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; |
---|
| 791 | reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; |
---|
| 792 | reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH; |
---|
| 793 | reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; |
---|
| 794 | reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); |
---|
| 795 | } |
---|
| 796 | |
---|
| 797 | // Test if have an event |
---|
| 798 | if ((state == ROB_END_BRANCH_MISS) or |
---|
| 799 | (state == ROB_END_LOAD_MISS)) |
---|
| 800 | { |
---|
| 801 | reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT; |
---|
[139] | 802 | reg_EVENT_TYPE [front_end_id][context_id] = rob_state_to_event_type(state); |
---|
[123] | 803 | // reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue |
---|
[122] | 804 | reg_EVENT_LAST [front_end_id][context_id] = false; |
---|
| 805 | // it the head ! |
---|
| 806 | reg_EVENT_PACKET [front_end_id][context_id] = packet_id; |
---|
[139] | 807 | reg_EVENT_DEPTH [front_end_id][context_id] = entry->depth; |
---|
| 808 | |
---|
[123] | 809 | // // If event is an load_miss, many instruction can be inserted. |
---|
| 810 | // // -> new last instruction |
---|
| 811 | // if (state == ROB_END_LOAD_MISS) |
---|
| 812 | // { |
---|
| 813 | // // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; |
---|
[122] | 814 | |
---|
[123] | 815 | // reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 816 | // reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; |
---|
| 817 | // } |
---|
[122] | 818 | } |
---|
| 819 | |
---|
| 820 | // Test if this instruction is the last instruction of an event |
---|
| 821 | // * need event |
---|
| 822 | // * packet id = last packet id |
---|
[124] | 823 | // for (uint32_t x=0; x<_param->_nb_front_end; x++) |
---|
| 824 | // for (uint32_t y=0; y<_param->_nb_context [x]; y++) |
---|
| 825 | // if (((reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NO_EVENT ) and |
---|
| 826 | // (reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and |
---|
| 827 | // (reg_EVENT_LAST_NUM_BANK [x][y] == num_bank ) and |
---|
| 828 | // (reg_EVENT_LAST_NUM_PTR [x][y] == entry->ptr )) |
---|
| 829 | // reg_EVENT_LAST [x][y] = true; |
---|
| 830 | |
---|
| 831 | |
---|
| 832 | if (reg_EVENT_NB_INST [front_end_id][context_id] > 0) |
---|
| 833 | { |
---|
| 834 | reg_EVENT_NB_INST [front_end_id][context_id] --; |
---|
| 835 | if (reg_EVENT_NB_INST [front_end_id][context_id] == 0) |
---|
| 836 | reg_EVENT_LAST [front_end_id][context_id] = true; |
---|
| 837 | } |
---|
| 838 | |
---|
[122] | 839 | // Update nb_inst |
---|
| 840 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
---|
| 841 | if (type == TYPE_MEMORY) |
---|
| 842 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
---|
| 843 | |
---|
| 844 | // Update pointer |
---|
| 845 | reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; |
---|
| 846 | |
---|
| 847 | // Reset watch dog timer because have transaction on retire interface |
---|
| 848 | _nb_cycle_idle [front_end_id][context_id] = 0; |
---|
| 849 | |
---|
| 850 | // Increase stop condition |
---|
| 851 | if (retire_ok) |
---|
| 852 | _simulation_nb_instruction_commited [num_thread] ++; |
---|
[88] | 853 | |
---|
[122] | 854 | #ifdef STATISTICS |
---|
| 855 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 856 | { |
---|
| 857 | if (retire_ok) |
---|
| 858 | { |
---|
[137] | 859 | uint32_t instruction = entry->instruction; |
---|
| 860 | |
---|
| 861 | (*_stat_nb_inst_retire_ok [num_thread] ) ++; |
---|
| 862 | (*_stat_nb_inst_instruction [instruction]) ++; |
---|
| 863 | (*_stat_nb_inst_type [type] ) ++; |
---|
[122] | 864 | } |
---|
| 865 | else |
---|
| 866 | (*_stat_nb_inst_retire_ko [num_thread]) ++; |
---|
| 867 | } |
---|
| 868 | #endif |
---|
[88] | 869 | |
---|
[122] | 870 | #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) |
---|
[134] | 871 | if (log_file_generate) |
---|
| 872 | { |
---|
| 873 | // log file |
---|
| 874 | instruction_log_file [num_thread] |
---|
| 875 | << "[" << simulation_cycle() << "] " |
---|
| 876 | << std::hex |
---|
| 877 | << (entry->address<<2) << " (" << (entry->address) << ") " |
---|
| 878 | << std::dec |
---|
| 879 | << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " |
---|
| 880 | << "{" << ((retire_ok)?"OK":"KO") << "} "; |
---|
| 881 | |
---|
| 882 | if ((type == TYPE_MEMORY) and is_operation_memory_load(entry->operation)) |
---|
| 883 | instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec; |
---|
| 884 | |
---|
| 885 | instruction_log_file [num_thread] << std::endl; |
---|
| 886 | } |
---|
[122] | 887 | #endif |
---|
[123] | 888 | |
---|
| 889 | // Remove entry |
---|
| 890 | delete entry; |
---|
| 891 | _rob [num_bank].pop_front(); |
---|
[122] | 892 | } |
---|
[88] | 893 | } |
---|
[122] | 894 | |
---|
| 895 | if (not can_continue) |
---|
| 896 | break; // stop scan |
---|
[88] | 897 | } |
---|
| 898 | |
---|
| 899 | // =================================================================== |
---|
[122] | 900 | // =====[ REEXECUTE ]================================================= |
---|
| 901 | // =================================================================== |
---|
| 902 | // Test if have an reexecute instruction (an store in head of rob) |
---|
| 903 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) |
---|
| 904 | if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) |
---|
| 905 | { |
---|
| 906 | log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i); |
---|
| 907 | |
---|
| 908 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i]; |
---|
| 909 | |
---|
| 910 | entry_t * entry = _rob [num_bank].front(); |
---|
| 911 | rob_state_t state = entry->state; |
---|
| 912 | |
---|
| 913 | // Change state |
---|
| 914 | switch (state) |
---|
| 915 | { |
---|
| 916 | case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; } |
---|
| 917 | case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; } |
---|
| 918 | case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; } |
---|
| 919 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
---|
| 920 | } |
---|
| 921 | |
---|
| 922 | entry->state = state; |
---|
| 923 | } |
---|
| 924 | |
---|
| 925 | // =================================================================== |
---|
[88] | 926 | // =====[ BRANCH_COMPLETE ]=========================================== |
---|
| 927 | // =================================================================== |
---|
| 928 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
---|
[122] | 929 | // Test if the prediction_unit have accept the branch complete transaction |
---|
[88] | 930 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
---|
| 931 | { |
---|
[101] | 932 | log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
| 933 | |
---|
[122] | 934 | // Read information |
---|
[88] | 935 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
---|
| 936 | |
---|
| 937 | entry_t * entry = _rob [num_bank].front(); |
---|
| 938 | |
---|
| 939 | #ifdef DEBUG_TEST |
---|
| 940 | rob_state_t state = entry->state; |
---|
| 941 | if (state != ROB_BRANCH_COMPLETE) |
---|
| 942 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
---|
| 943 | #endif |
---|
[112] | 944 | Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); |
---|
[122] | 945 | |
---|
| 946 | log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss); |
---|
[112] | 947 | |
---|
| 948 | entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; |
---|
[88] | 949 | |
---|
[122] | 950 | // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; |
---|
[112] | 951 | |
---|
[122] | 952 | // Branch_complete can be execute if |
---|
| 953 | // * no present event |
---|
| 954 | // * futur event and most not speculative that the event |
---|
| 955 | |
---|
| 956 | // Also, test if in this cycle, they have not an most recently event !!! |
---|
| 957 | if (miss) |
---|
| 958 | { |
---|
[123] | 959 | bool can = true; |
---|
[122] | 960 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
| 961 | |
---|
| 962 | // test if this packet is before previous event |
---|
[123] | 963 | if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) |
---|
[122] | 964 | { |
---|
| 965 | uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); |
---|
| 966 | uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; |
---|
| 967 | uint32_t _new = packet; |
---|
| 968 | if (_old < _top) _old = _old+_param->_size_queue; |
---|
| 969 | if (_new < _top) _new = _new+_param->_size_queue; |
---|
| 970 | if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
[123] | 971 | else can = false; |
---|
[122] | 972 | } |
---|
| 973 | else |
---|
| 974 | reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; |
---|
| 975 | |
---|
[123] | 976 | if (can) |
---|
| 977 | { |
---|
| 978 | // In all case, stop instruction flow |
---|
| 979 | reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT; |
---|
[139] | 980 | // reg_EVENT_DEPTH [entry->front_end_id][entry->context_id] = _rob[packet]._depth; |
---|
[124] | 981 | reg_EVENT_NB_INST [entry->front_end_id][entry->context_id] = reg_NB_INST_COMMIT_ALL [entry->front_end_id][entry->context_id]; |
---|
[123] | 982 | // reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; |
---|
[122] | 983 | |
---|
[123] | 984 | // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; |
---|
[122] | 985 | |
---|
[123] | 986 | reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; |
---|
| 987 | reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; |
---|
| 988 | } |
---|
[122] | 989 | } |
---|
[88] | 990 | } |
---|
| 991 | |
---|
| 992 | // =================================================================== |
---|
[100] | 993 | // =====[ UPDATE ]==================================================== |
---|
| 994 | // =================================================================== |
---|
[122] | 995 | // Update when exception or load_miss |
---|
[105] | 996 | if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) |
---|
| 997 | { |
---|
| 998 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
---|
[100] | 999 | |
---|
[122] | 1000 | // Change state |
---|
[105] | 1001 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
---|
| 1002 | |
---|
| 1003 | switch (entry->state) |
---|
| 1004 | { |
---|
| 1005 | // case ROB_END_EXCEPTION_UPDATE : |
---|
| 1006 | // { |
---|
| 1007 | // entry->state = ROB_END_KO; |
---|
| 1008 | // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
---|
| 1009 | // break; |
---|
| 1010 | // } |
---|
| 1011 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 1012 | { |
---|
| 1013 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
---|
| 1014 | |
---|
| 1015 | entry->state = ROB_END_LOAD_MISS; |
---|
| 1016 | break; |
---|
| 1017 | } |
---|
| 1018 | default : |
---|
| 1019 | { |
---|
| 1020 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); |
---|
| 1021 | break; |
---|
| 1022 | } |
---|
| 1023 | } |
---|
| 1024 | } |
---|
| 1025 | |
---|
[100] | 1026 | // =================================================================== |
---|
[88] | 1027 | // =====[ EVENT ]===================================================== |
---|
| 1028 | // =================================================================== |
---|
[108] | 1029 | // for (uint32_t i=0; i < _param->_nb_front_end; ++i) |
---|
| 1030 | // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) |
---|
| 1031 | // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) |
---|
| 1032 | // { |
---|
| 1033 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); |
---|
[88] | 1034 | |
---|
[108] | 1035 | // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); |
---|
| 1036 | // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? |
---|
| 1037 | // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); |
---|
| 1038 | // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); |
---|
| 1039 | // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); |
---|
| 1040 | // } |
---|
| 1041 | |
---|
[88] | 1042 | // =================================================================== |
---|
| 1043 | // =====[ DEPTH - HEAD ]============================================== |
---|
| 1044 | // =================================================================== |
---|
| 1045 | |
---|
[122] | 1046 | { |
---|
[124] | 1047 | bool can_continue [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1048 | uint32_t event_nb_inst [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1049 | bool is_speculative [_param->_nb_front_end][_param->_max_nb_context]; |
---|
[122] | 1050 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1051 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[124] | 1052 | { |
---|
| 1053 | event_nb_inst [i][j] = 0; |
---|
| 1054 | is_speculative[i][j] = false; |
---|
| 1055 | can_continue [i][j] = (((reg_EVENT_NB_INST [i][j] == 0) or |
---|
| 1056 | ( event_nb_inst [i][j] < reg_EVENT_NB_INST [i][j])) and |
---|
| 1057 | not reg_EVENT_LAST [i][j]); |
---|
| 1058 | } |
---|
[122] | 1059 | |
---|
| 1060 | // Read all instruction of all top bank |
---|
| 1061 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1062 | { |
---|
| 1063 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[88] | 1064 | |
---|
[122] | 1065 | // Test if have an instruction |
---|
| 1066 | if (not _rob[num_bank].empty()) |
---|
| 1067 | { |
---|
| 1068 | // Scan all instruction in windows and test if instruction is speculative |
---|
| 1069 | entry_t * entry = _rob [num_bank].front(); |
---|
[124] | 1070 | |
---|
| 1071 | uint32_t num_packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
---|
[122] | 1072 | Tcontext_t front_end_id = entry->front_end_id; |
---|
| 1073 | Tcontext_t context_id = entry->context_id ; |
---|
[124] | 1074 | |
---|
| 1075 | log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,num_packet); |
---|
| 1076 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
---|
| 1077 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
---|
| 1078 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [front_end_id][context_id]); |
---|
| 1079 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NB_INST : %d",reg_EVENT_NB_INST [front_end_id][context_id]); |
---|
| 1080 | log_printf(TRACE,Commit_unit,FUNCTION," * event_nb_inst : %d", event_nb_inst [front_end_id][context_id]); |
---|
[122] | 1081 | |
---|
| 1082 | // scan while last event instruction is not retire |
---|
[124] | 1083 | if (can_continue [front_end_id][context_id]) |
---|
[122] | 1084 | { |
---|
| 1085 | // Read information |
---|
| 1086 | rob_state_t state = entry->state; |
---|
[137] | 1087 | // Tdepth_t depth = entry->depth; |
---|
[122] | 1088 | |
---|
[137] | 1089 | // Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
---|
| 1090 | // Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
---|
| 1091 | // Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
---|
[122] | 1092 | |
---|
| 1093 | // is a valid instruction ? |
---|
| 1094 | // If DEPTH_CURRENT : |
---|
| 1095 | // equal at DEPTH_MIN -> not speculative |
---|
| 1096 | // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss |
---|
| 1097 | // include ]DEPTH_MIN:DEPTH_MAX] -> speculative |
---|
| 1098 | |
---|
| 1099 | // All case |
---|
| 1100 | // ....... min ...X... max ....... OK |
---|
| 1101 | // ....... min ....... max ...X... KO |
---|
| 1102 | // ...X... min ....... max ....... KO |
---|
| 1103 | // ....... max ....... min ...X... OK |
---|
| 1104 | // ...X... max ....... min ....... OK |
---|
| 1105 | // ....... max ...X... min ....... KO |
---|
| 1106 | |
---|
| 1107 | bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or |
---|
[123] | 1108 | // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or |
---|
[122] | 1109 | (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)); |
---|
[124] | 1110 | bool speculative = is_speculative [front_end_id][context_id]; |
---|
| 1111 | |
---|
| 1112 | // bool speculative = entry->speculative and not (depth == depth_min); |
---|
| 1113 | // Tcontrol_t is_valid = ((not speculative or |
---|
| 1114 | // (speculative and (depth_full or // all is valid |
---|
| 1115 | // ((depth_min <= depth_max)? // test if depth is overflow |
---|
| 1116 | // ((depth >= depth_min) and (depth <=depth_max)): |
---|
| 1117 | // ((depth >= depth_min) or (depth <=depth_max)))))) |
---|
| 1118 | // and not flush); // no event |
---|
| 1119 | |
---|
| 1120 | Tcontrol_t is_valid = not flush; |
---|
| 1121 | |
---|
| 1122 | |
---|
[122] | 1123 | //Tcontrol_t is_valid = ((depth == depth_min) and not flush); |
---|
| 1124 | |
---|
| 1125 | |
---|
| 1126 | log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); |
---|
[137] | 1127 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); |
---|
| 1128 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); |
---|
| 1129 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); |
---|
| 1130 | // log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); |
---|
[122] | 1131 | log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative); |
---|
| 1132 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
[124] | 1133 | log_printf(TRACE,Commit_unit,FUNCTION," * state (before) : %s",toString(state).c_str()); |
---|
| 1134 | |
---|
| 1135 | // //------------------------------------------------------ |
---|
| 1136 | // // Event ? |
---|
| 1137 | // //------------------------------------------------------ |
---|
| 1138 | |
---|
| 1139 | // if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1140 | // (reg_EVENT_PACKET [front_end_id][context_id] == num_packet)) |
---|
| 1141 | // { |
---|
| 1142 | // switch (state) |
---|
| 1143 | // { |
---|
| 1144 | // case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1145 | // case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1146 | // case ROB_END_BRANCH_MISS : |
---|
| 1147 | // case ROB_END_LOAD_MISS : |
---|
| 1148 | // case ROB_END : |
---|
| 1149 | // {break;} |
---|
| 1150 | // default : |
---|
| 1151 | // { |
---|
| 1152 | // throw ERRORMORPHEO(FUNCTION,toString(_("Head [%d] : invalid state (%s)"),num_packet,toString(state).c_str())); |
---|
| 1153 | // break; |
---|
| 1154 | // } |
---|
| 1155 | // } |
---|
| 1156 | // } |
---|
[122] | 1157 | |
---|
| 1158 | //------------------------------------------------------ |
---|
| 1159 | // test if instruction is miss speculative |
---|
| 1160 | //------------------------------------------------------ |
---|
| 1161 | if (not is_valid) |
---|
| 1162 | { |
---|
| 1163 | // Change state |
---|
| 1164 | switch (state) |
---|
| 1165 | { |
---|
| 1166 | case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
| 1167 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
---|
| 1168 | case ROB_END_BRANCH_MISS : |
---|
| 1169 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
[124] | 1170 | case ROB_END_LOAD_MISS : |
---|
[122] | 1171 | case ROB_END_LOAD_MISS_UPDATE : |
---|
| 1172 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1173 | case ROB_STORE_OK : {state = ROB_STORE_KO ; break;} |
---|
| 1174 | case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;} |
---|
| 1175 | case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;} |
---|
| 1176 | case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
| 1177 | case ROB_END_OK : |
---|
| 1178 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1179 | case ROB_END_KO : |
---|
| 1180 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
| 1181 | case ROB_END_EXCEPTION_UPDATE : |
---|
| 1182 | case ROB_END_EXCEPTION : |
---|
| 1183 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
---|
| 1184 | |
---|
| 1185 | // don't change state -> wait |
---|
| 1186 | case ROB_STORE_WAIT_END_KO : {break;} |
---|
| 1187 | case ROB_STORE_KO : {break;} |
---|
| 1188 | case ROB_STORE_KO_WAIT_END : {break;} |
---|
| 1189 | case ROB_STORE_EVENT : {break;} |
---|
| 1190 | case ROB_EVENT_WAIT_END : {break;} |
---|
| 1191 | case ROB_END_MISS : {break;} |
---|
| 1192 | case ROB_END : {break;} |
---|
| 1193 | |
---|
| 1194 | // can't have miss speculation -> invalid state |
---|
| 1195 | default : |
---|
| 1196 | { |
---|
| 1197 | throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); |
---|
| 1198 | break; |
---|
| 1199 | } |
---|
| 1200 | } |
---|
| 1201 | } |
---|
[124] | 1202 | |
---|
| 1203 | //------------------------------------------------------ |
---|
| 1204 | // test if instruction is branch not finish |
---|
| 1205 | //------------------------------------------------------ |
---|
| 1206 | switch (state) |
---|
| 1207 | { |
---|
| 1208 | case ROB_BRANCH_WAIT_END : |
---|
| 1209 | case ROB_BRANCH_COMPLETE : |
---|
| 1210 | { |
---|
| 1211 | is_speculative [front_end_id][context_id] = true; |
---|
| 1212 | break; |
---|
| 1213 | } |
---|
| 1214 | default : break; |
---|
| 1215 | } |
---|
[122] | 1216 | |
---|
| 1217 | //------------------------------------------------------ |
---|
| 1218 | // test if instruction is not speculative |
---|
| 1219 | //------------------------------------------------------ |
---|
[124] | 1220 | // entry->speculative = speculative; |
---|
[122] | 1221 | // if (entry->depth == depth_min) |
---|
| 1222 | // test if instruction is speculative (depth != depth_min) |
---|
| 1223 | if (not speculative) |
---|
| 1224 | { |
---|
| 1225 | switch (state) |
---|
| 1226 | { |
---|
| 1227 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
---|
| 1228 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
---|
| 1229 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
| 1230 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
| 1231 | default : {break;} // else, no change |
---|
| 1232 | } |
---|
| 1233 | } |
---|
| 1234 | |
---|
| 1235 | //------------------------------------------------------ |
---|
| 1236 | // test if instruction wait head and is the top of rob |
---|
| 1237 | //------------------------------------------------------ |
---|
| 1238 | // TODO : retire OOO |
---|
| 1239 | if (i == 0) |
---|
| 1240 | { |
---|
| 1241 | switch (state) |
---|
| 1242 | { |
---|
| 1243 | // case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
---|
| 1244 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} |
---|
| 1245 | default : {break;} // else, no change |
---|
| 1246 | } |
---|
| 1247 | } |
---|
| 1248 | |
---|
| 1249 | // Write new state |
---|
| 1250 | entry->state = state; |
---|
[124] | 1251 | |
---|
| 1252 | log_printf(TRACE,Commit_unit,FUNCTION," * state (after ) : %s",toString(state).c_str()); |
---|
[122] | 1253 | |
---|
[124] | 1254 | // log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!"); |
---|
[122] | 1255 | |
---|
[124] | 1256 | event_nb_inst [front_end_id][context_id] ++; |
---|
| 1257 | |
---|
| 1258 | // stop if : |
---|
| 1259 | // * begin event |
---|
| 1260 | // * end event |
---|
| 1261 | if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
---|
| 1262 | (reg_EVENT_PACKET[front_end_id][context_id] == num_packet)) or |
---|
| 1263 | ((reg_EVENT_NB_INST [front_end_id][context_id] > 0) and |
---|
| 1264 | ( event_nb_inst [front_end_id][context_id] >= reg_EVENT_NB_INST [front_end_id][context_id]))) |
---|
| 1265 | can_continue [front_end_id][context_id] = false; |
---|
[122] | 1266 | } |
---|
| 1267 | } |
---|
| 1268 | } |
---|
| 1269 | } |
---|
[105] | 1270 | |
---|
| 1271 | |
---|
[101] | 1272 | |
---|
[122] | 1273 | #ifdef STATISTICS |
---|
[124] | 1274 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 1275 | { |
---|
| 1276 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
| 1277 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
---|
| 1278 | |
---|
| 1279 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1280 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1281 | { |
---|
| 1282 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [i][j]; |
---|
| 1283 | |
---|
| 1284 | switch (reg_EVENT_STATE [i][j]) |
---|
| 1285 | { |
---|
| 1286 | case COMMIT_EVENT_STATE_NO_EVENT : (*_stat_nb_cycle_state_no_event [num_thread])++; break; |
---|
| 1287 | case COMMIT_EVENT_STATE_NOT_YET_EVENT : (*_stat_nb_cycle_state_not_yet_event [num_thread])++; break; |
---|
| 1288 | case COMMIT_EVENT_STATE_EVENT : (*_stat_nb_cycle_state_event [num_thread])++; break; |
---|
| 1289 | case COMMIT_EVENT_STATE_WAIT_END : (*_stat_nb_cycle_state_wait_end [num_thread])++; break; |
---|
| 1290 | } |
---|
| 1291 | } |
---|
| 1292 | } |
---|
[122] | 1293 | #endif |
---|
[88] | 1294 | } |
---|
| 1295 | |
---|
| 1296 | // =================================================================== |
---|
| 1297 | // =====[ OTHER ]===================================================== |
---|
| 1298 | // =================================================================== |
---|
| 1299 | |
---|
[108] | 1300 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) |
---|
| 1301 | { |
---|
| 1302 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
---|
| 1303 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
---|
| 1304 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
---|
[122] | 1305 | log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL ); |
---|
[108] | 1306 | |
---|
| 1307 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1308 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1309 | { |
---|
[110] | 1310 | log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); |
---|
[122] | 1311 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str()); |
---|
| 1312 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); |
---|
[123] | 1313 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); |
---|
| 1314 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); |
---|
| 1315 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); |
---|
[139] | 1316 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str()); |
---|
[124] | 1317 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); |
---|
| 1318 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]); |
---|
| 1319 | log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : all : %d - mem : %d - event : %d",reg_NB_INST_COMMIT_ALL[i][j], reg_NB_INST_COMMIT_MEM[i][j],reg_EVENT_NB_INST[i][j]); |
---|
| 1320 | log_printf(TRACE,Commit_unit,FUNCTION," * PC : %.8x (%.8x) - %d %d - %.8x (%.8x)",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j],reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); |
---|
[108] | 1321 | } |
---|
| 1322 | |
---|
[122] | 1323 | std::list<entry_t*>::iterator iter [_param->_nb_bank]; |
---|
[108] | 1324 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[104] | 1325 | { |
---|
[108] | 1326 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
[122] | 1327 | // log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); |
---|
[108] | 1328 | |
---|
[122] | 1329 | iter [num_bank] = _rob[num_bank].begin(); |
---|
| 1330 | } |
---|
| 1331 | |
---|
[123] | 1332 | bool all_empty = false; |
---|
| 1333 | uint32_t nb_write_rd = 0; |
---|
| 1334 | uint32_t nb_write_re = 0; |
---|
| 1335 | |
---|
[122] | 1336 | while (not all_empty) |
---|
| 1337 | { |
---|
| 1338 | all_empty = true; |
---|
[108] | 1339 | |
---|
[122] | 1340 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
[108] | 1341 | { |
---|
[122] | 1342 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
| 1343 | |
---|
| 1344 | std::list<entry_t*>::iterator it = iter[num_bank]; |
---|
| 1345 | if (it != _rob[num_bank].end()) |
---|
| 1346 | { |
---|
| 1347 | all_empty = false; |
---|
| 1348 | |
---|
[123] | 1349 | nb_write_rd += ((*it)->write_rd)?1:0; |
---|
| 1350 | nb_write_re += ((*it)->write_re)?1:0; |
---|
| 1351 | |
---|
[124] | 1352 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", |
---|
[122] | 1353 | num_bank , |
---|
| 1354 | (*it)->ptr , |
---|
| 1355 | (*it)->front_end_id , |
---|
| 1356 | (*it)->context_id , |
---|
| 1357 | (*it)->rename_unit_id , |
---|
| 1358 | (*it)->depth , |
---|
| 1359 | (*it)->type , |
---|
| 1360 | (*it)->operation , |
---|
| 1361 | (*it)->is_delay_slot , |
---|
| 1362 | (*it)->use_store_queue , |
---|
| 1363 | (*it)->store_queue_ptr_write , |
---|
| 1364 | (*it)->use_load_queue , |
---|
| 1365 | (*it)->load_queue_ptr_write , |
---|
| 1366 | toString((*it)->state).c_str() ); |
---|
[124] | 1367 | log_printf(TRACE,Commit_unit,FUNCTION," (%.4d) %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
---|
| 1368 | (((*it)->ptr << _param->_shift_num_slot) | num_bank), |
---|
[122] | 1369 | (*it)->read_ra , |
---|
| 1370 | (*it)->num_reg_ra_log , |
---|
| 1371 | (*it)->num_reg_ra_phy , |
---|
| 1372 | (*it)->read_rb , |
---|
| 1373 | (*it)->num_reg_rb_log , |
---|
| 1374 | (*it)->num_reg_rb_phy , |
---|
| 1375 | (*it)->read_rc , |
---|
| 1376 | (*it)->num_reg_rc_log , |
---|
| 1377 | (*it)->num_reg_rc_phy , |
---|
| 1378 | (*it)->write_rd , |
---|
| 1379 | (*it)->num_reg_rd_log , |
---|
| 1380 | (*it)->num_reg_rd_phy_old , |
---|
| 1381 | (*it)->num_reg_rd_phy_new , |
---|
| 1382 | (*it)->write_re , |
---|
| 1383 | (*it)->num_reg_re_log , |
---|
| 1384 | (*it)->num_reg_re_phy_old , |
---|
| 1385 | (*it)->num_reg_re_phy_new ); |
---|
| 1386 | |
---|
[124] | 1387 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", |
---|
[122] | 1388 | (*it)->exception_use , |
---|
| 1389 | (*it)->exception , |
---|
| 1390 | (*it)->flags , |
---|
| 1391 | (*it)->no_sequence , |
---|
[128] | 1392 | // (*it)->speculative , |
---|
[122] | 1393 | (*it)->address , |
---|
| 1394 | (*it)->address<<2 , |
---|
| 1395 | (*it)->address_next , |
---|
| 1396 | (*it)->address_next<<2 |
---|
| 1397 | ); |
---|
| 1398 | |
---|
| 1399 | iter [num_bank] ++; |
---|
| 1400 | } |
---|
[108] | 1401 | } |
---|
[104] | 1402 | } |
---|
[123] | 1403 | |
---|
[139] | 1404 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT Update Table"); |
---|
| 1405 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
---|
| 1406 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
---|
| 1407 | { |
---|
| 1408 | { |
---|
| 1409 | std::string str = ""; |
---|
| 1410 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
---|
| 1411 | str+=toString("%.1d ",rat_gpr_update_table[i][j][k]); |
---|
| 1412 | |
---|
| 1413 | log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str()); |
---|
| 1414 | } |
---|
| 1415 | |
---|
| 1416 | { |
---|
| 1417 | std::string str = ""; |
---|
| 1418 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
---|
| 1419 | str+=toString("%.1d ",rat_spr_update_table[i][j][k]); |
---|
| 1420 | |
---|
| 1421 | log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str()); |
---|
| 1422 | } |
---|
| 1423 | } |
---|
| 1424 | |
---|
[123] | 1425 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd); |
---|
| 1426 | log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re); |
---|
[108] | 1427 | } |
---|
[88] | 1428 | #endif |
---|
| 1429 | |
---|
[108] | 1430 | #ifdef DEBUG_TEST |
---|
| 1431 | { |
---|
| 1432 | uint32_t x=reg_NUM_BANK_HEAD; |
---|
| 1433 | if (not _rob[x].empty()) |
---|
| 1434 | { |
---|
| 1435 | entry_t * entry = _rob [x].front(); |
---|
[97] | 1436 | |
---|
[108] | 1437 | if (false |
---|
| 1438 | // or (entry->state == ROB_EMPTY ) |
---|
| 1439 | // or (entry->state == ROB_BRANCH_WAIT_END ) |
---|
| 1440 | // or (entry->state == ROB_BRANCH_COMPLETE ) |
---|
| 1441 | // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) |
---|
| 1442 | // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) |
---|
| 1443 | // or (entry->state == ROB_STORE_HEAD_OK ) |
---|
| 1444 | // or (entry->state == ROB_STORE_HEAD_KO ) |
---|
| 1445 | // or (entry->state == ROB_OTHER_WAIT_END ) |
---|
[112] | 1446 | // or (entry->state == ROB_EVENT_WAIT_END ) |
---|
[108] | 1447 | // or (entry->state == ROB_END_OK_SPECULATIVE ) |
---|
| 1448 | or (entry->state == ROB_END_OK ) |
---|
| 1449 | // or (entry->state == ROB_END_KO_SPECULATIVE ) |
---|
| 1450 | // or (entry->state == ROB_END_KO ) |
---|
| 1451 | // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) |
---|
| 1452 | or (entry->state == ROB_END_BRANCH_MISS ) |
---|
| 1453 | // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) |
---|
| 1454 | // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) |
---|
| 1455 | or (entry->state == ROB_END_LOAD_MISS ) |
---|
| 1456 | // or (entry->state == ROB_END_MISS ) |
---|
| 1457 | // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) |
---|
| 1458 | // or (entry->state == ROB_END_EXCEPTION_UPDATE ) |
---|
| 1459 | // or (entry->state == ROB_END_EXCEPTION ) |
---|
| 1460 | ) |
---|
| 1461 | if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) |
---|
[122] | 1462 | throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"), |
---|
[108] | 1463 | entry->address, |
---|
| 1464 | entry->front_end_id, |
---|
| 1465 | entry->context_id, |
---|
| 1466 | reg_PC_CURRENT[entry->front_end_id][entry->context_id])); |
---|
| 1467 | } |
---|
| 1468 | } |
---|
[124] | 1469 | { |
---|
| 1470 | uint32_t NB_INST [_param->_nb_front_end][_param->_max_nb_context]; |
---|
| 1471 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1472 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1473 | NB_INST [i][j] = 0; //reg_EVENT_NB_INST [i][j]; |
---|
| 1474 | |
---|
| 1475 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
---|
| 1476 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
---|
| 1477 | it!=_rob [i].end(); |
---|
| 1478 | ++it) |
---|
| 1479 | NB_INST [(*it)->front_end_id][(*it)->context_id] ++; |
---|
| 1480 | |
---|
| 1481 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1482 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
| 1483 | if (NB_INST [i][j] != reg_NB_INST_COMMIT_ALL [i][j]) |
---|
| 1484 | throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] have not the good nb_inst (%d in rob, %d in register).\n"),i,j,NB_INST[i][j], reg_NB_INST_COMMIT_ALL [i][j])); |
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| 1485 | } |
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[108] | 1486 | #endif |
---|
[88] | 1487 | |
---|
| 1488 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 1489 | end_cycle (); |
---|
| 1490 | #endif |
---|
| 1491 | |
---|
[109] | 1492 | // Stop Condition |
---|
| 1493 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 1494 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
[110] | 1495 | if (_nb_cycle_idle [i][j] >= debug_idle_cycle) |
---|
| 1496 | throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j])); |
---|
[109] | 1497 | |
---|
[88] | 1498 | log_end(Commit_unit,FUNCTION); |
---|
| 1499 | }; |
---|
| 1500 | |
---|
| 1501 | }; // end namespace commit_unit |
---|
| 1502 | }; // end namespace ooo_engine |
---|
| 1503 | }; // end namespace multi_ooo_engine |
---|
| 1504 | }; // end namespace core |
---|
| 1505 | |
---|
| 1506 | }; // end namespace behavioural |
---|
| 1507 | }; // end namespace morpheo |
---|
| 1508 | #endif |
---|