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Makefile.Synthesis @ 121

Last change on this file since 121 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 5.5 KB

Rev	Line
[2]	1	#
	2	# $Id: Makefile.Synthesis 117 2009-05-16 14:42:39Z rosiere $
	3	#
[53]	4	# [ Description ]
[2]	5	#
	6	# Makefile
	7	#
	8
[53]	9	#-----[ Variables ]----------------------------------------
[2]	10
	11	DIR_VHDL = .
[113]	12	WORK_NAME = work
[117]	13	DIR_WORK = $(DIR_TMP)/$(WORK_NAME)
[2]	14
	15	FPGA_CFG_FILE_LOCAL = mkf.info
	16	FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural
	17	FPGA_CFG_FILE_GLOBAL = configure.mkf
	18
[19]	19	FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
	20	$(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg))
	21
	22	FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
	23	$(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
[113]	24
	25
[53]	26	#-----[ Rules ]--------------------------------------------
[62]	27	.PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log
[2]	28
[113]	29	vhdl : $(EXEC_LOG)
[48]	30	@\
[113]	31	$(MAKE) vhdl_package; \
	32	$(MAKE) vhdl_entity; \
	33	$(MAKE) vhdl_testbench
	34
	35	vhdl_package : $(DIR_WORK)
	36	@\
[15]	37	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \
[2]	38	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
[113]	39	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
	40
	41	vhdl_testbench : $(DIR_WORK)
	42	@\
[48]	43	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
[2]	44	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
[113]	45	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
[2]	46
[113]	47	vhdl_entity : $(DIR_WORK)
	48	@\
	49	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
	50	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
	51	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \
[103]	52
[113]	53	#list :
	54	# @\
	55	# declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
	56	# for file1 in $${vhdl_files[*]}; do \
	57	# declare x=$$(basename $${file1} .vhdl); \
	58	# declare -i count_x=$($(ECHO) $${x} \| ${WC} -m); \
	59	# for file2 in $${vhdl_files[*]}; do \
	60	# if $(TEST) "$${file1}" != "$${file2}"; then\
	61	# declare y=$$(basename $${file2} .vhdl); \
	62	# declare -i count_y=$($(ECHO) $${y} \| ${WC} -m); \
	63	# if $(TEST) $${count_x} -gt $${count_y}; then \
	64	# break; \
	65	# fi; \
	66	# $(ECHO) $${x}; \
	67	# fi; \
	68	# done; \
	69	# done;
	70
[62]	71	sim : vhdl
[48]	72	@\
[15]	73	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
[62]	74	declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \
[113]	75	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
[2]	76
[62]	77	fpga : sim
[48]	78	@\
	79	$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \
	80	$(ECHO) "files :::::::: $(FPGA_FILES)"; \
	81	for file in $(FPGA_FILES); do \
[2]	82	declare -a files=($$($(LS) $$file*.vhdl\|$(GREP_NOT) "(_Testbench\.)")); \
	83	$(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \
	84	$(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \
	85	$(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \
	86	$(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \
	87	$(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \
[48]	88	done; \
[96]	89	($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \
[113]	90	$(MAKE) -k $(FPGA_LOG_FILES);
[2]	91
	92	$(DIR_LOG)/%.fpga.log :
[48]	93	@\
	94	$(ECHO) "Synthetis on FPGA : $*"; \
	95	$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@;
[2]	96
[117]	97	$(DIR_WORK) :
[48]	98	@\
[113]	99	$(ECHO) "Create work-space : $@"; \
[117]	100	mkdir -p $@; \
[113]	101	$(MODELTECH_VLIB) $@; \
	102	$(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR); \
	103	if $(TEST) $${?} -ne 0; then \
	104	$(ECHO) "Xilinx corelib must be compiled to simulation tools"; \
	105	$(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \
	106	fi;
[2]	107
[62]	108	$(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
[48]	109	@\
	110	$(ECHO) "VHDL's Simulation : $*"; \
	111	$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* \|$(UPPERtoLOWER)`" &> $@; \
[42]	112	declare -i count=`$(GREP) -ch "Test OK" $@`; \
	113	if $(TEST) $$count -ne 0; \
[2]	114	then echo " $* ... OK"; \
	115	else echo " $* ... KO"; exit 1; \
	116	fi;
	117
	118	$(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl
[48]	119	@\
	120	$(ECHO) "VHDL's Compilation : $*"; \
[113]	121	$(MODELTECH_VCOM) -work $(DIR_WORK) $< &> $@;
[2]	122
	123	synthesis_clean :
[48]	124	@\
	125	if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \
[113]	126	$(RM) $(DIR_WORK) transcript Makefile.mkf wlf modelsim.ini;
[2]	127
[88]	128	synthesis_clean_all : synthesis_clean
	129
[2]	130	synthesis_help :
[48]	131	@\
[53]	132	$(ECHO) " -----[ Synthesis ]----------------------------------";\
[48]	133	$(ECHO) "";\
	134	$(ECHO) " * vhdl : compile all vhdl's file";\
[62]	135	$(ECHO) " * sim : simulate all testbench's file";\
[48]	136	$(ECHO) " * fpga : synthetis with fpga's tools";\
	137	$(ECHO) "";

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