- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine
- Files:
-
- 79 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r110 r112 153 153 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 154 154 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); 155 ALLOC _SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t );156 ALLOC _SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t );157 ALLOC _SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t );158 ALLOC _SC_SIGNAL(out_UPDATE_FRONT_END_ID ,"out_UPDATE_FRONT_END_ID ",Tcontext_t );159 ALLOC _SC_SIGNAL(out_UPDATE_DEPTH ,"out_UPDATE_DEPTH ",Tdepth_t );160 ALLOC _SC_SIGNAL(out_UPDATE_TYPE ,"out_UPDATE_TYPE ",Tevent_type_t );161 ALLOC _SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t );162 ALLOC _SC_SIGNAL(out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t );163 ALLOC _SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t );164 ALLOC _SC_SIGNAL(out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t );165 ALLOC _SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t );166 ALLOC _SC_SIGNAL(out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t );155 ALLOC0_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); 156 ALLOC0_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ); 157 ALLOC0_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ); 158 ALLOC0_SC_SIGNAL(out_UPDATE_FRONT_END_ID ,"out_UPDATE_FRONT_END_ID ",Tcontext_t ); 159 ALLOC0_SC_SIGNAL(out_UPDATE_DEPTH ,"out_UPDATE_DEPTH ",Tdepth_t ); 160 ALLOC0_SC_SIGNAL(out_UPDATE_TYPE ,"out_UPDATE_TYPE ",Tevent_type_t ); 161 ALLOC0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); 162 ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); 163 ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t ); 164 ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); 165 ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); 166 ALLOC0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t ); 167 167 168 168 ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); … … 304 304 INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 305 305 INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 306 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_VAL );307 INSTANCE _SC_SIGNAL(_Commit_unit, in_UPDATE_ACK );306 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_VAL ); 307 INSTANCE0_SC_SIGNAL(_Commit_unit, in_UPDATE_ACK ); 308 308 if (_param->_have_port_context_id) 309 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_CONTEXT_ID );309 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_CONTEXT_ID ); 310 310 if (_param->_have_port_front_end_id) 311 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_FRONT_END_ID );311 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_FRONT_END_ID ); 312 312 if (_param->_have_port_depth) 313 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_DEPTH );314 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_TYPE );315 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_IS_DELAY_SLOT );316 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS );317 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL );318 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR );319 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL );320 INSTANCE _SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR );313 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_DEPTH ); 314 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_TYPE ); 315 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); 316 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS ); 317 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL ); 318 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EPCR ); 319 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); 320 INSTANCE0_SC_SIGNAL(_Commit_unit,out_UPDATE_ADDRESS_EEAR ); 321 321 322 322 INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); … … 708 708 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 709 709 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 710 DELETE _SC_SIGNAL(out_UPDATE_VAL );711 DELETE _SC_SIGNAL( in_UPDATE_ACK );712 DELETE _SC_SIGNAL(out_UPDATE_CONTEXT_ID );713 DELETE _SC_SIGNAL(out_UPDATE_FRONT_END_ID );714 DELETE _SC_SIGNAL(out_UPDATE_DEPTH );715 DELETE _SC_SIGNAL(out_UPDATE_TYPE );716 DELETE _SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT );717 DELETE _SC_SIGNAL(out_UPDATE_ADDRESS );718 DELETE _SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL );719 DELETE _SC_SIGNAL(out_UPDATE_ADDRESS_EPCR );720 DELETE _SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL );721 DELETE _SC_SIGNAL(out_UPDATE_ADDRESS_EEAR );710 DELETE0_SC_SIGNAL(out_UPDATE_VAL ); 711 DELETE0_SC_SIGNAL( in_UPDATE_ACK ); 712 DELETE0_SC_SIGNAL(out_UPDATE_CONTEXT_ID ); 713 DELETE0_SC_SIGNAL(out_UPDATE_FRONT_END_ID ); 714 DELETE0_SC_SIGNAL(out_UPDATE_DEPTH ); 715 DELETE0_SC_SIGNAL(out_UPDATE_TYPE ); 716 DELETE0_SC_SIGNAL(out_UPDATE_IS_DELAY_SLOT ); 717 DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS ); 718 DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ); 719 DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EPCR ); 720 DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ); 721 DELETE0_SC_SIGNAL(out_UPDATE_ADDRESS_EEAR ); 722 722 723 723 DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r111 r112 238 238 private : Tevent_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] 239 239 private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] 240 private : bool ** reg_EVENT_STOP ;//[nb_front_end][nb_context] 240 241 241 242 //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r111 r112 35 35 ROB_STORE_HEAD_KO , // 36 36 ROB_OTHER_WAIT_END , // 37 ROB_MISS_WAIT_END , // 37 38 ROB_EVENT_WAIT_END , // 39 38 40 ROB_END_OK_SPECULATIVE , // 39 41 ROB_END_OK , // … … 49 51 ROB_END_EXCEPTION_UPDATE , // 50 52 ROB_END_EXCEPTION // 53 51 54 } rob_state_t; 52 55 … … 121 124 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "ROB_STORE_HEAD_KO" ; break; 122 125 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "ROB_OTHER_WAIT_END" ; break; 123 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_ MISS_WAIT_END : return "ROB_MISS_WAIT_END"; break;126 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END : return "ROB_EVENT_WAIT_END" ; break; 124 127 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "ROB_END_OK_SPECULATIVE" ; break; 125 128 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "ROB_END_OK" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
r110 r112 118 118 # ifdef SYSTEMCASS_SPECIFIC 119 119 // List dependency information 120 for (uint32_t i=0; i<_param->_nb_rename_unit; i++)121 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)122 for (uint32_t x=0; x<_param->_nb_rename_unit; x++)123 for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++)124 {125 (*(out_INSERT_ACK [i][j])) (*(in_INSERT_VAL [x][y]));126 if (_param->_have_port_rob_ptr)127 (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y]));128 }120 // for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 121 // for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) 122 // for (uint32_t x=0; x<_param->_nb_rename_unit; x++) 123 // for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++) 124 // { 125 // (*(out_INSERT_ACK [i][j])) (*(in_INSERT_VAL [x][y])); 126 // if (_param->_have_port_rob_ptr) 127 // (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y])); 128 // } 129 129 # endif 130 130 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r111 r112 58 58 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC2_INTERFACE ("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);60 ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 61 61 62 62 _ALLOC2_VALACK_IN ( in_INSERT_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 96 96 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 97 97 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 98 99 ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 98 100 } 99 101 100 102 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 101 103 { 102 ALLOC2_INTERFACE ("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);104 ALLOC2_INTERFACE_BEGIN("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 103 105 104 106 _ALLOC2_VALACK_OUT(out_RETIRE_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); … … 125 127 _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 126 128 _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 129 130 ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 127 131 } 128 132 129 133 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 130 134 { 131 ALLOC2_INTERFACE ("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]);135 ALLOC2_INTERFACE_BEGIN("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]); 132 136 133 137 _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end,_param->_nb_context[it1]); 134 138 _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end,_param->_nb_context[it1]); 135 139 _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_front_end,_param->_nb_context[it1]); 140 141 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 136 142 } 137 143 138 144 // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 139 145 { 140 ALLOC1_INTERFACE ("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit);146 ALLOC1_INTERFACE_BEGIN("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit); 141 147 142 148 ALLOC1_VALACK_IN ( in_COMMIT_VAL ,VAL); … … 152 158 // ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id); 153 159 ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); 160 161 ALLOC1_INTERFACE_END(_param->_nb_inst_commit); 154 162 } 155 163 156 164 // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 157 165 { 158 ALLOC1_INTERFACE ("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute);166 ALLOC1_INTERFACE_BEGIN("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute); 159 167 160 168 ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); … … 166 174 ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type); 167 175 ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 176 177 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 168 178 } 169 179 170 180 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 171 181 { 172 ALLOC1_INTERFACE ("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete);182 ALLOC1_INTERFACE_BEGIN("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete); 173 183 174 184 ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_VAL ,VAL); … … 181 191 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); 182 192 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 193 194 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); 183 195 } 184 196 185 197 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 186 198 { 187 ALLOC_INTERFACE("update", OUT, WEST,_("Interface with to Context State.")); 188 189 ALLOC_VALACK_OUT(out_UPDATE_VAL ,VAL); 190 ALLOC_VALACK_IN ( in_UPDATE_ACK ,ACK); 191 ALLOC_SIGNAL_OUT(out_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 192 ALLOC_SIGNAL_OUT(out_UPDATE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); 193 ALLOC_SIGNAL_OUT(out_UPDATE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 194 ALLOC_SIGNAL_OUT(out_UPDATE_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); 195 ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 196 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 197 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 198 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 199 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); 200 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); 199 ALLOC0_INTERFACE_BEGIN("update", OUT, WEST,_("Interface with to Context State.")); 200 201 ALLOC0_VALACK_OUT(out_UPDATE_VAL ,VAL); 202 ALLOC0_VALACK_IN ( in_UPDATE_ACK ,ACK); 203 ALLOC0_SIGNAL_OUT(out_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 204 ALLOC0_SIGNAL_OUT(out_UPDATE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); 205 ALLOC0_SIGNAL_OUT(out_UPDATE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 206 ALLOC0_SIGNAL_OUT(out_UPDATE_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); 207 ALLOC0_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 208 ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 209 ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 210 ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 211 ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); 212 ALLOC0_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); 213 214 ALLOC0_INTERFACE_END(); 201 215 } 202 216 203 217 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 204 218 { 205 ALLOC2_INTERFACE ("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]);219 ALLOC2_INTERFACE_BEGIN("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]); 206 220 207 221 _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end, _param->_nb_context[it1]); … … 211 225 _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"ADDRESS_NEXT_VAL",Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 212 226 _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 227 228 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 213 229 } 214 230 215 231 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 216 232 { 217 ALLOC2_INTERFACE ("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]);233 ALLOC2_INTERFACE_BEGIN("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]); 218 234 219 235 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); 220 236 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); 221 237 _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]); 238 239 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 222 240 } 223 241 224 242 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 225 243 { 226 ALLOC2_INTERFACE ("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);244 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 227 245 228 246 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); 229 247 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); 230 248 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 249 250 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 231 251 } 232 252 … … 234 254 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 235 255 { 236 ALLOC2_INTERFACE ("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]);256 ALLOC2_INTERFACE_BEGIN("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]); 237 257 238 258 _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR_OVE ,"sr_ove" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); 259 260 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 239 261 } 240 262 241 263 // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 242 264 { 243 ALLOC2_INTERFACE ("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]);265 ALLOC2_INTERFACE_BEGIN("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]); 244 266 245 267 _ALLOC2_VALACK_OUT(out_SPR_WRITE_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); … … 251 273 _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 252 274 _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV ,"sr_ov" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 275 276 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 253 277 } 254 278 … … 289 313 ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); 290 314 ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 315 ALLOC2(reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 291 316 292 317 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r111 r112 124 124 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); 125 125 126 DELETE _SIGNAL(out_UPDATE_VAL ,1 );127 DELETE _SIGNAL( in_UPDATE_ACK ,1 );128 DELETE _SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_size_context_id );129 DELETE _SIGNAL(out_UPDATE_FRONT_END_ID ,_param->_size_front_end_id);130 DELETE _SIGNAL(out_UPDATE_DEPTH ,_param->_size_depth );131 DELETE _SIGNAL(out_UPDATE_TYPE ,_param->_size_event_type );132 DELETE _SIGNAL(out_UPDATE_IS_DELAY_SLOT ,1 );133 DELETE _SIGNAL(out_UPDATE_ADDRESS ,_param->_size_instruction_address );134 DELETE _SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,1 );135 DELETE _SIGNAL(out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address );136 DELETE _SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,1 );137 DELETE _SIGNAL(out_UPDATE_ADDRESS_EEAR ,_param->_size_instruction_address );126 DELETE0_SIGNAL(out_UPDATE_VAL ,1 ); 127 DELETE0_SIGNAL( in_UPDATE_ACK ,1 ); 128 DELETE0_SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_size_context_id ); 129 DELETE0_SIGNAL(out_UPDATE_FRONT_END_ID ,_param->_size_front_end_id); 130 DELETE0_SIGNAL(out_UPDATE_DEPTH ,_param->_size_depth ); 131 DELETE0_SIGNAL(out_UPDATE_TYPE ,_param->_size_event_type ); 132 DELETE0_SIGNAL(out_UPDATE_IS_DELAY_SLOT ,1 ); 133 DELETE0_SIGNAL(out_UPDATE_ADDRESS ,_param->_size_instruction_address ); 134 DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR_VAL ,1 ); 135 DELETE0_SIGNAL(out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); 136 DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR_VAL ,1 ); 137 DELETE0_SIGNAL(out_UPDATE_ADDRESS_EEAR ,_param->_size_instruction_address ); 138 138 139 139 DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); … … 194 194 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 195 195 DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 196 DELETE2(reg_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 196 197 // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 197 198 DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
r100 r112 30 30 #endif 31 31 bool can_rename_select [_param->_nb_rename_unit]; 32 33 // Initialisation 32 bool event_stop; 33 34 // Initialisation 35 event_stop = false; // one signal for all context. 36 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 37 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 38 event_stop |= reg_EVENT_STOP [i][j]; 34 39 for (uint32_t i=0; i<_param->_nb_bank; i++) 35 40 { … … 52 57 // log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); 53 58 54 std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert 55 std::list<generic::priority::select_t>::iterator it=select_insert ->begin(); 56 57 // Scan all bank ... 58 for (uint32_t i=0; i<_param->_nb_bank; i++) 59 if (not event_stop) 59 60 { 60 // compute the bank number (num_bank_tail is the older write slot) 61 uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; 62 63 // log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); 64 // log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); 65 // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); 66 67 // Scan all insert interface to find a valid transaction 68 while (it!=select_insert ->end()) 69 { 70 uint32_t num_rename_unit = it->grp; 71 uint32_t num_inst_insert = it->elt; 72 73 it++; 74 75 log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); 76 // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); 77 log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); 78 79 // Test if have instruction 80 // -> rename_unit_glue test the in-order insert !!!!! 81 if (can_rename_select [num_rename_unit] // and 82 // PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) 83 ) 84 { 85 log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); 86 log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); 87 88 // test if bank is not busy (full or previous access) 89 if (not bank_full [num_bank]) 90 { 91 // find !!! 92 insert_ack [num_rename_unit][num_inst_insert] = true; 93 94 Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); 95 61 std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert 62 std::list<generic::priority::select_t>::iterator it=select_insert ->begin(); 63 64 // Scan all bank ... 65 for (uint32_t i=0; i<_param->_nb_bank; i++) 66 { 67 // compute the bank number (num_bank_tail is the older write slot) 68 uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; 69 70 // log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); 71 // log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); 72 // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); 73 74 // Scan all insert interface to find a valid transaction 75 while (it!=select_insert ->end()) 76 { 77 uint32_t num_rename_unit = it->grp; 78 uint32_t num_inst_insert = it->elt; 79 80 it++; 81 82 log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); 83 // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); 84 log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); 85 86 // Test if have instruction 87 // -> rename_unit_glue test the in-order insert !!!!! 88 if (can_rename_select [num_rename_unit] // and 89 // PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) 90 ) 91 { 92 log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); 93 log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); 94 95 // test if bank is not busy (full or previous access) 96 if (not bank_full [num_bank]) 97 { 98 // find !!! 99 insert_ack [num_rename_unit][num_inst_insert] = true; 100 101 Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); 102 96 103 #ifdef SYSTEMC_VHDL_COMPATIBILITY 97 104 insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; 98 105 #else 99 100 106 if (_param->_have_port_rob_ptr ) 107 PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); 101 108 #endif 102 103 104 105 106 107 108 109 internal_BANK_INSERT_VAL [num_bank] = true; 110 internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; 111 internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; 112 113 break; 114 } 115 } 109 116 110 // is a valid instruction, but it's not send at a bank 111 // ... invalid this rename_unit (because, insert in_order) 112 can_rename_select [num_rename_unit] = false; 113 } 117 // is a valid instruction, but it's not send at a bank 118 // ... invalid this rename_unit (because, insert in_order) 119 can_rename_select [num_rename_unit] = false; 120 } 121 } 114 122 } 115 123 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r110 r112 76 76 PORT_READ(in_RETIRE_ACK [x][y])) // not busy 77 77 { 78 rob_state_t state = entry->state; 79 80 if ((state == ROB_END_OK ) or 81 (state == ROB_END_KO ) or 82 (state == ROB_END_BRANCH_MISS) or 83 (state == ROB_END_LOAD_MISS ) or 84 (state == ROB_END_MISS )// or 85 // (state == ROB_END_EXCEPTION) 86 ) 87 { 88 Tcontext_t front_end_id = entry->front_end_id; 89 Tcontext_t context_id = entry->context_id; 90 Tcontrol_t write_re = entry->write_re; 91 Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; 92 93 // if state is ok, when write flags in the SR regsiters 94 bool spr_write_ack = true; 95 96 // Write in SR the good flag 97 if ((state == ROB_END_OK ) and write_re) 98 // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE 99 { 100 spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); 101 102 // retire_ack is set !!! 103 spr_write_val [front_end_id][context_id] = 1; 104 105 Tspecial_data_t flags = entry->flags; 106 107 switch (num_reg_re_log) 108 { 109 case SPR_LOGIC_SR_F : 110 { 111 spr_write_sr_f_val [front_end_id][context_id] = 1; 112 spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; 113 114 break; 115 } 116 case SPR_LOGIC_SR_CY_OV : 117 { 118 spr_write_sr_cy_val [front_end_id][context_id] = 1; 119 spr_write_sr_ov_val [front_end_id][context_id] = 1; 120 spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; 121 spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; 122 123 break; 124 } 125 default : 126 { 78 rob_state_t state = entry->state; 79 if ((state == ROB_END_OK ) or 80 (state == ROB_END_KO ) or 81 (state == ROB_END_BRANCH_MISS) or 82 (state == ROB_END_LOAD_MISS ) or 83 (state == ROB_END_MISS )// or 84 // (state == ROB_END_EXCEPTION) 85 ) 86 { 87 Tcontrol_t write_re = entry->write_re; 88 Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; 89 Tcontext_t front_end_id = entry->front_end_id; 90 Tcontext_t context_id = entry->context_id; 91 92 // if state is ok, when write flags in the SR regsiters 93 bool spr_write_ack = true; 94 95 // Write in SR the good flag 96 if ((state == ROB_END_OK ) and write_re) 97 // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE 98 { 99 spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); 100 101 // retire_ack is set !!! 102 spr_write_val [front_end_id][context_id] = 1; 103 104 Tspecial_data_t flags = entry->flags; 105 106 switch (num_reg_re_log) 107 { 108 case SPR_LOGIC_SR_F : 109 { 110 spr_write_sr_f_val [front_end_id][context_id] = 1; 111 spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; 112 113 break; 114 } 115 case SPR_LOGIC_SR_CY_OV : 116 { 117 spr_write_sr_cy_val [front_end_id][context_id] = 1; 118 spr_write_sr_ov_val [front_end_id][context_id] = 1; 119 spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; 120 spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; 121 122 break; 123 } 124 default : 125 { 127 126 #ifdef DEBUG_TEST 128 127 throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); 129 128 #endif 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id );151 152 153 154 155 PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write );156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 // Event -> rob must be manage this event172 if ((state == ROB_END_BRANCH_MISS) or173 (state == ROB_END_LOAD_MISS))174 can_retire [x] = false;175 129 } 130 } 131 } 132 133 // find an instruction can be retire, and in order 134 135 if (spr_write_ack) 136 { 137 retire_val [x][y] = 1; 138 num_inst_retire [x] ++; 139 internal_BANK_RETIRE_VAL [num_bank] = true; 140 } 141 142 internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; 143 internal_BANK_RETIRE_NUM_INST [num_bank] = y; 144 145 if (_param->_have_port_front_end_id) 146 PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); 147 if (_param->_have_port_context_id) 148 PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); 149 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); 150 PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); 151 PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); 152 PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); 153 if (_param->_have_port_load_queue_ptr) 154 PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); 155 PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); 156 PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); 157 PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); 158 PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); 159 PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); 160 PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); 161 PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); 162 PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); 163 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); 164 PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); 165 PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); 166 PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); 167 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); 168 PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); 169 170 // Event -> rob must be manage this event 171 if ((state == ROB_END_BRANCH_MISS) or 172 (state == ROB_END_LOAD_MISS)) 173 can_retire [x] = false; 174 } 176 175 } 177 176 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r111 r112 49 49 reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; 50 50 reg_EVENT_FLUSH [i][j] = false; 51 reg_EVENT_STOP [i][j] = false; 51 52 52 53 // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; … … 90 91 reg_EVENT_STATE [i][j] = EVENT_STATE_END; 91 92 reg_EVENT_FLUSH [i][j] = false; 93 //reg_EVENT_STOP [i][j] = false; 92 94 } 93 95 break; … … 324 326 case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} 325 327 // Store KO 326 case ROB_ MISS_WAIT_END: {state = ROB_END_KO_SPECULATIVE; break;}328 case ROB_EVENT_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 327 329 // Store OK, Load and other instruction 328 330 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} … … 333 335 } 334 336 } 337 338 if ((have_exception or have_miss_speculation) and 339 (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) 340 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 335 341 336 342 // update Re Order Buffer … … 364 370 365 371 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); 372 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); 366 373 367 374 #ifdef DEBUG_TEST … … 381 388 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); 382 389 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 390 log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((num_bank << _param->_shift_num_bank) | entry->ptr)); 383 391 log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); 384 392 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); … … 406 414 // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); 407 415 } 408 416 409 417 if ((state == ROB_END_BRANCH_MISS) or 410 418 (state == ROB_END_LOAD_MISS)) 411 { 412 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 413 reg_EVENT_FLUSH [front_end_id][context_id] = true; 414 } 419 { 420 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 421 reg_EVENT_FLUSH [front_end_id][context_id] = true; 422 reg_EVENT_STOP [front_end_id][context_id] = false; 423 } 415 424 416 425 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) … … 475 484 { 476 485 case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } 477 case ROB_STORE_HEAD_KO : {state = ROB_ MISS_WAIT_END; break; }486 case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; } 478 487 default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} 479 488 } … … 500 509 throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); 501 510 #endif 502 503 entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; 511 Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); 512 513 entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; 514 515 if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) 516 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 517 518 504 519 // entry->state = ROB_END_OK_SPECULATIVE; 505 520 } … … 612 627 switch (state) 613 628 { 614 case ROB_BRANCH_WAIT_END : {state = ROB_ MISS_WAIT_END; break;}615 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}629 case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 630 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 616 631 case ROB_END_BRANCH_MISS : 617 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}632 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 618 633 case ROB_END_LOAD_MISS_UPDATE : 619 634 case ROB_END_LOAD_MISS : 620 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}621 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;}635 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 636 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;} 622 637 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 623 case ROB_OTHER_WAIT_END : {state = ROB_ MISS_WAIT_END; break;}638 case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 624 639 case ROB_END_OK : 625 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}640 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 626 641 case ROB_END_KO : 627 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}642 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 628 643 case ROB_END_EXCEPTION_UPDATE : 629 644 case ROB_END_EXCEPTION : 630 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}645 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 631 646 632 647 // don't change 633 648 case ROB_STORE_HEAD_KO : {break;} 634 case ROB_ MISS_WAIT_END: {break;}649 case ROB_EVENT_WAIT_END : {break;} 635 650 case ROB_END_MISS : {break;} 636 651 … … 671 686 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 672 687 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 673 688 default : {break;} // else, no change 674 689 } 675 690 } … … 701 716 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); 702 717 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 718 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); 703 719 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 704 720 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); … … 784 800 // or (entry->state == ROB_STORE_HEAD_KO ) 785 801 // or (entry->state == ROB_OTHER_WAIT_END ) 786 // or (entry->state == ROB_ MISS_WAIT_END)802 // or (entry->state == ROB_EVENT_WAIT_END ) 787 803 // or (entry->state == ROB_END_OK_SPECULATIVE ) 788 804 or (entry->state == ROB_END_OK ) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp
r111 r112 59 59 // ~~~~~[ Interface : "issue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC2_INTERFACE ("issue_in", IN, WEST, _("Rename_out / Insert Rob interface"),_param->_nb_rename_unit, _param->_nb_inst_rename[it1]);61 ALLOC2_INTERFACE_BEGIN("issue_in", IN, WEST, _("Rename_out / Insert Rob interface"),_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); 62 62 63 63 _ALLOC2_VALACK_IN ( in_ISSUE_IN_VAL ,VAL,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); … … 82 82 _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); 83 83 _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); 84 85 ALLOC2_INTERFACE_END(_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); 84 86 } 85 87 86 88 // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 89 { 88 ALLOC1_INTERFACE ("reexecute", IN, NORTH, _("Instruction reexecute (store head/ spr access)"),_param->_nb_inst_reexecute);90 ALLOC1_INTERFACE_BEGIN("reexecute", IN, NORTH, _("Instruction reexecute (store head/ spr access)"),_param->_nb_inst_reexecute); 89 91 90 92 ALLOC1_VALACK_IN ( in_REEXECUTE_VAL ,VAL); … … 109 111 ALLOC1_SIGNAL_IN ( in_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 110 112 ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); 113 114 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 111 115 } 112 116 113 117 // ~~~~~[ Interface : "issue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 118 { 115 ALLOC1_INTERFACE ("issue_out",OUT, EAST, _("Go to issue network"),_param->_nb_inst_issue);119 ALLOC1_INTERFACE_BEGIN("issue_out",OUT, EAST, _("Go to issue network"),_param->_nb_inst_issue); 116 120 117 121 ALLOC1_VALACK_OUT(out_ISSUE_OUT_VAL ,VAL); … … 136 140 ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 137 141 ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); 142 143 ALLOC1_INTERFACE_END(_param->_nb_inst_issue); 138 144 } 139 145 … … 141 147 { 142 148 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 143 _issue_queue = new std::list<entry_t*> [_param->_nb_bank];149 ALLOC1(_issue_queue ,std::list<entry_t*>,_param->_nb_bank); 144 150 145 151 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp
r111 r112 95 95 96 96 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 97 delete [] _issue_queue;97 DELETE1(_issue_queue ,_param->_nb_bank); 98 98 99 99 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp
r97 r112 58 58 // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC2_INTERFACE ("rename",IN, SOUTH,_("rename's interface"),_param->_nb_front_end,_param->_nb_inst_decod[it1]);60 ALLOC2_INTERFACE_BEGIN("rename",IN, SOUTH,_("rename's interface"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 62 62 _ALLOC2_SIGNAL_IN ( in_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 63 63 _ALLOC2_SIGNAL_OUT(out_RENAME_RENAME_UNIT_FRONT_END_ID ,"RENAME_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 64 65 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_inst_decod[it1]); 64 66 } 65 67 66 68 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 67 69 { 68 ALLOC1_INTERFACE ("insert",OUT, WEST,_("insert's interface"),_param->_sum_inst_insert);70 ALLOC1_INTERFACE_BEGIN("insert",OUT, WEST,_("insert's interface"),_param->_sum_inst_insert); 69 71 70 72 ALLOC1_SIGNAL_OUT (out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1 ); … … 74 76 ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); 75 77 ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); 76 } 77 78 { 79 ALLOC2_INTERFACE("insert",IN, EAST,_("insert's interface"),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 78 79 ALLOC1_INTERFACE_END(_param->_sum_inst_insert); 80 } 81 82 { 83 ALLOC2_INTERFACE_BEGIN("insert",IN, EAST,_("insert's interface"),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 80 84 81 85 _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 146 150 _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_WRITE_RE ,"ISSUE_QUEUE_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 147 151 _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,"ISSUE_QUEUE_NUM_REG_RE" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 152 153 ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 148 154 } 149 155 150 156 // // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 151 157 // { 152 // ALLOC1_INTERFACE ("retire",OUT, WEST,_("retire's interface"),_param->_sum_inst_retire);158 // ALLOC1_INTERFACE_BEGIN("retire",OUT, WEST,_("retire's interface"),_param->_sum_inst_retire); 153 159 154 160 // ALLOC1_SIGNAL_OUT (out_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1 ); … … 162 168 // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); 163 169 // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); 170 171 // ALLOC1_INTERFACE_END(_param->_sum_inst_retire); 164 172 // } 165 173 166 174 // { 167 // ALLOC2_INTERFACE ("retire",IN, EAST,_("retire's interface"),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]);175 // ALLOC2_INTERFACE_BEGIN("retire",IN, EAST,_("retire's interface"),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 168 176 169 177 // _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); … … 188 196 // _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 189 197 // _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_EVENT_STATE ,"COMMIT_UNIT_EVENT_STATE" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 198 199 // ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 190 200 // } 191 201 192 202 // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 193 203 { 194 ALLOC2_INTERFACE ("spr",IN, NORTH,_("spr's interface"),_param->_nb_front_end,_param->_nb_context[it1]);204 ALLOC2_INTERFACE_BEGIN("spr",IN, NORTH,_("spr's interface"),_param->_nb_front_end,_param->_nb_context[it1]); 195 205 196 206 _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); … … 199 209 _ALLOC2_SIGNAL_OUT(out_SPR_COMMIT_UNIT_SR_OVE ,"COMMIT_UNIT_SR_OVE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 200 210 _ALLOC2_SIGNAL_IN ( in_SPR_SPECIAL_REGISTER_UNIT_SR ,"SPECIAL_REGISTER_UNIT_SR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); 211 212 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 201 213 } 202 214 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp
r97 r112 58 58 // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC2_INTERFACE ("execute_loop", IN, EAST, _("Instruction executed from execute_loop"),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);60 ALLOC2_INTERFACE_BEGIN("execute_loop", IN, EAST, _("Instruction executed from execute_loop"),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 61 61 62 62 _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL ,VAL,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); … … 72 72 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 74 75 ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 74 76 } 75 77 76 78 // ~~~~~[ Interface "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 79 { 78 ALLOC1_INTERFACE ("commit",OUT,WEST, _("Instruction executed to Re Order Buffer"),_param->_nb_inst_commit);80 ALLOC1_INTERFACE_BEGIN("commit",OUT,WEST, _("Instruction executed to Re Order Buffer"),_param->_nb_inst_commit); 79 81 80 82 ALLOC1_VALACK_OUT(out_COMMIT_VAL ,VAL); … … 91 93 ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 92 94 ALLOC1_SIGNAL_IN ( in_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t ,_param->_size_general_register); 95 96 ALLOC1_INTERFACE_END(_param->_nb_inst_commit); 93 97 } 94 98 95 99 // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 96 100 { 97 ALLOC1_INTERFACE ("spr",OUT,EAST, _("Access to Special Register"), _param->_nb_inst_reexecute);101 ALLOC1_INTERFACE_BEGIN("spr",OUT,EAST, _("Access to Special Register"), _param->_nb_inst_reexecute); 98 102 99 103 ALLOC1_VALACK_OUT(out_SPR_VAL ,VAL); … … 107 111 ALLOC1_SIGNAL_IN ( in_SPR_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); 108 112 ALLOC1_SIGNAL_IN ( in_SPR_INVALID ,"invalid" ,Tcontrol_t ,1); 113 114 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 109 115 } 110 116 111 117 // ~~~~~[ Interface : "reexecute_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 112 118 { 113 ALLOC1_INTERFACE ("reexecute_rob", IN,EAST, _("Instruction reexecuted by the Re Order Buffer (Store head)"), _param->_nb_inst_reexecute);119 ALLOC1_INTERFACE_BEGIN("reexecute_rob", IN,EAST, _("Instruction reexecuted by the Re Order Buffer (Store head)"), _param->_nb_inst_reexecute); 114 120 115 121 ALLOC1_VALACK_IN ( in_REEXECUTE_ROB_VAL ,VAL); … … 121 127 ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_TYPE ,"type" ,Ttype_t ,_param->_size_type); 122 128 ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 129 130 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 123 131 } 124 132 125 133 // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 126 134 { 127 ALLOC1_INTERFACE ("reexecute",OUT,SOUTH, _("Instruction reexecute, send at the issue_queue"), _param->_nb_inst_reexecute);135 ALLOC1_INTERFACE_BEGIN("reexecute",OUT,SOUTH, _("Instruction reexecute, send at the issue_queue"), _param->_nb_inst_reexecute); 128 136 129 137 ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); 130 138 ALLOC1_VALACK_IN ( in_REEXECUTE_ACK ,ACK); 131 ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 132 ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 133 ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 134 ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 135 ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 136 ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 137 ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 138 ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 139 ALLOC1_SIGNAL_OUT(out_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 140 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 141 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register ); 142 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 143 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register ); 144 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 145 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register ); 146 ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 147 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 148 ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 149 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); 139 ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 140 ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 141 ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 142 ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 143 ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 144 ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 145 ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 146 ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 147 ALLOC1_SIGNAL_OUT(out_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 148 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 149 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); 150 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 151 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); 152 ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 153 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); 154 ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 155 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); 156 ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 157 ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); 158 159 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 150 160 } 151 161 … … 153 163 { 154 164 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 155 _reexecute_queue = new std::list<entry_t *> [_param->_nb_bank];165 ALLOC1(_reexecute_queue ,std::list<entry_t *>,_param->_nb_bank); 156 166 157 167 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 158 internal_QUEUE_PUSH = new Tcontrol_t [_param->_nb_bank];159 internal_QUEUE_NUM_EXECUTE_LOOP = new uint32_t [_param->_nb_bank];160 internal_QUEUE_NUM_INST_EXECUTE = new uint32_t [_param->_nb_bank];161 internal_QUEUE_NUM_INST_COMMIT = new uint32_t [_param->_nb_bank];162 internal_QUEUE_INFO = new info_t [_param->_nb_bank];163 internal_SPR_VAL = new Tcontrol_t [_param->_nb_inst_reexecute];164 internal_REEXECUTE_ROB_ACK = new Tcontrol_t [_param->_nb_inst_reexecute];165 internal_REEXECUTE_VAL = new Tcontrol_t [_param->_nb_inst_reexecute];168 ALLOC1(internal_QUEUE_PUSH ,Tcontrol_t,_param->_nb_bank); 169 ALLOC1(internal_QUEUE_NUM_EXECUTE_LOOP ,uint32_t ,_param->_nb_bank); 170 ALLOC1(internal_QUEUE_NUM_INST_EXECUTE ,uint32_t ,_param->_nb_bank); 171 ALLOC1(internal_QUEUE_NUM_INST_COMMIT ,uint32_t ,_param->_nb_bank); 172 ALLOC1(internal_QUEUE_INFO ,info_t ,_param->_nb_bank); 173 ALLOC1(internal_SPR_VAL ,Tcontrol_t,_param->_nb_inst_reexecute); 174 ALLOC1(internal_REEXECUTE_ROB_ACK ,Tcontrol_t,_param->_nb_inst_reexecute); 175 ALLOC1(internal_REEXECUTE_VAL ,Tcontrol_t,_param->_nb_inst_reexecute); 166 176 #ifdef STATISTICS 167 internal_COMMIT_VAL = new Tcontrol_t [_param->_nb_inst_commit];177 ALLOC1(internal_COMMIT_VAL ,Tcontrol_t,_param->_nb_inst_commit); 168 178 #endif 169 179 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp
r88 r112 105 105 delete entry; 106 106 } 107 delete [] _reexecute_queue;107 DELETE1(_reexecute_queue ,_param->_nb_bank); 108 108 109 109 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 delete [] internal_QUEUE_PUSH;111 delete [] internal_QUEUE_NUM_EXECUTE_LOOP;112 delete [] internal_QUEUE_NUM_INST_EXECUTE;113 delete [] internal_QUEUE_NUM_INST_COMMIT;114 delete [] internal_QUEUE_INFO;115 delete [] internal_SPR_VAL;116 delete [] internal_REEXECUTE_ROB_ACK;117 delete [] internal_REEXECUTE_VAL;110 DELETE1(internal_QUEUE_PUSH ,_param->_nb_bank); 111 DELETE1(internal_QUEUE_NUM_EXECUTE_LOOP ,_param->_nb_bank); 112 DELETE1(internal_QUEUE_NUM_INST_EXECUTE ,_param->_nb_bank); 113 DELETE1(internal_QUEUE_NUM_INST_COMMIT ,_param->_nb_bank); 114 DELETE1(internal_QUEUE_INFO ,_param->_nb_bank); 115 DELETE1(internal_SPR_VAL ,_param->_nb_inst_reexecute); 116 DELETE1(internal_REEXECUTE_ROB_ACK ,_param->_nb_inst_reexecute); 117 DELETE1(internal_REEXECUTE_VAL ,_param->_nb_inst_reexecute); 118 118 #ifdef STATISTICS 119 delete [] internal_COMMIT_VAL;119 DELETE1(internal_COMMIT_VAL ,_param->_nb_inst_commit); 120 120 #endif 121 121 } 122 122 123 123 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 124 124 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp
r97 r112 58 58 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("insert", IN, EAST, "insert to the re order buffer an instruction", _param->_nb_inst_insert);60 ALLOC1_INTERFACE_BEGIN("insert", IN, EAST, _("insert to the re order buffer an instruction"), _param->_nb_inst_insert); 61 61 62 62 ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); … … 68 68 ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 69 69 ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 70 71 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 70 72 } 71 73 72 74 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 75 { 74 ALLOC1_INTERFACE ("retire", IN, EAST, "retire from the re order buffer an instruction", _param->_nb_inst_retire);76 ALLOC1_INTERFACE_BEGIN("retire", IN, EAST, _("retire from the re order buffer an instruction"), _param->_nb_inst_retire); 75 77 76 78 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); … … 84 86 ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); 85 87 ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 88 89 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 86 90 } 87 91 88 92 if (usage_is_set(_usage,USE_SYSTEMC)) 89 93 { 90 reg_STORE_QUEUE_PTR_WRITE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; 91 reg_STORE_QUEUE_USE = new bool * [_param->_nb_load_store_queue]; 92 reg_STORE_QUEUE_NB_USE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; 93 reg_LOAD_QUEUE_PTR_WRITE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; 94 reg_LOAD_QUEUE_USE = new bool * [_param->_nb_load_store_queue]; 95 96 for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) 97 { 98 reg_STORE_QUEUE_USE [i] = new bool [_param->_size_store_queue [i]]; 99 reg_LOAD_QUEUE_USE [i] = new bool [_param->_size_load_queue [i]]; 100 } 94 ALLOC1(reg_STORE_QUEUE_PTR_WRITE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); 95 ALLOC2(reg_STORE_QUEUE_USE ,bool ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]); 96 ALLOC1(reg_STORE_QUEUE_NB_USE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); 97 ALLOC1(reg_LOAD_QUEUE_PTR_WRITE ,Tlsq_ptr_t ,_param->_nb_load_store_queue); 98 ALLOC2(reg_LOAD_QUEUE_USE ,bool ,_param->_nb_load_store_queue,_param->_size_load_queue [it1]); 101 99 102 internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert];103 internal_INSERT_OPERATION_USE = new operation_use_t [_param->_nb_inst_insert];104 internal_INSERT_LSQ = new uint32_t [_param->_nb_inst_insert];105 internal_INSERT_PTR = new Tlsq_ptr_t [_param->_nb_inst_insert];100 ALLOC1(internal_INSERT_ACK ,Tcontrol_t ,_param->_nb_inst_insert); 101 ALLOC1(internal_INSERT_OPERATION_USE ,operation_use_t,_param->_nb_inst_insert); 102 ALLOC1(internal_INSERT_LSQ ,uint32_t ,_param->_nb_inst_insert); 103 ALLOC1(internal_INSERT_PTR ,Tlsq_ptr_t ,_param->_nb_inst_insert); 106 104 107 internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire];108 internal_RETIRE_OPERATION_USE = new operation_use_t [_param->_nb_inst_retire];109 internal_RETIRE_LSQ = new uint32_t [_param->_nb_inst_retire];110 internal_RETIRE_PTR = new Tlsq_ptr_t [_param->_nb_inst_retire];105 ALLOC1(internal_RETIRE_ACK ,Tcontrol_t ,_param->_nb_inst_retire); 106 ALLOC1(internal_RETIRE_OPERATION_USE ,operation_use_t,_param->_nb_inst_retire); 107 ALLOC1(internal_RETIRE_LSQ ,uint32_t ,_param->_nb_inst_retire); 108 ALLOC1(internal_RETIRE_PTR ,Tlsq_ptr_t ,_param->_nb_inst_retire); 111 109 } 112 110 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 28 29 delete in_NRESET; 29 30 30 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 31 delete [] in_INSERT_VAL ; 32 delete [] out_INSERT_ACK ; 33 if (_param->_have_port_front_end_id) 34 delete [] in_INSERT_FRONT_END_ID ; 35 if (_param->_have_port_context_id) 36 delete [] in_INSERT_CONTEXT_ID ; 37 delete [] in_INSERT_TYPE ; 38 delete [] in_INSERT_OPERATION ; 39 delete [] out_INSERT_STORE_QUEUE_PTR_WRITE; 40 if (_param->_have_port_load_queue_ptr) 41 delete [] out_INSERT_LOAD_QUEUE_PTR_WRITE ; 42 43 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 44 delete [] in_RETIRE_VAL ; 45 delete [] out_RETIRE_ACK ; 46 if (_param->_have_port_front_end_id) 47 delete [] in_RETIRE_FRONT_END_ID ; 48 if (_param->_have_port_context_id) 49 delete [] in_RETIRE_CONTEXT_ID ; 50 // delete [] in_RETIRE_TYPE ; 51 // delete [] in_RETIRE_OPERATION ; 52 delete [] in_RETIRE_USE_STORE_QUEUE ; 53 delete [] in_RETIRE_USE_LOAD_QUEUE ; 54 delete [] in_RETIRE_STORE_QUEUE_PTR_WRITE; 55 if (_param->_have_port_load_queue_ptr) 56 delete [] in_RETIRE_LOAD_QUEUE_PTR_WRITE ; 31 DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); 32 DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); 34 DELETE1_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 35 DELETE1_SIGNAL( in_INSERT_TYPE ,_param->_nb_inst_insert,_param->_size_type ); 36 DELETE1_SIGNAL( in_INSERT_OPERATION ,_param->_nb_inst_insert,_param->_size_operation ); 37 DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert,_param->_size_store_queue_ptr); 38 DELETE1_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert,_param->_size_load_queue_ptr ); 57 39 58 delete [] reg_STORE_QUEUE_PTR_WRITE ; 59 delete [] reg_STORE_QUEUE_USE ; 60 delete [] reg_STORE_QUEUE_NB_USE ; 61 delete [] reg_LOAD_QUEUE_PTR_WRITE ; 62 delete [] reg_LOAD_QUEUE_USE ; 63 delete [] internal_INSERT_ACK ; 64 delete [] internal_INSERT_OPERATION_USE; 65 delete [] internal_INSERT_LSQ ; 66 delete [] internal_INSERT_PTR ; 67 delete [] internal_RETIRE_ACK ; 68 delete [] internal_RETIRE_OPERATION_USE; 69 delete [] internal_RETIRE_LSQ ; 70 delete [] internal_RETIRE_PTR ; 40 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 41 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); 42 DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); 43 DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); 44 // DELETE1_SIGNAL( in_RETIRE_TYPE ,_param->_nb_inst_retire,_param->_size_type ); 45 // DELETE1_SIGNAL( in_RETIRE_OPERATION ,_param->_nb_inst_retire,_param->_size_operation ); 46 DELETE1_SIGNAL( in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire,1); 47 DELETE1_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire,1); 48 DELETE1_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr); 49 DELETE1_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr ); 50 51 DELETE1(reg_STORE_QUEUE_PTR_WRITE ,_param->_nb_load_store_queue); 52 DELETE2(reg_STORE_QUEUE_USE ,_param->_nb_load_store_queue,_param->_size_store_queue [it1]); 53 DELETE1(reg_STORE_QUEUE_NB_USE ,_param->_nb_load_store_queue); 54 DELETE1(reg_LOAD_QUEUE_PTR_WRITE ,_param->_nb_load_store_queue); 55 DELETE2(reg_LOAD_QUEUE_USE ,_param->_nb_load_store_queue,_param->_size_load_queue [it1]); 56 57 DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); 58 DELETE1(internal_INSERT_OPERATION_USE ,_param->_nb_inst_insert); 59 DELETE1(internal_INSERT_LSQ ,_param->_nb_inst_insert); 60 DELETE1(internal_INSERT_PTR ,_param->_nb_inst_insert); 61 62 DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); 63 DELETE1(internal_RETIRE_OPERATION_USE ,_param->_nb_inst_retire); 64 DELETE1(internal_RETIRE_LSQ ,_param->_nb_inst_retire); 65 DELETE1(internal_RETIRE_PTR ,_param->_nb_inst_retire); 71 66 } 72 67 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp
r88 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 58 58 // ~~~~~[ Interface "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("rename_in", IN, EAST, "Registers before near dependency checking", _param->_nb_inst_insert);60 ALLOC1_INTERFACE_BEGIN("rename_in", IN, EAST, _("Registers before near dependency checking"), _param->_nb_inst_insert); 61 61 62 // 63 // 62 // ALLOC1_VALACK_IN ( in_RENAME_IN_VAL ,VAL); 63 // ALLOC1_VALACK_OUT(out_RENAME_IN_ACK ,ACK); 64 64 ALLOC1_SIGNAL_IN ( in_RENAME_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 65 65 ALLOC1_SIGNAL_IN ( in_RENAME_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); … … 81 81 ALLOC1_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); 82 82 ALLOC1_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); 83 84 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 83 85 } 84 86 85 87 // ~~~~~[ Interface "rename_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 88 { 87 ALLOC1_INTERFACE ("rename_out", OUT, WEST, "Registers after near dependency checking", _param->_nb_inst_insert);89 ALLOC1_INTERFACE_BEGIN("rename_out", OUT, WEST, _("Registers after near dependency checking"), _param->_nb_inst_insert); 88 90 89 // 90 // 91 // ALLOC1_VALACK_OUT(out_RENAME_OUT_VAL ,VAL); 92 // ALLOC1_VALACK_IN ( in_RENAME_OUT_ACK ,ACK); 91 93 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 92 94 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); … … 108 110 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); 109 111 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); 112 113 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 110 114 } 111 115 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 // delete [] in_RENAME_IN_VAL ; 32 // delete [] out_RENAME_IN_ACK ; 33 if (_param->_have_port_front_end_id) 34 delete [] in_RENAME_IN_FRONT_END_ID ; 35 if (_param->_have_port_context_id) 36 delete [] in_RENAME_IN_CONTEXT_ID ; 37 delete [] in_RENAME_IN_READ_RA ; 38 delete [] in_RENAME_IN_NUM_REG_RA_LOG ; 39 delete [] in_RENAME_IN_NUM_REG_RA_PHY ; 40 delete [] in_RENAME_IN_READ_RB ; 41 delete [] in_RENAME_IN_NUM_REG_RB_LOG ; 42 delete [] in_RENAME_IN_NUM_REG_RB_PHY ; 43 delete [] in_RENAME_IN_READ_RC ; 44 delete [] in_RENAME_IN_NUM_REG_RC_LOG ; 45 delete [] in_RENAME_IN_NUM_REG_RC_PHY ; 46 delete [] in_RENAME_IN_WRITE_RD ; 47 delete [] in_RENAME_IN_NUM_REG_RD_LOG ; 48 delete [] in_RENAME_IN_NUM_REG_RD_PHY_OLD ; 49 delete [] in_RENAME_IN_NUM_REG_RD_PHY_NEW ; 50 delete [] in_RENAME_IN_WRITE_RE ; 51 delete [] in_RENAME_IN_NUM_REG_RE_LOG ; 52 delete [] in_RENAME_IN_NUM_REG_RE_PHY_OLD ; 53 delete [] in_RENAME_IN_NUM_REG_RE_PHY_NEW ; 32 // DELETE1_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_inst_insert,1); 33 // DELETE1_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); 35 DELETE1_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 36 DELETE1_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_inst_insert,1 ); 37 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 38 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 39 DELETE1_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_inst_insert,1 ); 40 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 41 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 42 DELETE1_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_inst_insert,1 ); 43 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 44 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); 45 DELETE1_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_inst_insert,1 ); 46 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 47 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert,_param->_size_general_register ); 48 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); 49 DELETE1_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_inst_insert,1 ); 50 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 51 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert,_param->_size_special_register ); 52 DELETE1_SIGNAL( in_RENAME_IN_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); 54 53 55 // delete [] out_RENAME_OUT_VAL ; 56 // delete [] in_RENAME_OUT_ACK ; 57 if (_param->_have_port_front_end_id) 58 delete [] out_RENAME_OUT_FRONT_END_ID ; 59 if (_param->_have_port_context_id) 60 delete [] out_RENAME_OUT_CONTEXT_ID ; 61 delete [] out_RENAME_OUT_READ_RA ; 62 delete [] out_RENAME_OUT_NUM_REG_RA_LOG ; 63 delete [] out_RENAME_OUT_NUM_REG_RA_PHY ; 64 delete [] out_RENAME_OUT_READ_RB ; 65 delete [] out_RENAME_OUT_NUM_REG_RB_LOG ; 66 delete [] out_RENAME_OUT_NUM_REG_RB_PHY ; 67 delete [] out_RENAME_OUT_READ_RC ; 68 delete [] out_RENAME_OUT_NUM_REG_RC_LOG ; 69 delete [] out_RENAME_OUT_NUM_REG_RC_PHY ; 70 delete [] out_RENAME_OUT_WRITE_RD ; 71 delete [] out_RENAME_OUT_NUM_REG_RD_LOG ; 72 delete [] out_RENAME_OUT_NUM_REG_RD_PHY_OLD; 73 delete [] out_RENAME_OUT_NUM_REG_RD_PHY_NEW; 74 delete [] out_RENAME_OUT_WRITE_RE ; 75 delete [] out_RENAME_OUT_NUM_REG_RE_LOG ; 76 delete [] out_RENAME_OUT_NUM_REG_RE_PHY_OLD; 77 delete [] out_RENAME_OUT_NUM_REG_RE_PHY_NEW; 54 // DELETE1_SIGNAL(out_RENAME_OUT_VAL ,_param->_nb_inst_insert,1); 55 // DELETE1_SIGNAL( in_RENAME_OUT_ACK ,_param->_nb_inst_insert,1); 56 DELETE1_SIGNAL(out_RENAME_OUT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); 57 DELETE1_SIGNAL(out_RENAME_OUT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 58 DELETE1_SIGNAL(out_RENAME_OUT_READ_RA ,_param->_nb_inst_insert,1 ); 59 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 60 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 61 DELETE1_SIGNAL(out_RENAME_OUT_READ_RB ,_param->_nb_inst_insert,1 ); 62 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 63 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 64 DELETE1_SIGNAL(out_RENAME_OUT_READ_RC ,_param->_nb_inst_insert,1 ); 65 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 66 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); 67 DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RD ,_param->_nb_inst_insert,1 ); 68 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 69 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register ); 70 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register ); 71 DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RE ,_param->_nb_inst_insert,1 ); 72 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 73 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register ); 74 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); 78 75 } 79 76 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp
r109 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 58 58 // ~~~~~[ interface : "pop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("pop", IN, NORTH, "New destination register", _param->_nb_pop);60 ALLOC1_INTERFACE_BEGIN("pop", IN, NORTH, _("New destination register"), _param->_nb_pop); 61 61 62 62 ALLOC1_VALACK_IN ( in_POP_VAL ,VAL); … … 66 66 ALLOC1_SIGNAL_IN ( in_POP_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 ); 67 67 ALLOC1_SIGNAL_OUT(out_POP_SPR_NUM_REG,"spr_num_reg",Tspecial_address_t,_param->_size_special_register); 68 69 ALLOC1_INTERFACE_END(_param->_nb_pop); 68 70 } 69 71 70 72 // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 71 73 { 72 ALLOC1_INTERFACE ("push_gpr", IN, NORTH, "General register free", _param->_nb_push);74 ALLOC1_INTERFACE_BEGIN("push_gpr", IN, NORTH, _("General register free"), _param->_nb_push); 73 75 74 76 ALLOC1_VALACK_IN ( in_PUSH_GPR_VAL ,VAL); 75 77 ALLOC1_VALACK_OUT(out_PUSH_GPR_ACK ,ACK); 76 78 ALLOC1_SIGNAL_IN ( in_PUSH_GPR_NUM_REG,"num_reg",Tgeneral_address_t,_param->_size_general_register); 79 80 ALLOC1_INTERFACE_END(_param->_nb_push); 77 81 } 78 82 79 83 // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 80 84 { 81 ALLOC1_INTERFACE ("push_spr", IN, NORTH, "General register free", _param->_nb_push);85 ALLOC1_INTERFACE_BEGIN("push_spr", IN, NORTH, _("General register free"), _param->_nb_push); 82 86 83 87 ALLOC1_VALACK_IN ( in_PUSH_SPR_VAL ,VAL); 84 88 ALLOC1_VALACK_OUT(out_PUSH_SPR_ACK ,ACK); 85 89 ALLOC1_SIGNAL_IN ( in_PUSH_SPR_NUM_REG,"num_reg",Tspecial_address_t,_param->_size_special_register); 90 91 ALLOC1_INTERFACE_END(_param->_nb_push); 86 92 } 87 93 88 94 if (usage_is_set(_usage,USE_SYSTEMC)) 89 95 { 90 _gpr_list = new std::list<uint32_t> [_param->_nb_bank];91 _spr_list = new std::list<uint32_t> [_param->_nb_bank];96 ALLOC1(_gpr_list,std::list<uint32_t>,_param->_nb_bank); 97 ALLOC1(_spr_list,std::list<uint32_t>,_param->_nb_bank); 92 98 93 internal_POP_ACK = new Tcontrol_t [_param->_nb_pop];94 internal_POP_GPR_BANK = new uint32_t [_param->_nb_pop];95 internal_POP_SPR_BANK = new uint32_t [_param->_nb_pop];99 ALLOC1(internal_POP_ACK ,Tcontrol_t,_param->_nb_pop); 100 ALLOC1(internal_POP_GPR_BANK ,uint32_t ,_param->_nb_pop); 101 ALLOC1(internal_POP_SPR_BANK ,uint32_t ,_param->_nb_pop); 96 102 97 internal_PUSH_GPR_ACK = new Tcontrol_t [_param->_nb_push];98 internal_PUSH_SPR_ACK = new Tcontrol_t [_param->_nb_push];99 internal_PUSH_GPR_BANK = new uint32_t [_param->_nb_push];100 internal_PUSH_SPR_BANK = new uint32_t [_param->_nb_push];103 ALLOC1(internal_PUSH_GPR_ACK ,Tcontrol_t,_param->_nb_push); 104 ALLOC1(internal_PUSH_SPR_ACK ,Tcontrol_t,_param->_nb_push); 105 ALLOC1(internal_PUSH_GPR_BANK,uint32_t ,_param->_nb_push); 106 ALLOC1(internal_PUSH_SPR_BANK,uint32_t ,_param->_nb_push); 101 107 } 108 102 109 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 110 _priority_gpr = new generic::priority::Priority (_name+"_priority_gpr", -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp
r109 r112 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_POP_VAL;32 delete [] out_POP_ACK;33 delete [] in_POP_GPR_VAL;34 delete [] out_POP_GPR_NUM_REG;35 delete [] in_POP_SPR_VAL;36 delete [] out_POP_SPR_NUM_REG;32 DELETE1_SIGNAL( in_POP_VAL ,_param->_nb_pop,1); 33 DELETE1_SIGNAL(out_POP_ACK ,_param->_nb_pop,1); 34 DELETE1_SIGNAL( in_POP_GPR_VAL ,_param->_nb_pop,1 ); 35 DELETE1_SIGNAL(out_POP_GPR_NUM_REG ,_param->_nb_pop,_param->_size_general_register); 36 DELETE1_SIGNAL( in_POP_SPR_VAL ,_param->_nb_pop,1 ); 37 DELETE1_SIGNAL(out_POP_SPR_NUM_REG ,_param->_nb_pop,_param->_size_special_register); 37 38 38 delete [] in_PUSH_GPR_VAL;39 delete [] out_PUSH_GPR_ACK;40 delete [] in_PUSH_GPR_NUM_REG;39 DELETE1_SIGNAL( in_PUSH_GPR_VAL ,_param->_nb_push,1); 40 DELETE1_SIGNAL(out_PUSH_GPR_ACK ,_param->_nb_push,1); 41 DELETE1_SIGNAL( in_PUSH_GPR_NUM_REG,_param->_nb_push,_param->_size_general_register); 41 42 42 delete [] in_PUSH_SPR_VAL;43 delete [] out_PUSH_SPR_ACK;44 delete [] in_PUSH_SPR_NUM_REG;43 DELETE1_SIGNAL( in_PUSH_SPR_VAL ,_param->_nb_push,1); 44 DELETE1_SIGNAL(out_PUSH_SPR_ACK ,_param->_nb_push,1); 45 DELETE1_SIGNAL( in_PUSH_SPR_NUM_REG,_param->_nb_push,_param->_size_special_register); 45 46 46 delete [] _gpr_list;47 delete [] _spr_list;48 49 delete [] internal_POP_ACK;50 delete [] internal_POP_GPR_BANK;51 delete [] internal_POP_SPR_BANK;52 53 delete [] internal_PUSH_GPR_ACK;54 delete [] internal_PUSH_SPR_ACK;55 delete [] internal_PUSH_GPR_BANK;56 delete [] internal_PUSH_SPR_BANK;47 DELETE1(_gpr_list ,_param->_nb_bank); 48 DELETE1(_spr_list ,_param->_nb_bank); 49 50 DELETE1(internal_POP_ACK ,_param->_nb_pop); 51 DELETE1(internal_POP_GPR_BANK ,_param->_nb_pop); 52 DELETE1(internal_POP_SPR_BANK ,_param->_nb_pop); 53 54 DELETE1(internal_PUSH_GPR_ACK ,_param->_nb_push); 55 DELETE1(internal_PUSH_SPR_ACK ,_param->_nb_push); 56 DELETE1(internal_PUSH_GPR_BANK,_param->_nb_push); 57 DELETE1(internal_PUSH_SPR_BANK,_param->_nb_push); 57 58 } 58 59 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r110 r112 51 51 52 52 #ifdef STATISTICS 53 (*_stat_nb_inst_pop) ++; 53 if (usage_is_set(_usage,USE_STATISTICS)) 54 (*_stat_nb_inst_pop) ++; 54 55 #endif 55 56 … … 57 58 { 58 59 #ifdef STATISTICS 59 (*_stat_nb_inst_pop_gpr) ++; 60 if (usage_is_set(_usage,USE_STATISTICS)) 61 (*_stat_nb_inst_pop_gpr) ++; 60 62 #endif 61 63 _gpr_list [internal_POP_GPR_BANK[i]].pop_front(); … … 65 67 { 66 68 #ifdef STATISTICS 67 (*_stat_nb_inst_pop_spr) ++; 69 if (usage_is_set(_usage,USE_STATISTICS)) 70 (*_stat_nb_inst_pop_spr) ++; 68 71 #endif 69 72 _spr_list [internal_POP_SPR_BANK[i]].pop_front(); … … 82 85 83 86 #ifdef STATISTICS 84 (*_stat_nb_inst_push_gpr) ++; 87 if (usage_is_set(_usage,USE_STATISTICS)) 88 (*_stat_nb_inst_push_gpr) ++; 85 89 #endif 86 90 … … 98 102 99 103 #ifdef STATISTICS 100 (*_stat_nb_inst_push_spr) ++; 104 if (usage_is_set(_usage,USE_STATISTICS)) 105 (*_stat_nb_inst_push_spr) ++; 101 106 #endif 102 107 … … 105 110 106 111 #ifdef STATISTICS 107 for (uint32_t i=0; i<_param->_nb_bank; ++i) 108 { 112 if (usage_is_set(_usage,USE_STATISTICS)) 113 for (uint32_t i=0; i<_param->_nb_bank; ++i) 114 { 115 109 116 (*(_stat_bank_gpr_nb_elt [i])) += _gpr_list[i].size(); 110 117 (*(_stat_bank_spr_nb_elt [i])) += _spr_list[i].size(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp
r106 r112 89 89 ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); 90 90 ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); 91 ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE ,"out_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); 91 92 92 93 ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_VAL ," in_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); … … 147 148 INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); 148 149 INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); 150 INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE ,_param->_nb_inst_retire); 149 151 150 152 INSTANCE2_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); … … 540 542 delete [] out_RETIRE_RESTORE_RD_PHY_OLD; 541 543 delete [] out_RETIRE_RESTORE_RE_PHY_OLD; 544 delete [] out_RETIRE_RESTORE ; 542 545 543 546 DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
r104 r112 104 104 public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] 105 105 public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] 106 public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE ;//[nb_inst_retire] 106 107 107 108 // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 126 127 private : bool *** internal_rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] 127 128 private : bool *** internal_rat_spr_update_table; //[nb_front_end][nb_context][nb_special_register_logic] 129 public : Tcontrol_t * internal_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] 130 public : Tcontrol_t * internal_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] 131 128 132 #endif 129 133 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
r104 r112 59 59 // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("rename",IN,EAST,"Input to rename source logical register", _param->_nb_inst_insert);61 ALLOC1_INTERFACE_BEGIN("rename",IN,EAST,_("Input to rename source logical register"), _param->_nb_inst_insert); 62 62 63 63 ALLOC1_VALACK_IN ( in_RENAME_VAL , VAL); … … 75 75 ALLOC1_SIGNAL_OUT(out_RENAME_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register); 76 76 ALLOC1_SIGNAL_OUT(out_RENAME_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); 77 78 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 77 79 } 78 80 79 81 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 80 82 { 81 ALLOC1_INTERFACE ("insert",IN,NORTH,"Input to rename destination logical register", _param->_nb_inst_insert);83 ALLOC1_INTERFACE_BEGIN("insert",IN,NORTH,_("Input to rename destination logical register"), _param->_nb_inst_insert); 82 84 83 85 ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); … … 91 93 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY,"num_reg_rd_phy",Tgeneral_address_t,_param->_size_general_register); 92 94 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY,"num_reg_re_phy",Tspecial_address_t,_param->_size_special_register); 95 96 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 93 97 } 94 98 95 99 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 96 100 { 97 ALLOC1_INTERFACE ("retire",IN,NORTH,"Input to update on event", _param->_nb_inst_retire);101 ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Input to update on event"), _param->_nb_inst_retire); 98 102 99 103 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); … … 109 113 ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RD_PHY_OLD,"restore_rd_phy_old",Tcontrol_t ,1); 110 114 ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RE_PHY_OLD,"restore_re_phy_old",Tcontrol_t ,1); 115 ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE ,"restore" ,Tcontrol_t ,1); 116 117 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 111 118 } 112 119 113 120 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 121 { 115 ALLOC2_INTERFACE ("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);122 ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); 116 123 117 124 _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); 118 125 _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); 119 126 _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); 127 128 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 120 129 } 121 130 … … 127 136 ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); 128 137 129 rat_gpr = new Tgeneral_address_t ** [_param->_nb_front_end];130 rat_spr = new Tspecial_address_t ** [_param->_nb_front_end];131 rat_gpr_update_table = new bool ** [_param->_nb_front_end];132 rat_spr_update_table = new bool ** [_param->_nb_front_end];133 internal_rat_gpr_update_table = new bool ** [_param->_nb_front_end];134 internal_rat_spr_update_table = new bool ** [_param->_nb_front_end];138 ALLOC3(rat_gpr ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 139 ALLOC3(rat_spr ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 140 ALLOC3(rat_gpr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 141 ALLOC3(rat_spr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 142 ALLOC3(internal_rat_gpr_update_table,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 143 ALLOC3(internal_rat_spr_update_table,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 135 144 136 for (uint32_t i=0; i<_param->_nb_front_end; i++) 137 { 138 rat_gpr [i] = new Tgeneral_address_t * [_param->_nb_context[i]]; 139 rat_spr [i] = new Tspecial_address_t * [_param->_nb_context[i]]; 140 rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; 141 rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; 142 internal_rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; 143 internal_rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; 144 145 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 146 { 147 rat_gpr [i][j] = new Tgeneral_address_t [_param->_nb_general_register_logic]; 148 rat_spr [i][j] = new Tspecial_address_t [_param->_nb_special_register_logic]; 149 rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; 150 rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; 151 internal_rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; 152 internal_rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; 153 } 154 } 145 ALLOC1(internal_RETIRE_RESTORE_RD_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire); 146 ALLOC1(internal_RETIRE_RESTORE_RE_PHY_OLD,Tcontrol_t,_param->_nb_inst_retire); 155 147 } 156 148 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
r104 r112 30 30 delete in_NRESET; 31 31 32 delete [] in_RENAME_VAL ; 33 delete [] out_RENAME_ACK ; 34 if (_param->_have_port_front_end_id) 35 delete [] in_RENAME_FRONT_END_ID ; 36 if (_param->_have_port_context_id) 37 delete [] in_RENAME_CONTEXT_ID ; 38 delete [] in_RENAME_NUM_REG_RA_LOG ; 39 delete [] in_RENAME_NUM_REG_RB_LOG ; 40 delete [] in_RENAME_NUM_REG_RC_LOG ; 41 delete [] in_RENAME_NUM_REG_RD_LOG ; 42 delete [] in_RENAME_NUM_REG_RE_LOG ; 43 delete [] out_RENAME_NUM_REG_RA_PHY ; 44 delete [] out_RENAME_NUM_REG_RB_PHY ; 45 delete [] out_RENAME_NUM_REG_RC_PHY ; 46 delete [] out_RENAME_NUM_REG_RD_PHY_OLD; 47 delete [] out_RENAME_NUM_REG_RE_PHY_OLD; 32 DELETE1_SIGNAL( in_RENAME_VAL ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL(out_RENAME_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); 35 DELETE1_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 36 DELETE1_SIGNAL( in_RENAME_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 37 DELETE1_SIGNAL( in_RENAME_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 38 DELETE1_SIGNAL( in_RENAME_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 39 DELETE1_SIGNAL( in_RENAME_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 40 DELETE1_SIGNAL( in_RENAME_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 41 DELETE1_SIGNAL(out_RENAME_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 42 DELETE1_SIGNAL(out_RENAME_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 43 DELETE1_SIGNAL(out_RENAME_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); 44 DELETE1_SIGNAL(out_RENAME_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register); 45 DELETE1_SIGNAL(out_RENAME_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register); 48 46 49 delete [] in_INSERT_VAL ; 50 delete [] out_INSERT_ACK ; 51 // if (_param->_have_port_front_end_id) 52 // delete [] in_INSERT_FRONT_END_ID ; 53 // if (_param->_have_port_context_id) 54 // delete [] in_INSERT_CONTEXT_ID ; 55 delete [] in_INSERT_WRITE_RD ; 56 delete [] in_INSERT_WRITE_RE ; 57 delete [] in_INSERT_NUM_REG_RD_LOG ; 58 delete [] in_INSERT_NUM_REG_RE_LOG ; 59 delete [] in_INSERT_NUM_REG_RD_PHY ; 60 delete [] in_INSERT_NUM_REG_RE_PHY ; 47 DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); 48 DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); 49 // DELETE1_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); 50 // DELETE1_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 51 DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1); 52 DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1); 53 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); 54 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); 55 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY,_param->_nb_inst_insert,_param->_size_general_register); 56 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY,_param->_nb_inst_insert,_param->_size_special_register); 61 57 62 delete [] in_RETIRE_VAL ; 63 delete [] out_RETIRE_ACK ; 64 if (_param->_have_port_front_end_id) 65 delete [] in_RETIRE_FRONT_END_ID ; 66 if (_param->_have_port_context_id) 67 delete [] in_RETIRE_CONTEXT_ID ; 68 delete [] in_RETIRE_WRITE_RD ; 69 delete [] in_RETIRE_WRITE_RE ; 70 delete [] in_RETIRE_NUM_REG_RD_LOG ; 71 delete [] in_RETIRE_NUM_REG_RE_LOG ; 72 delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; 73 delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; 74 delete [] out_RETIRE_RESTORE_RD_PHY_OLD; 75 delete [] out_RETIRE_RESTORE_RE_PHY_OLD; 58 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 59 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); 60 DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id); 61 DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); 62 DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1); 63 DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1); 64 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire,_param->_size_general_register_logic); 65 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire,_param->_size_special_register_logic); 66 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register); 67 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register); 68 DELETE1_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1); 69 DELETE1_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1); 70 DELETE1_SIGNAL(out_RETIRE_RESTORE ,_param->_nb_inst_retire,1); 71 72 DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); 73 DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); 74 DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); 76 75 77 76 DELETE1(internal_RENAME_ACK ,_param->_nb_inst_insert); … … 80 79 DELETE2(internal_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); 81 80 82 DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); 83 DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); 84 DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); 81 DELETE3(rat_gpr ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 82 DELETE3(rat_spr ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 83 DELETE3(rat_gpr_update_table ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 84 DELETE3(rat_spr_update_table ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 85 DELETE3(internal_rat_gpr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 86 DELETE3(internal_rat_spr_update_table,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 85 87 86 delete [] rat_gpr ; 87 delete [] rat_spr ; 88 delete [] rat_gpr_update_table; 89 delete [] rat_spr_update_table; 90 delete [] internal_rat_gpr_update_table; 91 delete [] internal_rat_spr_update_table; 88 DELETE1(internal_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); 89 DELETE1(internal_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); 92 90 } 93 91 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp
r106 r112 31 31 { 32 32 // An event occure 33 bool no_event = not (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) and (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); 33 // bool event = (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) != EVENT_STATE_NO_EVENT); 34 bool reset_update_table = (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and // always ack 35 (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); 36 37 // not event -> update_table == 1 -> always update 38 // event -> update_table and not reset 34 39 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 35 internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] and no_event; 40 internal_rat_gpr_update_table [i][j][k] = // not event or 41 (rat_gpr_update_table [i][j][k] and not reset_update_table); 36 42 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 37 internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] and no_event; 43 internal_rat_spr_update_table [i][j][k] = // not event or 44 (rat_spr_update_table [i][j][k] and not reset_update_table); 38 45 } 39 46 … … 50 57 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; 51 58 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; 59 Tcontrol_t restore = (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT); 52 60 53 61 // Test if event -> need restore ? 54 if ( PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT)62 if (restore) 55 63 { 56 64 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Have event"); … … 82 90 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re_phy_old : %d",retire_restore_re_phy_old); 83 91 } 92 93 internal_RETIRE_RESTORE_RD_PHY_OLD[i] = retire_restore_rd_phy_old; 94 internal_RETIRE_RESTORE_RE_PHY_OLD[i] = retire_restore_re_phy_old; 84 95 85 PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], retire_restore_rd_phy_old); 86 PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], retire_restore_re_phy_old); 96 PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], internal_RETIRE_RESTORE_RD_PHY_OLD[i]); 97 PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], internal_RETIRE_RESTORE_RE_PHY_OLD[i]); 98 PORT_WRITE(out_RETIRE_RESTORE [i], restore); 87 99 } 88 100 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
r106 r112 125 125 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); 126 126 127 if (event_state != EVENT_STATE_NO_EVENT)128 {127 // if (event_state != EVENT_STATE_NO_EVENT) 128 // { 129 129 // Test if write and have not a previous update 130 130 if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) 131 131 { 132 132 Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); 133 133 134 134 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RD"); 135 135 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log); 136 136 137 // if (RETIRE_RESTORE_RD_PHY_OLD [i]) 138 if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) 137 // #ifdef DEBUG_TEST 138 // if (not (internal_RETIRE_RESTORE_RD_PHY_OLD [i] and ( (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0)) and (event_state != EVENT_STATE_NO_EVENT))) 139 // throw ERRORMORPHEO(FUNCTION,toString(_("restore_rd_phy_old [%d] = %d, but rat_gpr_update_table[%d][%d][%d] = %d\n"), 140 // i,internal_RETIRE_RESTORE_RD_PHY_OLD [i], 141 // front_end_id,context_id,rd_log,rat_gpr_update_table [front_end_id][context_id][rd_log])); 142 // #endif 143 144 if (internal_RETIRE_RESTORE_RD_PHY_OLD [i]) 145 // if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) 139 146 { 140 147 rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); … … 150 157 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * re_log : %d",re_log); 151 158 152 // if (RETIRE_RESTORE_RE_PHY_OLD [i]) 153 if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) 159 // #ifdef DEBUG_TEST 160 // if (not (internal_RETIRE_RESTORE_RE_PHY_OLD [i] and ((rat_spr_update_table [front_end_id][context_id][re_log] == 0) and (event_state != EVENT_STATE_NO_EVENT)))) 161 // throw ERRORMORPHEO(FUNCTION,toString(_("restore_re_phy_old [%d] = %d, but rat_spr_update_table[%d][%d][%d] = %d\n"), 162 // i,internal_RETIRE_RESTORE_RE_PHY_OLD [i], 163 // front_end_id,context_id,re_log,rat_spr_update_table [front_end_id][context_id][re_log])); 164 // #endif 165 166 if (internal_RETIRE_RESTORE_RE_PHY_OLD [i]) 167 // if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) 154 168 { 155 169 rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); … … 157 171 } 158 172 } 159 }173 // } 160 174 } 161 175 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp
r110 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 59 59 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("insert",OUT, EAST, "insert's interface", _param->_nb_inst_insert);61 ALLOC1_INTERFACE_BEGIN("insert",OUT, EAST, _("insert's interface"), _param->_nb_inst_insert); 62 62 63 63 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); … … 122 122 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"NUM_REG_RE_PHY_OLD" ,Tspecial_address_t,_param->_size_special_register ); 123 123 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); 124 125 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 124 126 } 125 127 126 128 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 129 { 128 ALLOC1_INTERFACE ("retire", IN, WEST, "retire's interface", _param->_nb_inst_retire);130 ALLOC1_INTERFACE_BEGIN("retire", IN, WEST, _("retire's interface"), _param->_nb_inst_retire); 129 131 130 132 ALLOC1_SIGNAL_IN ( in_RETIRE_VAL ,"val" ,Tcontrol_t,1); … … 134 136 ALLOC1_SIGNAL_OUT(out_RETIRE_STAT_LIST_VAL,"stat_list_val",Tcontrol_t,1); 135 137 ALLOC1_SIGNAL_IN ( in_RETIRE_STAT_LIST_ACK,"stat_list_ack",Tcontrol_t,1); 138 139 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 136 140 } 137 141 138 142 #ifdef STATISTICS 139 ALLOC1(internal_INSERT_RENAME_ACK, Tcontrol_t,_param->_nb_inst_insert); 143 if (usage_is_set(_usage,USE_SYSTEMC)) 144 ALLOC1(internal_INSERT_RENAME_ACK, Tcontrol_t,_param->_nb_inst_insert); 140 145 #endif 141 146 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg
r88 r112 8 8 1 1 *4 #nb_reg_free 9 9 1 1 *2 #nb_bank 10 1 1 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg
r88 r112 8 8 1 4 *4 #nb_reg_free 9 9 8 8 *2 #nb_bank 10 1 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg
r88 r112 8 8 1 4 *4 #nb_reg_free 9 9 8 8 *2 #nb_bank 10 1 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg
r88 r112 11 11 4 4 *4 #nb_reg_free 12 12 8 8 *2 #nb_bank 13 2 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg
r88 r112 8 8 4 4 *4 #nb_reg_free 9 9 8 8 *2 #nb_bank 10 2 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg
r88 r112 9 9 4 4 *4 #nb_reg_free 10 10 8 8 *2 #nb_bank 11 2 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg
r88 r112 9 9 4 4 *4 #nb_reg_free 10 10 8 8 *2 #nb_bank 11 2 2 *2 #size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp
r88 r112 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 810 #define NB_PARAMS 7 11 11 12 12 void usage (int argc, char * argv[]) … … 22 22 err (_(" * nb_reg_free (uint32_t)\n")); 23 23 err (_(" * nb_bank (uint32_t)\n")); 24 err (_(" * size_read_counter (uint32_t)\n"));24 // err (_(" * size_read_counter (uint32_t)\n")); 25 25 26 26 exit (1); … … 51 51 uint32_t _nb_reg_free = atoi(argv[x++]); 52 52 uint32_t _nb_bank = atoi(argv[x++]); 53 uint32_t _size_read_counter = atoi(argv[x++]);53 // uint32_t _size_read_counter = atoi(argv[x++]); 54 54 55 55 int _return = EXIT_SUCCESS; … … 65 65 _nb_reg_free , 66 66 _nb_bank , 67 _size_read_counter ,67 // _size_read_counter , 68 68 true //is_toplevel 69 69 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg
r81 r112 8 8 1 4 *2 #_nb_reg_free 9 9 4 4 *2 #_nb_bank 10 2 2 +1 #_size_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg
r81 r112 9 9 4 4 *2 #_nb_reg_free 10 10 4 8 *2 #_nb_bank 11 2 4 *2 #_size_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp
r88 r112 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 810 #define NB_PARAMS 7 11 11 12 12 void usage (int argc, char * argv[]) … … 22 22 err (_(" * nb_reg_free (uint32_t)\n")); 23 23 err (_(" * nb_bank (uint32_t)\n")); 24 err (_(" * size_counter (uint32_t)\n"));25 24 26 25 exit (1); … … 55 54 uint32_t _nb_reg_free = atoi(argv[x++]); 56 55 uint32_t _nb_bank = atoi(argv[x++]); 57 uint32_t _size_counter = atoi(argv[x++]);58 56 59 57 try … … 68 66 _nb_reg_free , 69 67 _nb_bank , 70 _size_counter ,71 68 true //is_toplevel 72 69 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp
r88 r112 75 75 ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); 76 76 ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); 77 ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE ," in_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); 77 78 ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); 78 79 ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); … … 121 122 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_VAL ,_param->_nb_inst_retire); 122 123 INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); 124 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE ,_param->_nb_inst_retire); 123 125 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); 124 126 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); … … 234 236 TEST(bool, true,((gpr_status[reg]._is_free == 0) and 235 237 (gpr_status[reg]._is_link == 0) and 236 (gpr_status[reg]._is_valid == 1) and 237 (gpr_status[reg]._counter == 0))); 238 (gpr_status[reg]._is_valid == 1)// and 239 // (gpr_status[reg]._counter == 0) 240 )); 238 241 239 242 gpr_status[reg]._is_free = 1; … … 254 257 TEST(bool, true,((spr_status[reg]._is_free == 0) and 255 258 (spr_status[reg]._is_link == 0) and 256 (spr_status[reg]._is_valid == 1) and 257 (spr_status[reg]._counter == 0))); 259 (spr_status[reg]._is_valid == 1)// and 260 // (spr_status[reg]._counter == 0) 261 )); 258 262 259 263 spr_status[reg]._is_free = 1; … … 301 305 Tspecial_address_t re = (it_spr != free_list_spr.end())?*it_spr:0; 302 306 303 Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link) and (gpr_status_insert[ra]._counter < _param->_max_reader);304 Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link) and (gpr_status_insert[rb]._counter < _param->_max_reader);305 Tcontrol_t read_rc = (spr_status_insert[rc]._is_link) and (spr_status_insert[rc]._counter < _param->_max_reader);307 Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link); // and (gpr_status_insert[ra]._counter < _param->_max_reader); 308 Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link); // and (gpr_status_insert[rb]._counter < _param->_max_reader); 309 Tcontrol_t read_rc = (spr_status_insert[rc]._is_link); // and (spr_status_insert[rc]._counter < _param->_max_reader); 306 310 Tcontrol_t write_rd = (it_gpr != free_list_gpr.end()); 307 311 Tcontrol_t write_re = (it_spr != free_list_spr.end()); … … 341 345 Tspecial_address_t re_new = (rand()%(_param->_nb_special_register )) ; 342 346 343 Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link) and (gpr_status_retire[ra]._counter > 0);344 Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link) and (gpr_status_retire[rb]._counter > 0);345 Tcontrol_t read_rc = (spr_status_retire[rc]._is_link) and (spr_status_retire[rc]._counter > 0);347 Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link); // and (gpr_status_retire[ra]._counter > 0); 348 Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link); // and (gpr_status_retire[rb]._counter > 0); 349 Tcontrol_t read_rc = (spr_status_retire[rc]._is_link); // and (spr_status_retire[rc]._counter > 0); 346 350 Tcontrol_t write_rd = ( (gpr_status_retire[rd_old]._is_link ) and 347 351 (gpr_status_retire[rd_old]._is_valid) and … … 355 359 in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire); 356 360 in_RETIRE_READ_RA [i]->write(read_ra ); 357 in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); 361 in_RETIRE_RESTORE [i]->write(0); 362 in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); 358 363 in_RETIRE_READ_RB [i]->write(read_rb ); 359 364 in_RETIRE_NUM_REG_RB_PHY [i]->write(rb); … … 502 507 if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) 503 508 { 509 Tcontrol_t restore = in_RETIRE_RESTORE [i]->read(); 504 510 Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); 505 511 Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); … … 518 524 519 525 LABEL("RETIRE [%d] - Accepted",i); 526 LABEL(" * restore : %d",restore); 520 527 LABEL(" * read_ra : %d",read_ra ); 521 528 LABEL(" * reg_ra : %d",ra ); … … 575 582 if (write_rd) 576 583 { 577 if (restore _rd_old)584 if (restore) 578 585 { 579 gpr_status[rd_old]._is_link = 1; 580 gpr_status[rd_new]._is_link = 0; 581 gpr_status[rd_new]._is_valid = 1; 586 if (restore_rd_old) 587 { 588 gpr_status[rd_old]._is_link = 1; 589 gpr_status[rd_new]._is_link = 0; 590 gpr_status[rd_new]._is_valid = 1; 591 } 592 else 593 { 594 gpr_status[rd_old]._is_link = 0; 595 gpr_status[rd_new]._is_link = 0; 596 gpr_status[rd_new]._is_valid = 1; 597 } 582 598 } 583 599 else … … 586 602 gpr_status[rd_new]._is_valid = 1; 587 603 } 604 588 605 } 589 606 if (write_re) … … 619 636 TEST(bool, true,((gpr_status[reg]._is_free == 0) and 620 637 (gpr_status[reg]._is_link == 0) and 621 (gpr_status[reg]._is_valid == 1) and 622 (gpr_status[reg]._counter == 0))); 638 (gpr_status[reg]._is_valid == 1)// and 639 // (gpr_status[reg]._counter == 0) 640 )); 623 641 624 642 gpr_status[reg]._is_free = 1; … … 639 657 TEST(bool, true,((spr_status[reg]._is_free == 0) and 640 658 (spr_status[reg]._is_link == 0) and 641 (spr_status[reg]._is_valid == 1) and 642 (spr_status[reg]._counter == 0))); 659 (spr_status[reg]._is_valid == 1)// and 660 // (spr_status[reg]._counter == 0) 661 )); 643 662 644 663 spr_status[reg]._is_free = 1; … … 678 697 delete [] in_RETIRE_VAL ; 679 698 delete [] out_RETIRE_ACK ; 699 delete [] in_RETIRE_RESTORE ; 680 700 delete [] in_RETIRE_READ_RA ; 681 701 delete [] in_RETIRE_NUM_REG_RA_PHY ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h
r88 r112 34 34 public : uint32_t _nb_reg_free ; 35 35 public : uint32_t _nb_bank ; 36 36 //public : uint32_t _size_counter ; 37 37 38 38 //public : uint32_t _size_general_register ; 39 39 //public : uint32_t _size_special_register ; 40 40 41 41 //public : uint32_t _max_reader ; 42 42 public : uint32_t _nb_gpr_use_init ; 43 43 public : uint32_t _nb_spr_use_init ; … … 63 63 uint32_t nb_reg_free , 64 64 uint32_t nb_bank , 65 uint32_t size_counter ,65 // uint32_t size_counter , 66 66 bool is_toplevel=false 67 67 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h
r88 r112 79 79 public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] 80 80 public : SC_OUT(Tcontrol_t ) ** out_RETIRE_ACK ;//[nb_inst_retire] 81 public : SC_IN (Tcontrol_t ) ** in_RETIRE_RESTORE ;//[nb_inst_retire] 81 82 public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] 82 83 public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] … … 110 111 private : stat_list_entry_t ** spr_stat_list; //[nb_bank][nb_general_register_by_bank] 111 112 113 private : uint32_t reg_GPR_PTR_FREE; 114 private : uint32_t reg_SPR_PTR_FREE; 115 112 116 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 private : uint32_t internal_GPR_PTR_FREE;114 private : uint32_t internal_SPR_PTR_FREE;115 116 117 private : Tcontrol_t * internal_INSERT_ACK ;//[nb_inst_insert] 117 118 private : Tcontrol_t * internal_RETIRE_ACK ;//[nb_inst_retire] … … 154 155 public : void transition (void); 155 156 public : void genMoore (void); 156 157 //public : void genMealy (void); 157 158 #endif 158 159 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h
r88 r112 25 25 public : bool _is_free ; // set = is present in free list 26 26 public : bool _is_link ; // set = is present in rat 27 28 27 //public : bool _is_valid; // set = an instruction have write in this register 28 //public : uint32_t _counter ; // number of register that must read this register 29 29 30 30 public : stat_list_entry_t (void) {}; … … 35 35 _is_free = 0; 36 36 _is_link = is_link; 37 38 37 // _is_valid = 1; 38 // _counter = 0; 39 39 } 40 40 41 public : void insert_read (void) 42 { 43 _counter ++; 44 } 41 // public : void insert_read (void) 42 // { 43 // _counter ++; 44 // } 45 45 46 public : void insert_write (void) 46 47 { 47 48 _is_free = 0; 48 49 _is_link = 1; 49 50 // _is_valid = 0; 50 51 } 51 52 52 public : void retire_read (void) 53 // public : void retire_read (void) 54 // { 55 // _counter --; 56 // } 57 58 public : void retire_write_old (bool restore, bool restore_old) 53 59 { 54 _counter --; 60 // restore restore_old is_link 61 // 0 x 0 - normal case : unallocate 62 // 1 0 0 - event and previous update 63 // 1 1 1 - event and first update 64 65 _is_link = restore and restore_old; 55 66 } 56 67 57 public : void retire_write_ old (bool restore_old)68 public : void retire_write_new (bool restore, bool restore_old) 58 69 { 59 if (not restore_old) 60 { 61 _is_link = 0; 62 } 63 // else nothing 64 } 70 // restore restore_old is_link 71 // 0 x 1 - normal case : allocate 72 // 1 x 0 - event, need restore oldest register 65 73 66 public : void retire_write_new (bool restore_old) 67 { 68 if (restore_old) 69 { 70 _is_link = 0; 71 } 74 if (restore) 75 _is_link = 0; 72 76 73 77 // in all case 74 78 // _is_valid = 1; 75 79 } 76 80 … … 80 84 } 81 85 82 public : bool can_insert_read (uint32_t max_reader)83 {84 85 }86 // public : bool can_insert_read (uint32_t max_reader) 87 // { 88 // return ((_counter+1) < max_reader); 89 // } 86 90 87 91 public : bool can_free (void) 88 92 { 89 93 return ((_is_free == 0) and 90 (_is_link == 0) and 91 // (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset 92 (_counter == 0)); 94 (_is_link == 0) // and 95 // (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset 96 // (_counter == 0) 97 ); 93 98 } 94 99 … … 97 102 { 98 103 output << x._is_free << " " 99 << x._is_link << " " 100 << x._is_valid << " " 101 << x._counter; 104 << x._is_link // << " " 105 // << x._is_valid << " " 106 // << x._counter 107 ; 102 108 103 109 return output; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp
r88 r112 29 29 uint32_t nb_reg_free , 30 30 uint32_t nb_bank , 31 uint32_t size_counter ,31 // uint32_t size_counter , 32 32 bool is_toplevel) 33 33 { … … 42 42 _nb_reg_free = nb_reg_free ; 43 43 _nb_bank = nb_bank ; 44 44 // _size_counter = size_counter ; 45 45 46 46 // _max_reader = 1<<size_counter; 47 47 48 48 uint32_t nb_thread = 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters_print.cpp
r81 r112 35 35 xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); 36 36 xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); 37 xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end();37 // xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end(); 38 38 39 39 for (uint32_t i=0;i<_nb_front_end; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit.cpp
r88 r112 75 75 { 76 76 // Constant 77 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 78 { 79 internal_INSERT_ACK[i] = 1; 80 PORT_WRITE(out_INSERT_ACK[i], internal_INSERT_ACK[i]); 81 } 77 82 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 78 83 { … … 101 106 # endif 102 107 103 log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy");108 // log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy"); 104 109 105 SC_METHOD (genMealy);106 dont_initialize ();107 sensitive << (*(in_CLOCK)).neg(); // need internal register108 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)109 sensitive << (*(in_INSERT_READ_RA [i]))110 << (*(in_INSERT_NUM_REG_RA_PHY [i]))111 << (*(in_INSERT_READ_RB [i]))112 << (*(in_INSERT_NUM_REG_RB_PHY [i]))113 << (*(in_INSERT_READ_RC [i]))114 << (*(in_INSERT_NUM_REG_RC_PHY [i]));110 // SC_METHOD (genMealy); 111 // dont_initialize (); 112 // sensitive << (*(in_CLOCK)).neg(); // need internal register 113 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 114 // sensitive << (*(in_INSERT_READ_RA [i])) 115 // << (*(in_INSERT_NUM_REG_RA_PHY [i])) 116 // << (*(in_INSERT_READ_RB [i])) 117 // << (*(in_INSERT_NUM_REG_RB_PHY [i])) 118 // << (*(in_INSERT_READ_RC [i])) 119 // << (*(in_INSERT_NUM_REG_RC_PHY [i])); 115 120 116 # ifdef SYSTEMCASS_SPECIFIC117 // List dependency information121 // # ifdef SYSTEMCASS_SPECIFIC 122 // // List dependency information 118 123 119 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)120 {121 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i]));122 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i]));123 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i]));124 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i]));125 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i]));126 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i]));127 }128 # endif124 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 125 // { 126 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i])); 127 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i])); 128 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i])); 129 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i])); 130 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i])); 131 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i])); 132 // } 133 // # endif 129 134 130 135 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp
r88 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 58 58 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("insert",IN,SOUTH,"Insert a renaming result",_param->_nb_inst_insert);60 ALLOC1_INTERFACE_BEGIN("insert",IN,SOUTH,_("Insert a renaming result"),_param->_nb_inst_insert); 61 61 62 62 ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); … … 72 72 ALLOC1_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 73 73 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); 74 75 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 74 76 } 75 77 76 78 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 79 { 78 ALLOC1_INTERFACE ("retire",IN,NORTH,"Retire a renaming result",_param->_nb_inst_retire);80 ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Retire a renaming result"),_param->_nb_inst_retire); 79 81 80 82 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); 81 83 ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); 84 ALLOC1_SIGNAL_IN ( in_RETIRE_RESTORE ,"restore" ,Tcontrol_t ,1 ); 82 85 ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 83 86 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register); … … 94 97 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); 95 98 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); 99 100 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 96 101 } 97 102 98 103 // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 99 104 { 100 ALLOC1_INTERFACE ("push_gpr",OUT,SOUTH,"Free a general register",_param->_nb_reg_free);105 ALLOC1_INTERFACE_BEGIN("push_gpr",OUT,SOUTH,_("Free a general register"),_param->_nb_reg_free); 101 106 102 107 ALLOC1_VALACK_OUT(out_PUSH_GPR_VAL ,VAL); 103 108 ALLOC1_VALACK_IN ( in_PUSH_GPR_ACK ,ACK); 104 109 ALLOC1_SIGNAL_OUT(out_PUSH_GPR_NUM_REG,"num_reg",Tgeneral_address_t,_param->_size_general_register); 110 111 ALLOC1_INTERFACE_END(_param->_nb_reg_free); 105 112 } 106 113 107 114 // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 108 115 { 109 ALLOC1_INTERFACE ("push_spr",OUT,SOUTH,"Free a special register",_param->_nb_reg_free);116 ALLOC1_INTERFACE_BEGIN("push_spr",OUT,SOUTH,_("Free a special register"),_param->_nb_reg_free); 110 117 111 118 ALLOC1_VALACK_OUT(out_PUSH_SPR_VAL ,VAL); 112 119 ALLOC1_VALACK_IN ( in_PUSH_SPR_ACK ,ACK); 113 120 ALLOC1_SIGNAL_OUT(out_PUSH_SPR_NUM_REG,"num_reg",Tspecial_address_t,_param->_size_special_register); 121 122 ALLOC1_INTERFACE_END(_param->_nb_reg_free); 114 123 } 115 124 … … 117 126 if (usage_is_set(_usage,USE_SYSTEMC)) 118 127 { 119 gpr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; 120 spr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; 121 122 for (uint32_t i=0; i<_param->_nb_bank; i++) 123 { 124 gpr_stat_list [i] = new stat_list_entry_t [_param->_nb_general_register_by_bank]; 125 spr_stat_list [i] = new stat_list_entry_t [_param->_nb_special_register_by_bank]; 126 } 127 128 internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; 129 internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; 130 internal_PUSH_GPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; 131 internal_PUSH_GPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; 132 internal_PUSH_SPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; 133 internal_PUSH_SPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; 128 ALLOC2(gpr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_general_register_by_bank); 129 ALLOC2(spr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_special_register_by_bank); 130 ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); 131 ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); 132 ALLOC1(internal_PUSH_GPR_VAL ,Tcontrol_t,_param->_nb_reg_free); 133 ALLOC1(internal_PUSH_GPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); 134 ALLOC1(internal_PUSH_SPR_VAL ,Tcontrol_t,_param->_nb_reg_free); 135 ALLOC1(internal_PUSH_SPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); 134 136 } 135 137 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_INSERT_VAL;32 delete [] out_INSERT_ACK;33 delete [] in_INSERT_READ_RA;34 delete [] in_INSERT_NUM_REG_RA_PHY;35 delete [] in_INSERT_READ_RB;36 delete [] in_INSERT_NUM_REG_RB_PHY;37 delete [] in_INSERT_READ_RC;38 delete [] in_INSERT_NUM_REG_RC_PHY;39 delete [] in_INSERT_WRITE_RD;40 delete [] in_INSERT_NUM_REG_RD_PHY_NEW;41 delete [] in_INSERT_WRITE_RE;42 delete [] in_INSERT_NUM_REG_RE_PHY_NEW;32 DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL( in_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); 35 DELETE1_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 36 DELETE1_SIGNAL( in_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); 37 DELETE1_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 38 DELETE1_SIGNAL( in_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); 39 DELETE1_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); 40 DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); 41 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register); 42 DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); 43 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register); 43 44 44 delete [] in_RETIRE_VAL ; 45 delete [] out_RETIRE_ACK ; 46 delete [] in_RETIRE_READ_RA ; 47 delete [] in_RETIRE_NUM_REG_RA_PHY ; 48 delete [] in_RETIRE_READ_RB ; 49 delete [] in_RETIRE_NUM_REG_RB_PHY ; 50 delete [] in_RETIRE_READ_RC ; 51 delete [] in_RETIRE_NUM_REG_RC_PHY ; 52 delete [] in_RETIRE_WRITE_RD ; 53 delete [] in_RETIRE_RESTORE_RD_PHY_OLD; 54 delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; 55 delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; 56 delete [] in_RETIRE_WRITE_RE ; 57 delete [] in_RETIRE_RESTORE_RE_PHY_OLD; 58 delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; 59 delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; 45 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 46 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); 47 DELETE1_SIGNAL( in_RETIRE_RESTORE ,_param->_nb_inst_retire,1 ); 48 DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); 49 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register); 50 DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); 51 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register); 52 DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); 53 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register); 54 DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); 55 DELETE1_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1 ); 56 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register); 57 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register); 58 DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); 59 DELETE1_SIGNAL( in_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1 ); 60 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register); 61 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register); 60 62 61 delete [] out_PUSH_GPR_VAL ; 62 delete [] in_PUSH_GPR_ACK ; 63 DELETE1_SIGNAL(out_PUSH_GPR_VAL ,_param->_nb_reg_free,1); 64 DELETE1_SIGNAL( in_PUSH_GPR_ACK ,_param->_nb_reg_free,1); 65 DELETE1_SIGNAL(out_PUSH_GPR_NUM_REG,_param->_nb_reg_free,_param->_size_general_register); 63 66 64 delete [] out_PUSH_GPR_NUM_REG ; 65 delete [] out_PUSH_SPR_VAL ; 66 delete [] in_PUSH_SPR_ACK ; 67 delete [] out_PUSH_SPR_NUM_REG ; 68 69 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 71 delete [] gpr_stat_list; 72 delete [] spr_stat_list; 73 74 delete [] internal_INSERT_ACK ; 75 delete [] internal_RETIRE_ACK ; 76 delete [] internal_PUSH_GPR_VAL ; 77 delete [] internal_PUSH_GPR_NUM_BANK; 78 delete [] internal_PUSH_SPR_VAL ; 79 delete [] internal_PUSH_SPR_NUM_BANK; 67 DELETE1_SIGNAL(out_PUSH_SPR_VAL ,_param->_nb_reg_free,1); 68 DELETE1_SIGNAL( in_PUSH_SPR_ACK ,_param->_nb_reg_free,1); 69 DELETE1_SIGNAL(out_PUSH_SPR_NUM_REG,_param->_nb_reg_free,_param->_size_special_register); 70 71 DELETE2(gpr_stat_list ,_param->_nb_bank,_param->_nb_general_register_by_bank); 72 DELETE2(spr_stat_list ,_param->_nb_bank,_param->_nb_special_register_by_bank); 73 DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); 74 DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); 75 DELETE1(internal_PUSH_GPR_VAL ,_param->_nb_reg_free); 76 DELETE1(internal_PUSH_GPR_NUM_BANK,_param->_nb_reg_free); 77 DELETE1(internal_PUSH_SPR_VAL ,_param->_nb_reg_free); 78 DELETE1(internal_PUSH_SPR_NUM_BANK,_param->_nb_reg_free); 80 79 } 81 82 80 83 81 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp
r88 r112 19 19 20 20 21 #undef FUNCTION22 #define FUNCTION "Stat_List_unit::genMealy"23 void Stat_List_unit::genMealy (void)24 {25 log_begin(Stat_List_unit,FUNCTION);26 log_function(Stat_List_unit,FUNCTION,_name.c_str());21 // #undef FUNCTION 22 // #define FUNCTION "Stat_List_unit::genMealy" 23 // void Stat_List_unit::genMealy (void) 24 // { 25 // log_begin(Stat_List_unit,FUNCTION); 26 // log_function(Stat_List_unit,FUNCTION,_name.c_str()); 27 27 28 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)29 {30 bool ack = true;28 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 29 // { 30 // bool ack = true; 31 31 32 if (PORT_READ(in_INSERT_READ_RA [i]))33 {34 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]);35 uint32_t bank = num_reg >> _param->_shift_gpr;36 uint32_t reg = num_reg & _param->_mask_gpr ;37 ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);38 }32 // if (PORT_READ(in_INSERT_READ_RA [i])) 33 // { 34 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 35 // uint32_t bank = num_reg >> _param->_shift_gpr; 36 // uint32_t reg = num_reg & _param->_mask_gpr ; 37 // ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 38 // } 39 39 40 if (PORT_READ(in_INSERT_READ_RB [i]))41 {42 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]);43 uint32_t bank = num_reg >> _param->_shift_gpr;44 uint32_t reg = num_reg & _param->_mask_gpr ;45 ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);46 }40 // if (PORT_READ(in_INSERT_READ_RB [i])) 41 // { 42 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 43 // uint32_t bank = num_reg >> _param->_shift_gpr; 44 // uint32_t reg = num_reg & _param->_mask_gpr ; 45 // ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 46 // } 47 47 48 if (PORT_READ(in_INSERT_READ_RC [i]))49 {50 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]);51 uint32_t bank = num_reg >> _param->_shift_spr;52 uint32_t reg = num_reg & _param->_mask_spr ;53 ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader);54 }48 // if (PORT_READ(in_INSERT_READ_RC [i])) 49 // { 50 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 51 // uint32_t bank = num_reg >> _param->_shift_spr; 52 // uint32_t reg = num_reg & _param->_mask_spr ; 53 // ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 54 // } 55 55 56 internal_INSERT_ACK [i] = ack;57 PORT_WRITE(out_INSERT_ACK [i], ack);58 }56 // internal_INSERT_ACK [i] = ack; 57 // PORT_WRITE(out_INSERT_ACK [i], ack); 58 // } 59 59 60 log_end(Stat_List_unit,FUNCTION);61 };60 // log_end(Stat_List_unit,FUNCTION); 61 // }; 62 62 63 63 }; // end namespace stat_list_unit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp
r88 r112 26 26 log_function(Stat_List_unit,FUNCTION,_name.c_str()); 27 27 28 uint32_t gpr_ptr = internal_GPR_PTR_FREE;29 uint32_t spr_ptr = internal_SPR_PTR_FREE;28 uint32_t gpr_ptr = reg_GPR_PTR_FREE; 29 uint32_t spr_ptr = reg_SPR_PTR_FREE; 30 30 31 31 for (uint32_t i=0; i<_param->_nb_reg_free; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r106 r112 38 38 spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); 39 39 } 40 internal_GPR_PTR_FREE = 0;41 internal_SPR_PTR_FREE = 0;40 reg_GPR_PTR_FREE = 0; 41 reg_SPR_PTR_FREE = 0; 42 42 } 43 43 else … … 51 51 log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); 52 52 53 if (PORT_READ(in_INSERT_READ_RA [i]))54 {55 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]);56 57 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg);58 59 uint32_t bank = num_reg >> _param->_shift_gpr;60 uint32_t reg = num_reg & _param->_mask_gpr ;61 gpr_stat_list [bank][reg].insert_read();62 }63 64 if (PORT_READ(in_INSERT_READ_RB [i]))65 {66 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]);67 68 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg);69 70 uint32_t bank = num_reg >> _param->_shift_gpr;71 uint32_t reg = num_reg & _param->_mask_gpr ;72 gpr_stat_list [bank][reg].insert_read();73 }74 75 if (PORT_READ(in_INSERT_READ_RC [i]))76 {77 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]);78 79 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg);80 81 uint32_t bank = num_reg >> _param->_shift_spr;82 uint32_t reg = num_reg & _param->_mask_spr ;83 spr_stat_list [bank][reg].insert_read();84 }53 // if (PORT_READ(in_INSERT_READ_RA [i])) 54 // { 55 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 56 57 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 58 59 // uint32_t bank = num_reg >> _param->_shift_gpr; 60 // uint32_t reg = num_reg & _param->_mask_gpr ; 61 // gpr_stat_list [bank][reg].insert_read(); 62 // } 63 64 // if (PORT_READ(in_INSERT_READ_RB [i])) 65 // { 66 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 67 68 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 69 70 // uint32_t bank = num_reg >> _param->_shift_gpr; 71 // uint32_t reg = num_reg & _param->_mask_gpr ; 72 // gpr_stat_list [bank][reg].insert_read(); 73 // } 74 75 // if (PORT_READ(in_INSERT_READ_RC [i])) 76 // { 77 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 78 79 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 80 81 // uint32_t bank = num_reg >> _param->_shift_spr; 82 // uint32_t reg = num_reg & _param->_mask_spr ; 83 // spr_stat_list [bank][reg].insert_read(); 84 // } 85 85 86 86 if (PORT_READ(in_INSERT_WRITE_RD [i])) … … 88 88 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 89 89 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); 91 91 92 92 uint32_t bank = num_reg >> _param->_shift_gpr; … … 97 97 if (PORT_READ(in_INSERT_WRITE_RE [i])) 98 98 { 99 T general_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]);100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg 99 Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); 102 102 103 103 uint32_t bank = num_reg >> _param->_shift_spr; … … 115 115 log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); 116 116 117 if (PORT_READ(in_RETIRE_READ_RA [i])) 118 { 119 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 120 121 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 122 123 uint32_t bank = num_reg >> _param->_shift_gpr; 124 uint32_t reg = num_reg & _param->_mask_gpr ; 125 gpr_stat_list [bank][reg].retire_read(); 126 } 127 128 if (PORT_READ(in_RETIRE_READ_RB [i])) 129 { 130 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 131 132 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); 133 134 uint32_t bank = num_reg >> _param->_shift_gpr; 135 uint32_t reg = num_reg & _param->_mask_gpr ; 136 gpr_stat_list [bank][reg].retire_read(); 137 } 138 139 if (PORT_READ(in_RETIRE_READ_RC [i])) 140 { 141 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 142 143 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 144 145 uint32_t bank = num_reg >> _param->_shift_spr; 146 uint32_t reg = num_reg & _param->_mask_spr ; 147 spr_stat_list [bank][reg].retire_read(); 148 } 117 Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); 118 119 log_printf(TRACE,Stat_List_unit,FUNCTION," * restore : %d",restore); 120 121 // if (PORT_READ(in_RETIRE_READ_RA [i])) 122 // { 123 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 124 125 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 126 127 // uint32_t bank = num_reg >> _param->_shift_gpr; 128 // uint32_t reg = num_reg & _param->_mask_gpr ; 129 // gpr_stat_list [bank][reg].retire_read(); 130 // } 131 132 // if (PORT_READ(in_RETIRE_READ_RB [i])) 133 // { 134 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 135 136 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 137 138 // uint32_t bank = num_reg >> _param->_shift_gpr; 139 // uint32_t reg = num_reg & _param->_mask_gpr ; 140 // gpr_stat_list [bank][reg].retire_read(); 141 // } 142 143 // if (PORT_READ(in_RETIRE_READ_RC [i])) 144 // { 145 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 146 147 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 148 149 // uint32_t bank = num_reg >> _param->_shift_spr; 150 // uint32_t reg = num_reg & _param->_mask_spr ; 151 // spr_stat_list [bank][reg].retire_read(); 152 // } 149 153 150 154 if (PORT_READ(in_RETIRE_WRITE_RD [i])) … … 157 161 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); 158 162 159 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD -num_reg_old : %d",num_reg);163 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); 160 164 161 165 uint32_t bank = num_reg >> _param->_shift_gpr; 162 166 uint32_t reg = num_reg & _param->_mask_gpr ; 163 gpr_stat_list [bank][reg].retire_write_old(restore _old);167 gpr_stat_list [bank][reg].retire_write_old(restore, restore_old); 164 168 } 165 169 { 166 170 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 167 171 168 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD -num_reg_new : %d",num_reg);172 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); 169 173 170 174 uint32_t bank = num_reg >> _param->_shift_gpr; 171 175 uint32_t reg = num_reg & _param->_mask_gpr ; 172 gpr_stat_list [bank][reg].retire_write_new(restore _old);176 gpr_stat_list [bank][reg].retire_write_new(restore, restore_old); 173 177 } 174 178 } … … 181 185 182 186 { 183 T general_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]);184 185 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new: %d",num_reg);187 Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); 188 189 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); 186 190 187 191 uint32_t bank = num_reg >> _param->_shift_spr; 188 192 uint32_t reg = num_reg & _param->_mask_spr ; 189 spr_stat_list [bank][reg].retire_write_old(restore _old);193 spr_stat_list [bank][reg].retire_write_old(restore, restore_old); 190 194 } 191 195 { 192 T general_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);193 194 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE -num_reg_new : %d",num_reg);196 Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 197 198 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); 195 199 196 200 uint32_t bank = num_reg >> _param->_shift_spr; 197 201 uint32_t reg = num_reg & _param->_mask_spr ; 198 spr_stat_list [bank][reg].retire_write_new(restore _old);202 spr_stat_list [bank][reg].retire_write_new(restore, restore_old); 199 203 } 200 204 } … … 207 211 // ===================================================== 208 212 if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) 209 gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][ internal_GPR_PTR_FREE].free();213 gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][reg_GPR_PTR_FREE].free(); 210 214 211 215 // ===================================================== … … 213 217 // ===================================================== 214 218 if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) 215 spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][ internal_SPR_PTR_FREE].free();219 spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][reg_SPR_PTR_FREE].free(); 216 220 } 217 221 218 222 // Update pointer 219 internal_GPR_PTR_FREE = ((internal_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:internal_GPR_PTR_FREE)-1;220 internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1;223 reg_GPR_PTR_FREE = ((reg_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:reg_GPR_PTR_FREE)-1; 224 reg_SPR_PTR_FREE = ((reg_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:reg_SPR_PTR_FREE)-1; 221 225 } 222 226 223 227 224 228 #if (DEBUG >= DEBUG_TRACE) 225 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); 226 for (uint32_t i=0; i<_param->_nb_bank; i++) 227 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 228 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", 229 i, 230 j, 231 (i<<_param->_shift_gpr)|j, 232 gpr_stat_list[i][j]._is_free, 233 gpr_stat_list[i][j]._is_link, 234 gpr_stat_list[i][j]._is_valid, 235 gpr_stat_list[i][j]._counter); 236 for (uint32_t i=0; i<_param->_nb_bank; i++) 237 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 238 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", 239 i, 240 j, 241 (i<<_param->_shift_spr)|j, 242 spr_stat_list[i][j]._is_free, 243 spr_stat_list[i][j]._is_link, 244 spr_stat_list[i][j]._is_valid, 245 spr_stat_list[i][j]._counter); 229 { 230 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); 231 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); 232 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); 233 234 for (uint32_t i=0; i<_param->_nb_bank; i++) 235 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 236 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", 237 i, 238 j, 239 (i<<_param->_shift_gpr)|j, 240 gpr_stat_list[i][j]._is_free, 241 gpr_stat_list[i][j]._is_link// , 242 // gpr_stat_list[i][j]._is_valid, 243 // gpr_stat_list[i][j]._counter 244 ); 245 for (uint32_t i=0; i<_param->_nb_bank; i++) 246 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 247 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", 248 i, 249 j, 250 (i<<_param->_shift_spr)|j, 251 spr_stat_list[i][j]._is_free, 252 spr_stat_list[i][j]._is_link// , 253 // spr_stat_list[i][j]._is_valid, 254 // spr_stat_list[i][j]._counter 255 ); 256 } 246 257 #endif 258 259 #ifdef DEBUG_TEST 260 # if 0 261 { 262 uint32_t size_rob = 64; 263 uint32_t nb_context = 1; 264 265 { 266 uint32_t nb_is_link = 0; 267 uint32_t nb_reg = 32; 268 for (uint32_t i=0; i<_param->_nb_bank; i++) 269 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 270 if (gpr_stat_list[i][j]._is_link) 271 nb_is_link ++; 272 273 log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_GPR_IS_LINK : %d",nb_is_link); 274 275 if (nb_is_link > size_rob+nb_context*nb_reg) 276 throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked gpr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); 277 } 278 279 { 280 uint32_t nb_is_link = 0; 281 uint32_t nb_reg = 2; 282 for (uint32_t i=0; i<_param->_nb_bank; i++) 283 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 284 if (spr_stat_list[i][j]._is_link) 285 nb_is_link ++; 286 287 log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_SPR_IS_LINK : %d",nb_is_link); 288 289 if (nb_is_link > size_rob+nb_context*nb_reg) 290 throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked spr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); 291 } 292 } 293 # endif 294 #endif 295 247 296 248 297 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h
r88 r112 38 38 public : uint32_t _nb_reg_free ; 39 39 public : uint32_t _nb_bank ; 40 40 //public : uint32_t _size_read_counter ; 41 41 42 42 //public : uint32_t _size_front_end_id ; … … 62 62 uint32_t nb_reg_free , 63 63 uint32_t nb_bank , 64 uint32_t size_read_counter ,64 // uint32_t size_read_counter , 65 65 bool is_toplevel=false); 66 66 // public : Parameters (Parameters & param) ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp
r88 r112 28 28 uint32_t nb_reg_free , 29 29 uint32_t nb_bank , 30 uint32_t size_read_counter ,30 // uint32_t size_read_counter , 31 31 bool is_toplevel) 32 32 { … … 41 41 _nb_reg_free = nb_reg_free ; 42 42 _nb_bank = nb_bank ; 43 _size_read_counter = size_read_counter ;43 // _size_read_counter = size_read_counter ; 44 44 45 45 uint32_t size_general_register = log2(nb_general_register); … … 83 83 _nb_inst_retire , 84 84 _nb_reg_free , 85 _nb_bank , 86 _size_read_counter ); 85 _nb_bank // , 86 // _size_read_counter 87 ); 87 88 88 89 _param_register_translation_unit_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Parameters -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters_print.cpp
r81 r112 34 34 xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); 35 35 xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); 36 36 // xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); 37 37 for (uint32_t i=0;i<_nb_front_end; i++) 38 38 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
r104 r112 58 58 // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("rename", IN, EAST, "Instruction with logical register", _param->_nb_inst_insert);60 ALLOC1_INTERFACE_BEGIN("rename", IN, EAST, _("Instruction with logical register"), _param->_nb_inst_insert); 61 61 62 62 ALLOC1_VALACK_IN ( in_RENAME_VAL ,VAL); … … 74 74 ALLOC1_SIGNAL_IN ( in_RENAME_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 75 75 ALLOC1_SIGNAL_IN ( in_RENAME_NUM_REG_RE_LOG,"num_reg_re_log",Tspecial_address_t,_param->_size_special_register_logic); 76 77 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 76 78 } 77 79 78 80 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 81 { 80 ALLOC1_INTERFACE ("insert",OUT,WEST , "Instruction with physical register", _param->_nb_inst_insert);82 ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); 81 83 82 84 ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); … … 101 103 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); 102 104 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); 105 106 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 103 107 } 104 108 105 109 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 106 110 { 107 ALLOC1_INTERFACE("retire",IN ,NORTH, "Retire instruction, update renaming structure.", _param->_nb_inst_retire); 111 ALLOC1_INTERFACE_BEGIN("retire",IN ,NORTH, _("Retire instruction, update renaming structure."), _param->_nb_inst_retire); 112 108 113 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); 109 114 ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); … … 124 129 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register ); 125 130 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); 131 132 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 126 133 } 127 134 128 135 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 129 136 { 130 ALLOC2_INTERFACE ("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);137 ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); 131 138 132 139 _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); 133 140 _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); 134 141 _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); 142 143 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 135 144 } 136 145 … … 362 371 COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD", 363 372 dest, "in_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD"); 373 COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE" , 374 dest, "in_RETIRE_"+toString(i)+"_RESTORE" ); 364 375 } 365 376 … … 671 682 // in_RETIRE_RESTORE_RD_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RD_PHY_OLD 672 683 // in_RETIRE_RESTORE_RE_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RE_PHY_OLD 684 // in_RETIRE_RESTORE - register_address_translation_unit.out_RETIRE_RESTORE 673 685 674 686 dest = _name+"_register_translation_unit_glue"; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp
r104 r112 29 29 delete in_NRESET; 30 30 31 delete [] in_RENAME_VAL ; 32 delete [] out_RENAME_ACK ; 33 if (_param->_have_port_front_end_id) 34 delete [] in_RENAME_FRONT_END_ID ; 35 if (_param->_have_port_context_id) 36 delete [] in_RENAME_CONTEXT_ID ; 37 delete [] in_RENAME_READ_RA ; 38 delete [] in_RENAME_NUM_REG_RA_LOG ; 39 delete [] in_RENAME_READ_RB ; 40 delete [] in_RENAME_NUM_REG_RB_LOG ; 41 delete [] in_RENAME_READ_RC ; 42 delete [] in_RENAME_NUM_REG_RC_LOG ; 43 delete [] in_RENAME_WRITE_RD ; 44 delete [] in_RENAME_NUM_REG_RD_LOG ; 45 delete [] in_RENAME_WRITE_RE ; 46 delete [] in_RENAME_NUM_REG_RE_LOG ; 31 DELETE1_SIGNAL( in_RENAME_VAL ,_param->_nb_inst_insert,1); 32 DELETE1_SIGNAL(out_RENAME_ACK ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); 34 DELETE1_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 35 DELETE1_SIGNAL( in_RENAME_READ_RA ,_param->_nb_inst_insert,1 ); 36 DELETE1_SIGNAL( in_RENAME_NUM_REG_RA_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); 37 DELETE1_SIGNAL( in_RENAME_READ_RB ,_param->_nb_inst_insert,1 ); 38 DELETE1_SIGNAL( in_RENAME_NUM_REG_RB_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); 39 DELETE1_SIGNAL( in_RENAME_READ_RC ,_param->_nb_inst_insert,1 ); 40 DELETE1_SIGNAL( in_RENAME_NUM_REG_RC_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); 41 DELETE1_SIGNAL( in_RENAME_WRITE_RD ,_param->_nb_inst_insert,1 ); 42 DELETE1_SIGNAL( in_RENAME_NUM_REG_RD_LOG,_param->_nb_inst_insert,_param->_size_general_register_logic); 43 DELETE1_SIGNAL( in_RENAME_WRITE_RE ,_param->_nb_inst_insert,1 ); 44 DELETE1_SIGNAL( in_RENAME_NUM_REG_RE_LOG,_param->_nb_inst_insert,_param->_size_special_register_logic); 47 45 48 delete [] out_INSERT_VAL ; 49 delete [] in_INSERT_ACK ; 50 if (_param->_have_port_front_end_id) 51 delete [] out_INSERT_FRONT_END_ID ; 52 if (_param->_have_port_context_id) 53 delete [] out_INSERT_CONTEXT_ID ; 54 delete [] out_INSERT_READ_RA ; 55 delete [] out_INSERT_NUM_REG_RA_LOG ; 56 delete [] out_INSERT_NUM_REG_RA_PHY ; 57 delete [] out_INSERT_READ_RB ; 58 delete [] out_INSERT_NUM_REG_RB_LOG ; 59 delete [] out_INSERT_NUM_REG_RB_PHY ; 60 delete [] out_INSERT_READ_RC ; 61 delete [] out_INSERT_NUM_REG_RC_LOG ; 62 delete [] out_INSERT_NUM_REG_RC_PHY ; 63 delete [] out_INSERT_WRITE_RD ; 64 delete [] out_INSERT_NUM_REG_RD_LOG ; 65 delete [] out_INSERT_NUM_REG_RD_PHY_OLD; 66 delete [] out_INSERT_NUM_REG_RD_PHY_NEW; 67 delete [] out_INSERT_WRITE_RE ; 68 delete [] out_INSERT_NUM_REG_RE_LOG ; 69 delete [] out_INSERT_NUM_REG_RE_PHY_OLD; 70 delete [] out_INSERT_NUM_REG_RE_PHY_NEW; 46 DELETE1_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert,1); 47 DELETE1_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert,1); 48 DELETE1_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); 49 DELETE1_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); 50 DELETE1_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); 51 DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 52 DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 53 DELETE1_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); 54 DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 55 DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); 56 DELETE1_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); 57 DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 58 DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); 59 DELETE1_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); 60 DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); 61 DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register ); 62 DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register ); 63 DELETE1_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); 64 DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); 65 DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register ); 66 DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); 71 67 72 delete [] in_RETIRE_VAL ; 73 delete [] out_RETIRE_ACK ; 74 if (_param->_have_port_front_end_id) 75 delete [] in_RETIRE_FRONT_END_ID ; 76 if (_param->_have_port_context_id) 77 delete [] in_RETIRE_CONTEXT_ID ; 78 delete [] in_RETIRE_READ_RA ; 79 delete [] in_RETIRE_NUM_REG_RA_PHY ; 80 delete [] in_RETIRE_READ_RB ; 81 delete [] in_RETIRE_NUM_REG_RB_PHY ; 82 delete [] in_RETIRE_READ_RC ; 83 delete [] in_RETIRE_NUM_REG_RC_PHY ; 84 delete [] in_RETIRE_WRITE_RD ; 85 delete [] in_RETIRE_NUM_REG_RD_LOG ; 86 delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; 87 delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; 88 delete [] in_RETIRE_WRITE_RE ; 89 delete [] in_RETIRE_NUM_REG_RE_LOG ; 90 delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; 91 delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; 68 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 69 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); 70 DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); 71 DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); 72 DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); 73 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); 74 DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); 75 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); 76 DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); 77 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register ); 78 DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); 79 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire,_param->_size_general_register_logic); 80 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register ); 81 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register ); 82 DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); 83 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire,_param->_size_special_register_logic); 84 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register ); 85 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register ); 92 86 93 87 DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
r108 r112 58 58 // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC2_INTERFACE ("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]);60 ALLOC2_INTERFACE_BEGIN("rename_in", IN, EAST, _("output of decod's stage"), _param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 61 62 62 _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 87 87 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 88 88 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 89 90 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_inst_decod[it1]); 89 91 } 90 92 91 93 // ~~~~~[ Interface : "rename_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 92 94 { 93 ALLOC1_INTERFACE ("rename_out", IN, EAST, "output of decod's stage", _param->_nb_inst_rename);95 ALLOC1_INTERFACE_BEGIN("rename_out", IN, EAST, _("output of decod's stage"), _param->_nb_inst_rename); 94 96 95 97 ALLOC1_VALACK_OUT(out_RENAME_OUT_VAL ,VAL); … … 120 122 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); 121 123 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 124 125 ALLOC1_INTERFACE_END(_param->_nb_inst_rename); 122 126 } 123 127 124 128 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 125 129 { 126 ALLOC2_INTERFACE ("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);130 ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); 127 131 128 132 _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); 133 134 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 129 135 } 130 136 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp
r108 r112 29 29 delete in_NRESET; 30 30 31 delete [] in_RENAME_IN_VAL ; 32 delete [] out_RENAME_IN_ACK ; 33 if (_param->_have_port_front_end_id) 34 delete [] in_RENAME_IN_FRONT_END_ID ; 35 if (_param->_have_port_context_id) 36 delete [] in_RENAME_IN_CONTEXT_ID ; 37 if (_param->_have_port_depth) 38 delete [] in_RENAME_IN_DEPTH ; 39 delete [] in_RENAME_IN_TYPE ; 40 delete [] in_RENAME_IN_OPERATION ; 41 delete [] in_RENAME_IN_NO_EXECUTE ; 42 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 31 DELETE2_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1); 32 DELETE2_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1); 33 DELETE2_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_front_end_id ); 34 DELETE2_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_context_id ); 35 DELETE2_SIGNAL( in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_depth ); 36 DELETE2_SIGNAL( in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_type ); 37 DELETE2_SIGNAL( in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_operation ); 38 DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 39 DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 43 40 #ifdef DEBUG 44 delete [] in_RENAME_IN_ADDRESS;41 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 45 42 #endif 46 delete [] in_RENAME_IN_ADDRESS_NEXT ; 47 delete [] in_RENAME_IN_HAS_IMMEDIAT ; 48 delete [] in_RENAME_IN_IMMEDIAT ; 49 delete [] in_RENAME_IN_READ_RA ; 50 delete [] in_RENAME_IN_NUM_REG_RA ; 51 delete [] in_RENAME_IN_READ_RB ; 52 delete [] in_RENAME_IN_NUM_REG_RB ; 53 delete [] in_RENAME_IN_READ_RC ; 54 delete [] in_RENAME_IN_NUM_REG_RC ; 55 delete [] in_RENAME_IN_WRITE_RD ; 56 delete [] in_RENAME_IN_NUM_REG_RD ; 57 delete [] in_RENAME_IN_WRITE_RE ; 58 delete [] in_RENAME_IN_NUM_REG_RE ; 59 delete [] in_RENAME_IN_EXCEPTION_USE ; 60 delete [] in_RENAME_IN_EXCEPTION ; 43 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 44 DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 45 DELETE2_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); 46 DELETE2_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 47 DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); 48 DELETE2_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 49 DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); 50 DELETE2_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 51 DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); 52 DELETE2_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 53 DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); 54 DELETE2_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 55 DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); 56 DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception_use ); 57 DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception ); 58 59 DELETE1_SIGNAL(out_RENAME_OUT_VAL ,_param->_nb_inst_rename,1); 60 DELETE1_SIGNAL( in_RENAME_OUT_ACK ,_param->_nb_inst_rename,1); 61 DELETE1_SIGNAL(out_RENAME_OUT_FRONT_END_ID ,_param->_nb_inst_rename,_param->_size_front_end_id ); 62 DELETE1_SIGNAL(out_RENAME_OUT_CONTEXT_ID ,_param->_nb_inst_rename,_param->_size_context_id ); 63 DELETE1_SIGNAL(out_RENAME_OUT_DEPTH ,_param->_nb_inst_rename,_param->_size_depth ); 64 DELETE1_SIGNAL(out_RENAME_OUT_TYPE ,_param->_nb_inst_rename,_param->_size_type ); 65 DELETE1_SIGNAL(out_RENAME_OUT_OPERATION ,_param->_nb_inst_rename,_param->_size_operation ); 66 DELETE1_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename,1 ); 67 DELETE1_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT ,_param->_nb_inst_rename,1 ); 68 #ifdef DEBUG 69 DELETE1_SIGNAL(out_RENAME_OUT_ADDRESS ,_param->_nb_inst_rename,_param->_size_instruction_address ); 70 #endif 71 DELETE1_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename,_param->_size_instruction_address ); 72 DELETE1_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename,1 ); 73 DELETE1_SIGNAL(out_RENAME_OUT_IMMEDIAT ,_param->_nb_inst_rename,_param->_size_general_data ); 74 DELETE1_SIGNAL(out_RENAME_OUT_READ_RA ,_param->_nb_inst_rename,1 ); 75 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RA ,_param->_nb_inst_rename,_param->_size_general_register_logic); 76 DELETE1_SIGNAL(out_RENAME_OUT_READ_RB ,_param->_nb_inst_rename,1 ); 77 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RB ,_param->_nb_inst_rename,_param->_size_general_register_logic); 78 DELETE1_SIGNAL(out_RENAME_OUT_READ_RC ,_param->_nb_inst_rename,1 ); 79 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RC ,_param->_nb_inst_rename,_param->_size_special_register_logic); 80 DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RD ,_param->_nb_inst_rename,1 ); 81 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RD ,_param->_nb_inst_rename,_param->_size_general_register_logic); 82 DELETE1_SIGNAL(out_RENAME_OUT_WRITE_RE ,_param->_nb_inst_rename,1 ); 83 DELETE1_SIGNAL(out_RENAME_OUT_NUM_REG_RE ,_param->_nb_inst_rename,_param->_size_special_register_logic); 84 DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION_USE ,_param->_nb_inst_rename,_param->_size_exception_use ); 85 DELETE1_SIGNAL(out_RENAME_OUT_EXCEPTION ,_param->_nb_inst_rename,_param->_size_exception ); 61 86 62 delete [] out_RENAME_OUT_VAL ; 63 delete [] in_RENAME_OUT_ACK ; 64 if (_param->_have_port_front_end_id) 65 delete [] out_RENAME_OUT_FRONT_END_ID ; 66 if (_param->_have_port_context_id) 67 delete [] out_RENAME_OUT_CONTEXT_ID ; 68 if (_param->_have_port_depth) 69 delete [] out_RENAME_OUT_DEPTH ; 70 delete [] out_RENAME_OUT_TYPE ; 71 delete [] out_RENAME_OUT_OPERATION ; 72 #ifdef DEBUG 73 delete [] out_RENAME_OUT_ADDRESS ; 74 #endif 75 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 76 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; 77 delete [] out_RENAME_OUT_IMMEDIAT ; 78 delete [] out_RENAME_OUT_READ_RA ; 79 delete [] out_RENAME_OUT_NUM_REG_RA ; 80 delete [] out_RENAME_OUT_READ_RB ; 81 delete [] out_RENAME_OUT_NUM_REG_RB ; 82 delete [] out_RENAME_OUT_READ_RC ; 83 delete [] out_RENAME_OUT_NUM_REG_RC ; 84 delete [] out_RENAME_OUT_WRITE_RD ; 85 delete [] out_RENAME_OUT_NUM_REG_RD ; 86 delete [] out_RENAME_OUT_WRITE_RE ; 87 delete [] out_RENAME_OUT_NUM_REG_RE ; 88 delete [] out_RENAME_OUT_EXCEPTION_USE; 87 DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); 88 } 89 89 90 DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state);91 }92 90 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 93 91 delete _priority; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
r111 r112 52 52 53 53 log_printf(TRACE,Rename_select,FUNCTION," * front_end[%d].inst_decod[%d]",x,y); 54 log_printf(TRACE,Rename_select,FUNCTION," * rename_in_val: %d",PORT_READ(in_RENAME_IN_VAL[x][y]));54 log_printf(TRACE,Rename_select,FUNCTION," * in_RENAME_OUT_VAL : %d",PORT_READ(in_RENAME_IN_VAL[x][y])); 55 55 log_printf(TRACE,Rename_select,FUNCTION," * previous_transaction : %d",previous_transaction[x]); 56 56 … … 63 63 ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]); 64 64 65 log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack: %d",PORT_READ(in_RENAME_OUT_ACK[i]));65 log_printf(TRACE,Rename_select,FUNCTION," * in_RENAME_OUT_ACK : %d",PORT_READ(in_RENAME_OUT_ACK[i])); 66 66 67 67 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp
r88 r112 59 59 // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("insert",OUT,NORTH,_("Insert interface"),_param->_nb_inst_insert);61 ALLOC1_INTERFACE_BEGIN("insert",OUT,NORTH,_("Insert interface"),_param->_nb_inst_insert); 62 62 63 63 // ALLOC1_SIGNAL_OUT(out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1); … … 68 68 ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); 69 69 ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); 70 // 70 // ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); 71 71 ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception); 72 72 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register); … … 78 78 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_OPERATION ,"RENAME_SELECT_OPERATION" ,Toperation_t ,_param->_size_operation); 79 79 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_IMMEDIAT ,"RENAME_SELECT_IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); 80 // 80 // ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,"RENAME_SELECT_EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); 81 81 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION ,"RENAME_SELECT_EXCEPTION" ,Texception_t ,_param->_size_exception); 82 82 ALLOC1_SIGNAL_OUT(out_INSERT_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); … … 91 91 ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,"LOAD_STORE_QUEUE_POINTER_TYPE" ,Ttype_t ,_param->_size_type); 92 92 ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,"LOAD_STORE_QUEUE_POINTER_OPERATION" ,Toperation_t ,_param->_size_operation); 93 94 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 93 95 } 94 96 95 97 // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 96 98 { 97 ALLOC1_INTERFACE ("retire",OUT,NORTH,_("Retire interface"),_param->_nb_inst_retire);99 ALLOC1_INTERFACE_BEGIN("retire",OUT,NORTH,_("Retire interface"),_param->_nb_inst_retire); 98 100 99 101 ALLOC1_SIGNAL_IN ( in_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1); … … 105 107 ALLOC1_SIGNAL_OUT(out_RETIRE_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); 106 108 ALLOC1_SIGNAL_IN ( in_RETIRE_REGISTER_TRANSLATION_ACK ,"REGISTER_TRANSLATION_ACK" ,Tcontrol_t ,1); 109 110 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 107 111 } 112 108 113 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 109 114 { 110 ALLOC2_INTERFACE ("spr_read",IN ,NORTH,_("SPR read"),_param->_nb_front_end,_param->_nb_context[it1]);115 ALLOC2_INTERFACE_BEGIN("spr_read",IN ,NORTH,_("SPR read"),_param->_nb_front_end,_param->_nb_context[it1]); 111 116 112 117 _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR ,"SR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end,_param->_nb_context[it1]); 118 119 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 113 120 } 114 121 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg
r110 r112 19 19 1 1 +1 # nb_reg_free 20 20 1 1 +1 # nb_bank 21 1 1 +1 # size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg
r110 r112 19 19 2 2 +1 # nb_reg_free 20 20 4 8 *2 # nb_bank 21 4 4 +1 # size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg
r110 r112 22 22 2 2 +1 # nb_reg_free 23 23 8 8 *2 # nb_bank 24 4 4 +1 # size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg
r110 r112 25 25 2 2 +1 # nb_reg_free 26 26 8 8 *2 # nb_bank 27 4 4 +1 # size_read_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp
r110 r112 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 1 410 #define NB_PARAMS 13 11 11 12 12 void usage (int argc, char * argv[]) … … 33 33 err (_(" * nb_reg_free (uint32_t )\n")); 34 34 err (_(" * nb_bank (uint32_t )\n")); 35 err (_(" * size_read_counter (uint32_t )\n"));35 // err (_(" * size_read_counter (uint32_t )\n")); 36 36 37 37 exit (1); … … 103 103 uint32_t _nb_reg_free = fromString<uint32_t >(argv[x++]); 104 104 uint32_t _nb_bank = fromString<uint32_t >(argv[x++]); 105 uint32_t _size_read_counter = fromString<uint32_t >(argv[x++]);105 // uint32_t _size_read_counter = fromString<uint32_t >(argv[x++]); 106 106 107 107 int _return = EXIT_SUCCESS; … … 128 128 _nb_reg_free , 129 129 _nb_bank , 130 _size_read_counter ,130 // _size_read_counter , 131 131 true //is_toplevel 132 132 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h
r110 r112 47 47 public : uint32_t _nb_reg_free ; 48 48 public : uint32_t _nb_bank ; 49 public : uint32_t _size_read_counter ;49 // public : uint32_t _size_read_counter ; 50 50 51 51 //public : uint32_t _size_front_end_id ; … … 87 87 uint32_t nb_reg_free , 88 88 uint32_t nb_bank , 89 uint32_t size_read_counter ,89 // uint32_t size_read_counter , 90 90 bool is_toplevel=false 91 91 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp
r110 r112 38 38 uint32_t nb_reg_free , 39 39 uint32_t nb_bank , 40 uint32_t size_read_counter ,40 // uint32_t size_read_counter , 41 41 bool is_toplevel) 42 42 { … … 61 61 _nb_reg_free = nb_reg_free ; 62 62 _nb_bank = nb_bank ; 63 _size_read_counter = size_read_counter ;63 // _size_read_counter = size_read_counter ; 64 64 65 65 uint32_t size_special_register = log2(_nb_special_register); … … 91 91 _nb_inst_retire , 92 92 _nb_reg_free , 93 _nb_bank ,94 _size_read_counter93 _nb_bank // , 94 // _size_read_counter 95 95 ); 96 96 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp
r88 r112 39 39 xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); 40 40 xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); 41 xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end();41 // xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); 42 42 43 43 for (uint32_t i=0;i<_nb_front_end; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r108 r112 58 58 // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC2_INTERFACE ("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]);60 ALLOC2_INTERFACE_BEGIN("rename_in", IN, EAST, _("output of decod's stage"), _param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 61 62 62 _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 87 87 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 88 88 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 89 90 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_inst_decod[it1]); 89 91 } 90 92 91 93 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 92 94 { 93 ALLOC1_INTERFACE ("insert",OUT,WEST , "Instruction with physical register", _param->_nb_inst_insert);95 ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); 94 96 95 97 ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); … … 129 131 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); 130 132 ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); 133 134 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 131 135 } 132 136 133 137 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 134 138 { 135 ALLOC1_INTERFACE ("retire",IN ,NORTH, "Retire instruction, update renaming structure.", _param->_nb_inst_retire);139 ALLOC1_INTERFACE_BEGIN("retire",IN ,NORTH, _("Retire instruction, update renaming structure."), _param->_nb_inst_retire); 136 140 137 141 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); … … 159 163 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); 160 164 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); 165 166 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 161 167 } 162 168 163 169 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 164 170 { 165 ALLOC2_INTERFACE ("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]);171 ALLOC2_INTERFACE_BEGIN("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); 166 172 167 173 _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); 168 174 _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); 169 175 _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); 176 177 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 170 178 } 171 179 172 180 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 173 181 { 174 ALLOC2_INTERFACE ("spr_read", IN,NORTH, _("Special register"), _param->_nb_front_end, _param->_nb_context[it1]);182 ALLOC2_INTERFACE_BEGIN("spr_read", IN,NORTH, _("Special register"), _param->_nb_front_end, _param->_nb_context[it1]); 175 183 176 184 _ALLOC2_SIGNAL_IN (in_SPR_READ_SR ,"sr",Tspr_t ,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); 185 186 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 177 187 } 178 188 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
r111 r112 51 51 1 1 +1 # nb_reg_free [0] [nb_rename_unit] 52 52 1 1 +1 # nb_rename_unit_bank [0] [nb_rename_unit] 53 1 1 +1 # size_read_counter [0] [nb_rename_unit]54 53 1 1 +1 # nb_load_store_queue [0] [nb_rename_unit] 55 54 2 2 +1 # size_store_queue [0][0] [nb_rename_unit][nb_load_store_queue] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp
r111 r112 67 67 err (_(" * nb_reg_free [nb_rename_unit] (uint32_t )\n")); 68 68 err (_(" * nb_rename_unit_bank [nb_rename_unit] (uint32_t )\n")); 69 err (_(" * size_read_counter [nb_rename_unit] (uint32_t )\n"));69 // err (_(" * size_read_counter [nb_rename_unit] (uint32_t )\n")); 70 70 err (_(" * nb_load_store_queue [nb_rename_unit] (uint32_t )\n")); 71 71 err (_(" * size_store_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); … … 110 110 _nb_inst_decod [i] = fromString<uint32_t>(argv[x++]); 111 111 112 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+1 2*_nb_rename_unit+_nb_execute_loop))112 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop)) 113 113 usage (argc, argv); 114 114 … … 160 160 } 161 161 162 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+1 1*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue))162 if (argc <= static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue)) 163 163 usage (argc, argv); 164 164 … … 195 195 uint32_t * _nb_reg_free = new uint32_t [_nb_rename_unit]; 196 196 uint32_t * _nb_rename_unit_bank = new uint32_t [_nb_rename_unit]; 197 uint32_t * _size_read_counter = new uint32_t [_nb_rename_unit];197 // uint32_t * _size_read_counter = new uint32_t [_nb_rename_unit]; 198 198 uint32_t * _nb_load_store_queue = new uint32_t [_nb_rename_unit]; 199 199 … … 212 212 for (uint32_t i=0; i<_nb_rename_unit; i++) 213 213 _nb_rename_unit_bank [i] = fromString<uint32_t >(argv[x++]); 214 for (uint32_t i=0; i<_nb_rename_unit; i++)215 _size_read_counter [i] = fromString<uint32_t >(argv[x++]);214 // for (uint32_t i=0; i<_nb_rename_unit; i++) 215 // _size_read_counter [i] = fromString<uint32_t >(argv[x++]); 216 216 for (uint32_t i=0; i<_nb_rename_unit; i++) 217 217 { … … 220 220 } 221 221 222 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+1 1*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue))222 if (argc != static_cast<int>(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+10*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+3*_sum_nb_load_store_queue)) 223 223 usage (argc, argv); 224 224 … … 327 327 _nb_reg_free , 328 328 _nb_rename_unit_bank , 329 _size_read_counter ,329 // _size_read_counter , 330 330 _nb_load_store_queue , 331 331 _size_store_queue , … … 391 391 392 392 delete [] _nb_load_store_queue ; 393 delete [] _size_read_counter ;393 // delete [] _size_read_counter ; 394 394 delete [] _nb_rename_unit_bank ; 395 395 delete [] _nb_reg_free ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r110 r112 143 143 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ," in_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); 144 144 145 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_VAL ,"out_COMMIT_EVENT_VAL ",Tcontrol_t );146 ALLOC _SC_SIGNAL( in_COMMIT_EVENT_ACK ," in_COMMIT_EVENT_ACK ",Tcontrol_t );147 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,"out_COMMIT_EVENT_FRONT_END_ID ",Tcontext_t );148 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,"out_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );149 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_DEPTH ,"out_COMMIT_EVENT_DEPTH ",Tdepth_t );150 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_TYPE ,"out_COMMIT_EVENT_TYPE ",Tevent_type_t );151 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );152 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t );153 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t );154 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );155 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );156 ALLOC _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t );145 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_VAL ,"out_COMMIT_EVENT_VAL ",Tcontrol_t ); 146 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ACK ," in_COMMIT_EVENT_ACK ",Tcontrol_t ); 147 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,"out_COMMIT_EVENT_FRONT_END_ID ",Tcontext_t ); 148 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,"out_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); 149 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_DEPTH ,"out_COMMIT_EVENT_DEPTH ",Tdepth_t ); 150 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_TYPE ,"out_COMMIT_EVENT_TYPE ",Tevent_type_t ); 151 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 152 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); 153 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 154 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 155 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); 156 ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); 157 157 158 158 ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); … … 294 294 INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 295 295 296 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_VAL );297 INSTANCE _SC_SIGNAL(_OOO_Engine, in_COMMIT_EVENT_ACK );296 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_VAL ); 297 INSTANCE0_SC_SIGNAL(_OOO_Engine, in_COMMIT_EVENT_ACK ); 298 298 if (_param->_have_port_front_end_id) 299 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_FRONT_END_ID );299 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_FRONT_END_ID ); 300 300 if (_param->_have_port_context_id) 301 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_CONTEXT_ID );301 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_CONTEXT_ID ); 302 302 if (_param->_have_port_depth) 303 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_DEPTH );304 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_TYPE );305 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT );306 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS );307 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL );308 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR );309 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL );310 INSTANCE _SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR );303 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_DEPTH ); 304 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_TYPE ); 305 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); 306 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); 307 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 308 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); 309 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 310 INSTANCE0_SC_SIGNAL(_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR ); 311 311 312 312 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); … … 472 472 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 473 473 474 DELETE _SC_SIGNAL(out_COMMIT_EVENT_VAL );475 DELETE _SC_SIGNAL( in_COMMIT_EVENT_ACK );476 DELETE _SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID );477 DELETE _SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID );478 DELETE _SC_SIGNAL(out_COMMIT_EVENT_DEPTH );479 DELETE _SC_SIGNAL(out_COMMIT_EVENT_TYPE );480 DELETE _SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT );481 DELETE _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS );482 DELETE _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL );483 DELETE _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR );484 DELETE _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL );485 DELETE _SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR );474 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_VAL ); 475 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ACK ); 476 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ); 477 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ); 478 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_DEPTH ); 479 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_TYPE ); 480 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ); 481 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS ); 482 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 483 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ); 484 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 485 DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ); 486 486 487 487 DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp
r101 r112 58 58 // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute);60 ALLOC1_INTERFACE_BEGIN("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute); 61 61 62 62 ALLOC1_VALACK_IN ( in_SPR_ACCESS_VAL ,VAL); … … 70 70 ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); 71 71 ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_INVALID ,"invalid" ,Tcontrol_t ,1); 72 73 ALLOC1_INTERFACE_END(_param->_nb_inst_reexecute); 72 74 } 73 75 74 76 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 75 77 { 76 ALLOC2_INTERFACE ("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]);78 ALLOC2_INTERFACE_BEGIN("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]); 77 79 78 80 _ALLOC2_SIGNAL_OUT(out_SPR_READ_SR ,"sr",Tspr_t,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); 81 82 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 79 83 } 80 84 81 85 // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 82 86 { 83 ALLOC2_INTERFACE ("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]);87 ALLOC2_INTERFACE_BEGIN("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]); 84 88 85 89 _ALLOC2_VALACK_IN ( in_SPR_COMMIT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); … … 91 95 _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); 92 96 _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV ,"sr_ov" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); 97 98 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 93 99 } 94 100 95 101 // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 96 102 { 97 ALLOC2_INTERFACE ("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]);103 ALLOC2_INTERFACE_BEGIN("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]); 98 104 99 105 _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); … … 104 110 _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 105 111 _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 112 113 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 106 114 } 107 115 … … 109 117 { 110 118 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 111 internal_SPR_ACCESS_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; 112 internal_SPR_COMMIT_ACK = new Tcontrol_t * [_param->_nb_front_end]; 113 internal_SPR_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; 114 for (uint32_t i=0; i<_param->_nb_front_end; i++) 115 { 116 internal_SPR_COMMIT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; 117 internal_SPR_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; 118 } 119 ALLOC1(internal_SPR_ACCESS_ACK ,Tcontrol_t,_param->_nb_inst_reexecute); 120 ALLOC2(internal_SPR_COMMIT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context [it1]); 121 ALLOC2(internal_SPR_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context [it1]); 119 122 } 120 123 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp
r98 r112 59 59 60 60 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 delete [] internal_SPR_ACCESS_ACK; 62 for (uint32_t i=0; i<_param->_nb_front_end; i++) 63 { 64 delete [] internal_SPR_COMMIT_ACK [i]; 65 delete [] internal_SPR_EVENT_ACK [i]; 66 } 67 delete [] internal_SPR_COMMIT_ACK; 68 delete [] internal_SPR_EVENT_ACK; 61 DELETE1(internal_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); 62 DELETE2(internal_SPR_COMMIT_ACK ,_param->_nb_front_end,_param->_nb_context [it1]); 63 DELETE2(internal_SPR_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context [it1]); 69 64 } 70 65 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
r111 r112 76 76 public : uint32_t * _nb_reg_free ;//[nb_rename_unit] 77 77 public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_unit] 78 public : uint32_t * _size_read_counter ;//[nb_rename_unit]78 // public : uint32_t * _size_read_counter ;//[nb_rename_unit] 79 79 public : uint32_t * _nb_load_store_queue ;//[nb_rename_unit] 80 80 public : uint32_t ** _size_store_queue ;//[nb_rename_unit][nb_load_store_queue] … … 173 173 uint32_t * nb_reg_free ,//[nb_rename_unit] 174 174 uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] 175 uint32_t * size_read_counter ,//[nb_rename_unit]175 // uint32_t * size_read_counter ,//[nb_rename_unit] 176 176 uint32_t * nb_load_store_queue ,//[nb_rename_unit] 177 177 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r109 r112 55 55 // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 56 56 { 57 ALLOC2_INTERFACE ("rename",IN,WEST,_("Instruction from front_end."),_param->_nb_front_end,_param->_nb_inst_decod[it1]);57 ALLOC2_INTERFACE_BEGIN("rename",IN,WEST,_("Instruction from front_end."),_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 59 59 _ALLOC2_VALACK_IN ( in_RENAME_VAL , VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 84 84 _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 85 85 _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 86 87 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_inst_decod[it1]); 86 88 } 87 89 88 90 // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 89 91 { 90 ALLOC1_INTERFACE ("issue",OUT,EAST,_("Instruction to execute_loop"),_param->_nb_inst_issue);92 ALLOC1_INTERFACE_BEGIN("issue",OUT,EAST,_("Instruction to execute_loop"),_param->_nb_inst_issue); 91 93 92 94 ALLOC1_VALACK_OUT (out_ISSUE_VAL , VAL ); … … 111 113 ALLOC1_SIGNAL_OUT (out_ISSUE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ); 112 114 ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register ); 115 116 ALLOC1_INTERFACE_END(_param->_nb_inst_issue); 113 117 } 114 118 115 119 // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 120 { 117 ALLOC2_INTERFACE ("execute_loop",IN,EAST,_("Instruction executed, from execute_loop."),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]);121 ALLOC2_INTERFACE_BEGIN("execute_loop",IN,EAST,_("Instruction executed, from execute_loop."),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 118 122 119 123 _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL , VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); … … 129 133 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 130 134 _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 135 136 ALLOC2_INTERFACE_END(_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); 131 137 } 132 138 133 139 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 134 140 { 135 ALLOC1_INTERFACE ("insert",OUT,EAST,_("Interface with RegisterFile's stat-list (insert Re-Order-Buffer)."),_param->_sum_inst_insert);141 ALLOC1_INTERFACE_BEGIN("insert",OUT,EAST,_("Interface with RegisterFile's stat-list (insert Re-Order-Buffer)."),_param->_sum_inst_insert); 136 142 137 143 ALLOC1_VALACK_OUT (out_INSERT_VAL , VAL); … … 141 147 ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); 142 148 ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); 149 150 ALLOC1_INTERFACE_END(_param->_sum_inst_insert); 143 151 } 144 152 145 153 // // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 146 154 // { 147 // ALLOC1_INTERFACE ("retire",OUT,EAST,_("Interface with RegisterFile's stat-list (retire Re-Order-Buffer)."),_param->_sum_inst_retire);155 // ALLOC1_INTERFACE_BEGIN("retire",OUT,EAST,_("Interface with RegisterFile's stat-list (retire Re-Order-Buffer)."),_param->_sum_inst_retire); 148 156 149 157 // ALLOC1_VALACK_OUT (out_RETIRE_VAL , VAL); … … 157 165 // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); 158 166 // ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); 167 168 // ALLOC1_INTERFACE_END(_param->_sum_inst_retire); 159 169 // } 160 170 161 171 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 162 172 { 163 ALLOC1_INTERFACE ("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete);173 ALLOC1_INTERFACE_BEGIN("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete); 164 174 165 175 ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_VAL , VAL); … … 171 181 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); 172 182 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); 183 184 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); 173 185 } 174 186 175 187 // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 176 188 { 177 ALLOC_INTERFACE("commit_event",OUT,WEST,_("Commit an event (exception).")); 178 179 ALLOC_VALACK_OUT (out_COMMIT_EVENT_VAL , VAL); 180 ALLOC_VALACK_IN ( in_COMMIT_EVENT_ACK , ACK); 181 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); 182 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); 183 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); 184 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type ); 185 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 186 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 187 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); 188 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 189 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); 190 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); 189 ALLOC0_INTERFACE_BEGIN("commit_event",OUT,WEST,_("Commit an event (exception).")); 190 191 ALLOC0_VALACK_OUT(out_COMMIT_EVENT_VAL , VAL); 192 ALLOC0_VALACK_IN ( in_COMMIT_EVENT_ACK , ACK); 193 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); 194 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); 195 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); 196 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type ); 197 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 198 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 199 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); 200 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 201 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); 202 ALLOC0_SIGNAL_OUT(out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); 203 204 ALLOC0_INTERFACE_END(); 191 205 } 192 206 193 207 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 194 208 { 195 ALLOC2_INTERFACE ("event",IN,WEST,_("Event from context_state."),_param->_nb_front_end,_param->_nb_context[it1]);209 ALLOC2_INTERFACE_BEGIN("event",IN,WEST,_("Event from context_state."),_param->_nb_front_end,_param->_nb_context[it1]); 196 210 197 211 _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); … … 201 215 _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 202 216 _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 217 218 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 203 219 } 204 220 205 221 // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 206 222 { 207 ALLOC2_INTERFACE ("spr_event",IN,WEST,_("Exception : save spr and set a lot of special register."),_param->_nb_front_end,_param->_nb_context[it1]);223 ALLOC2_INTERFACE_BEGIN("spr_event",IN,WEST,_("Exception : save spr and set a lot of special register."),_param->_nb_front_end,_param->_nb_context[it1]); 208 224 209 225 _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); … … 214 230 _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 215 231 _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 232 233 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 216 234 } 217 235 218 236 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 219 237 { 220 ALLOC2_INTERFACE ("nb_inst",OUT,WEST,_("Internal number instruction."),_param->_nb_front_end,_param->_nb_context[it1]);238 ALLOC2_INTERFACE_BEGIN("nb_inst",OUT,WEST,_("Internal number instruction."),_param->_nb_front_end,_param->_nb_context[it1]); 221 239 222 240 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); 223 241 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); 224 242 _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end,_param->_nb_context[it1]); 243 244 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 225 245 } 226 246 227 247 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 228 248 { 229 ALLOC2_INTERFACE ("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]);249 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 230 250 231 251 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 232 252 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 233 253 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 254 255 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 234 256 } 235 257 236 258 // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 237 259 { 238 ALLOC2_INTERFACE ("spr",OUT,WEST,_("SPR"),_param->_nb_front_end,_param->_nb_context[it1]);260 ALLOC2_INTERFACE_BEGIN("spr",OUT,WEST,_("SPR"),_param->_nb_front_end,_param->_nb_context[it1]); 239 261 240 262 _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 241 263 _ALLOC2_SIGNAL_OUT(out_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 264 265 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 242 266 } 243 267 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
r108 r112 117 117 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); 118 118 119 DELETE _SIGNAL(out_COMMIT_EVENT_VAL , 1);120 DELETE _SIGNAL( in_COMMIT_EVENT_ACK , 1);121 DELETE _SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,_param->_size_front_end_id );122 DELETE _SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id );123 DELETE _SIGNAL(out_COMMIT_EVENT_DEPTH ,_param->_size_depth );124 DELETE _SIGNAL(out_COMMIT_EVENT_TYPE ,_param->_size_event_type );125 DELETE _SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,1 );126 DELETE _SIGNAL(out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data );127 DELETE _SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 );128 DELETE _SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data );129 DELETE _SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 );130 DELETE _SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_general_data );119 DELETE0_SIGNAL(out_COMMIT_EVENT_VAL , 1); 120 DELETE0_SIGNAL( in_COMMIT_EVENT_ACK , 1); 121 DELETE0_SIGNAL(out_COMMIT_EVENT_FRONT_END_ID ,_param->_size_front_end_id ); 122 DELETE0_SIGNAL(out_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id ); 123 DELETE0_SIGNAL(out_COMMIT_EVENT_DEPTH ,_param->_size_depth ); 124 DELETE0_SIGNAL(out_COMMIT_EVENT_TYPE ,_param->_size_event_type ); 125 DELETE0_SIGNAL(out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); 126 DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); 127 DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); 128 DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); 129 DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); 130 DELETE0_SIGNAL(out_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_general_data ); 131 131 132 132 DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
r111 r112 63 63 uint32_t * nb_reg_free ,//[nb_rename_unit] 64 64 uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] 65 uint32_t * size_read_counter ,//[nb_rename_unit]65 // uint32_t * size_read_counter ,//[nb_rename_unit] 66 66 uint32_t * nb_load_store_queue ,//[nb_rename_unit] 67 67 uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] … … 119 119 _nb_reg_free = nb_reg_free ; 120 120 _nb_rename_unit_bank = nb_rename_unit_bank ; 121 _size_read_counter = size_read_counter ;121 // _size_read_counter = size_read_counter ; 122 122 _nb_load_store_queue = nb_load_store_queue ; 123 123 _size_store_queue = size_store_queue ; … … 238 238 _nb_special_register [i], 239 239 _nb_reg_free [i], 240 _nb_rename_unit_bank [i], 241 _size_read_counter [i] 240 _nb_rename_unit_bank [i]// , 241 // _size_read_counter [i] 242 242 243 ); 243 244 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp
r97 r112 81 81 for (uint32_t i=0; i<_nb_rename_unit; ++i) 82 82 str+= toString(MSG_INFORMATION)+" * nb_rename_unit_bank ["+toString(i)+"] : "+toString<uint32_t >(_nb_rename_unit_bank [i])+"\n";//[nb_rename_unit] 83 for (uint32_t i=0; i<_nb_rename_unit; ++i)84 str+= toString(MSG_INFORMATION)+" * size_read_counter ["+toString(i)+"] : "+toString<uint32_t >(_size_read_counter [i])+"\n";//[nb_rename_unit]83 // for (uint32_t i=0; i<_nb_rename_unit; ++i) 84 // str+= toString(MSG_INFORMATION)+" * size_read_counter ["+toString(i)+"] : "+toString<uint32_t >(_size_read_counter [i])+"\n";//[nb_rename_unit] 85 85 for (uint32_t i=0; i<_nb_rename_unit; ++i) 86 86 str+= toString(MSG_INFORMATION)+" * nb_load_store_queue ["+toString(i)+"] : "+toString<uint32_t >(_nb_load_store_queue [i])+"\n";//[nb_rename_unit]
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