- Timestamp:
- Oct 20, 2009, 8:52:15 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 4 added
- 34 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
r110 r136 72 72 public : SC_OUT(Tcontrol_t ) *** out_IFETCH_ACK ;//[nb_context][nb_inst_fetch] 73 73 public : SC_IN (Tinstruction_t ) *** in_IFETCH_INSTRUCTION ;//[nb_context][nb_inst_fetch] 74 public : SC_IN (Tcontext_t ) ** in_IFETCH_CONTEXT_ID ;//[nb_context]75 public : SC_IN (Tgeneral_address_t ) ** in_IFETCH_ADDRESS ;//[nb_context]76 //public : SC_IN (Tgeneral_address_t ) ** in_IFETCH_ADDRESS_NEXT ;//[nb_context]77 public : SC_IN (Tinst_ifetch_ptr_t ) ** in_IFETCH_INST_IFETCH_PTR ;//[nb_context]78 public : SC_IN (Tbranch_state_t ) ** in_IFETCH_BRANCH_STATE ;//[nb_context]79 public : SC_IN (Tprediction_ptr_t ) ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context]80 public : SC_IN (Texception_t ) ** in_IFETCH_EXCEPTION ;//[nb_context]74 public : SC_IN (Tcontext_t ) *** in_IFETCH_CONTEXT_ID ;//[nb_context][nb_inst_fetch] 75 public : SC_IN (Tgeneral_address_t ) *** in_IFETCH_ADDRESS ;//[nb_context][nb_inst_fetch] 76 //public : SC_IN (Tgeneral_address_t ) *** in_IFETCH_ADDRESS_NEXT ;//[nb_context][nb_inst_fetch] 77 //public : SC_IN (Tinst_ifetch_ptr_t ) *** in_IFETCH_INST_IFETCH_PTR ;//[nb_context][nb_inst_fetch] 78 public : SC_IN (Tbranch_state_t ) *** in_IFETCH_BRANCH_STATE ;//[nb_context][nb_inst_fetch] 79 public : SC_IN (Tprediction_ptr_t ) *** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context][nb_inst_fetch] 80 public : SC_IN (Texception_t ) *** in_IFETCH_EXCEPTION ;//[nb_context][nb_inst_fetch] 81 81 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 82 82 public : SC_OUT(Tcontrol_t ) ** out_DECOD_VAL ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp
r132 r136 94 94 { 95 95 for (uint32_t j=0; j<_param->_nb_inst_fetch [i]; j++) 96 sensitive << (*(in_IFETCH_VAL [i][j])) 97 << (*(in_IFETCH_INSTRUCTION [i][j])); 98 sensitive << (*(in_IFETCH_ADDRESS [i])) 99 // << (*(in_IFETCH_ADDRESS_NEXT [i])) 100 << (*(in_IFETCH_BRANCH_STATE [i])) 101 << (*(in_IFETCH_EXCEPTION [i])) 102 << (*(in_CONTEXT_DECOD_ENABLE [i])); 103 if (_param->_have_port_context_id) 104 sensitive << (*(in_IFETCH_CONTEXT_ID [i])); 105 if (_param->_have_port_depth) 106 sensitive << (*(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i])); 107 sensitive << (*(in_CONTEXT_DEPTH_VAL [i])); 96 { 97 sensitive << (*(in_IFETCH_VAL [i][j])) 98 << (*(in_IFETCH_INSTRUCTION [i][j])) 99 << (*(in_IFETCH_ADDRESS [i][j])) 100 // << (*(in_IFETCH_ADDRESS_NEXT [i][j])) 101 << (*(in_IFETCH_BRANCH_STATE [i][j])) 102 << (*(in_IFETCH_EXCEPTION [i][j])); 103 104 if (_param->_have_port_context_id) 105 sensitive << (*(in_IFETCH_CONTEXT_ID [i][j])); 106 if (_param->_have_port_depth) 107 sensitive << (*(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i][j])); 108 // if (_param->_have_port_inst_ifetch_ptr) 109 // sensitive << (*(in_IFETCH_INST_IFETCH_PTR [i][j])); 110 } 111 sensitive << (*(in_CONTEXT_DECOD_ENABLE [i])) 112 << (*(in_CONTEXT_DEPTH_VAL [i])); 108 113 if (_param->_have_port_depth) 109 114 sensitive << (*(in_CONTEXT_DEPTH [i])); 110 if (_param->_have_port_inst_ifetch_ptr)111 sensitive << (*(in_IFETCH_INST_IFETCH_PTR [i]));112 115 } 113 116 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
r112 r136 61 61 62 62 63 _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); 64 _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); 65 _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); 63 _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); 64 _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); 65 _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 66 _ALLOC2_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 67 _ALLOC2_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address,_param->_nb_context, _param->_nb_inst_fetch[it1]); 68 // _ALLOC2_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address,_param->_nb_context, _param->_nb_inst_fetch[it1]); 69 // _ALLOC2_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 70 _ALLOC2_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 71 _ALLOC2_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 72 _ALLOC2_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 66 73 67 74 ALLOC2_INTERFACE_END(_param->_nb_context, _param->_nb_inst_fetch[it1]); 68 }69 {70 ALLOC1_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context);71 72 73 ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );74 ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address );75 // ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address );76 ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr );77 ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state );78 ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth );79 ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);80 81 ALLOC1_INTERFACE_END(_param->_nb_context);82 75 } 83 76 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
r112 r136 29 29 delete in_NRESET; 30 30 31 DELETE2_SIGNAL( in_IFETCH_VAL , _param->_nb_context, _param->_nb_inst_fetch[it1],1); 32 DELETE2_SIGNAL(out_IFETCH_ACK , _param->_nb_context, _param->_nb_inst_fetch[it1],1); 33 DELETE2_SIGNAL( in_IFETCH_INSTRUCTION, _param->_nb_context, _param->_nb_inst_fetch[it1],_param->_size_instruction); 34 35 DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID , _param->_nb_context,_param->_size_context_id ); 36 DELETE1_SIGNAL(in_IFETCH_ADDRESS , _param->_nb_context,_param->_size_instruction_address ); 37 // DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT , _param->_nb_context,_param->_size_instruction_address ); 38 DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR , _param->_nb_context,_param->_size_inst_ifetch_ptr ); 39 DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE , _param->_nb_context,_param->_size_branch_state ); 40 DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID, _param->_nb_context,_param->_size_depth ); 41 DELETE1_SIGNAL(in_IFETCH_EXCEPTION , _param->_nb_context,_param->_size_exception_ifetch); 31 DELETE2_SIGNAL( in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1],1); 32 DELETE2_SIGNAL(out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1],1); 33 DELETE2_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction); 34 DELETE2_SIGNAL( in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_context_id ); 35 DELETE2_SIGNAL( in_IFETCH_ADDRESS ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction_address ); 36 // DELETE2_SIGNAL( in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction_address ); 37 // DELETE2_SIGNAL( in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_inst_ifetch_ptr ); 38 DELETE2_SIGNAL( in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_branch_state ); 39 DELETE2_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_depth ); 40 DELETE2_SIGNAL( in_IFETCH_EXCEPTION ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_exception_ifetch); 42 41 43 42 DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r135 r136 99 99 ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack 100 100 101 Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x] )+y;101 Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]); 102 102 103 103 _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); … … 132 132 133 133 // Test IFetch exception 134 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x] );134 Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]); 135 135 136 136 if (ifetch_exception == EXCEPTION_IFETCH_NONE) … … 232 232 } 233 233 234 Tbranch_state_t ifetch_branch_state = PORT_READ(in_IFETCH_BRANCH_STATE [x][y]); 234 235 if (_param->_have_port_context_id) 235 236 PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); 236 PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); 237 PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); 237 // PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); 238 PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],ifetch_branch_state != BRANCH_STATE_NONE); 239 240 PORT_WRITE(out_PREDICT_BRANCH_STATE [i],ifetch_branch_state); 238 241 if (_param->_have_port_depth) 239 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x] ));242 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y])); 240 243 PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); 241 244 // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h
r123 r136 56 56 private : counter_t * _stat_use_queue; 57 57 58 private : counter_t * _stat_ sum_inst_enable;59 private : counter_t * _stat_ sum_transaction_decod_in;60 private : counter_t * _stat_ average_occupation_bundle;58 private : counter_t * _stat_decode_in_empty ; 59 private : counter_t * _stat_decode_in_full ; 60 private : counter_t * _stat_decode_in_average; 61 61 #endif 62 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_multi_fifo_transition.cpp
r124 r136 51 51 { 52 52 #ifdef STATISTICS 53 bool find = false; 54 #endif 53 uint32_t nb_decod_in = 0; 54 #endif 55 55 56 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 56 57 if (PORT_READ(in_DECOD_IN_VAL [i]) and internal_DECOD_IN_ACK[i]) 57 58 { 58 59 log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_IN [%d]"),i); 59 60 61 #ifdef STATISTICS 62 nb_decod_in ++; 63 #endif 64 60 65 // Create entry 61 66 decod_queue_entry_t * entry = new decod_queue_entry_t (1); 62 67 reg_QUEUE[reg_NUM_BANK_TAIL].push_back(entry); 63 68 64 #ifdef STATISTICS65 find = true;66 if (usage_is_set(_usage,USE_STATISTICS))67 (*_stat_sum_inst_enable) ++;68 #endif69 70 69 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_IN_CONTEXT_ID [i]):0; 71 70 … … 107 106 108 107 #ifdef STATISTICS 109 if (usage_is_set(_usage,USE_STATISTICS)) 110 if (find) 111 (*_stat_sum_transaction_decod_in) ++; 108 if (usage_is_set(_usage,USE_STATISTICS)) 109 { 110 if (nb_decod_in > 0) 111 { 112 if (nb_decod_in == _param->_nb_inst_decod) 113 (*_stat_decode_in_full) ++; 114 else 115 (*_stat_decode_in_average) += nb_decod_in; 116 } 117 else 118 { 119 (*_stat_decode_in_empty) ++; 120 } 121 } 112 122 #endif 113 123 } … … 208 218 { 209 219 for (uint32_t i=0; i<_param->_nb_bank; ++i) 210 *(_stat_use_queue) += reg_QUEUE[i].size();220 (*_stat_use_queue) += reg_QUEUE[i].size(); 211 221 for (uint32_t i=0; i<_param->_nb_context; i++) 212 *(_stat_nb_inst [i]) += reg_NB_INST [i];222 (*_stat_nb_inst [i]) += reg_NB_INST [i]; 213 223 } 214 224 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_transition.cpp
r123 r136 46 46 //-----[ DECOD_IN ]--------------------------------------------------- 47 47 //-------------------------------------------------------------------- 48 { 48 49 decod_queue_entry_t * entry = NULL; 50 51 #ifdef STATISTICS 52 uint32_t nb_decod_in = 0; 53 #endif 54 49 55 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 50 56 { … … 58 64 entry = new decod_queue_entry_t (_param->_nb_inst_decod); 59 65 reg_QUEUE->push_back(entry); 60 61 #ifdef STATISTICS62 if (usage_is_set(_usage,USE_STATISTICS))63 (*_stat_sum_transaction_decod_in) ++;64 #endif65 66 } 66 67 67 68 #ifdef STATISTICS 68 if (usage_is_set(_usage,USE_STATISTICS)) 69 (*_stat_sum_inst_enable) ++; 69 nb_decod_in ++; 70 70 #endif 71 71 … … 106 106 } 107 107 } 108 109 #ifdef STATISTICS 110 if (usage_is_set(_usage,USE_STATISTICS)) 111 { 112 if (nb_decod_in > 0) 113 { 114 if (nb_decod_in == _param->_nb_inst_decod) 115 (*_stat_decode_in_full) ++; 116 else 117 (*_stat_decode_in_average) += nb_decod_in; 118 } 119 else 120 { 121 (*_stat_decode_in_empty) ++; 122 } 123 } 124 #endif 125 } 108 126 109 127 //-------------------------------------------------------------------- … … 217 235 if (usage_is_set(_usage,USE_STATISTICS)) 218 236 { 219 *(_stat_use_queue) += reg_QUEUE->size();237 (*_stat_use_queue) += reg_QUEUE->size(); 220 238 for (uint32_t i=0; i<_param->_nb_context; i++) 221 *(_stat_nb_inst [i]) += reg_NB_INST [i];239 (*_stat_nb_inst [i]) += reg_NB_INST [i]; 222 240 } 223 241 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_statistics_allocation.cpp
r110 r136 17 17 namespace decod_queue { 18 18 19 20 19 #undef FUNCTION 21 20 #define FUNCTION "Decod_queue::statistics_allocation" … … 29 28 param_statistics); 30 29 31 _stat_ sum_transaction_decod_in = _stat->create_variable("sum_transaction_decod_in");32 _stat_ sum_inst_enable = _stat->create_variable("sum_inst_enable");33 _stat_ average_occupation_bundle= _stat->create_counter ("average_occupation_bundle", "", "Occupation average of instruction's bundle.");30 _stat_decode_in_empty = _stat->create_counter ("decode_in_empty" , "", "Number cycle with no input instruction."); 31 _stat_decode_in_full = _stat->create_counter ("decode_in_full" , "", toString("Number cycle with full input instruction (%d).",_param->_nb_inst_decod)); 32 _stat_decode_in_average = _stat->create_counter ("decode_in_average", "", "Average decod instruction."); 34 33 35 _stat->create_expr ("average_occupation_bundle" ,"/ sum_inst_enable sum_transaction_decod_in");36 _stat->create_expr_percent ("percent_ occupation_bundle" ,"average_occupation_bundle", toString(_param->_nb_inst_decod),"Percent of instruction's bundle occupation.");34 _stat->create_expr_average_by_cycle("average_decod_in", toString("+ * decode_in_full %d decode_in_average",_param->_nb_inst_decod), "", "Average instruction from decode unit"); 35 _stat->create_expr_percent ("percent_decod_in" ,"average_decod_in", toString(_param->_nb_inst_decod),"Percent of instruction's bundle occupation."); 37 36 38 37 _stat_use_queue = _stat->create_variable ("use_queue"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h
r123 r136 70 70 public : SC_OUT(Tcontrol_t ) *** out_IFETCH_ACK ;//[nb_context][nb_inst_fetch] 71 71 public : SC_IN (Tinstruction_t ) *** in_IFETCH_INSTRUCTION ;//[nb_context][nb_inst_fetch] 72 public : SC_IN (Tcontext_t ) ** in_IFETCH_CONTEXT_ID ;//[nb_context]73 public : SC_IN (Tgeneral_address_t ) ** in_IFETCH_ADDRESS ;//[nb_context]74 //public : SC_IN (Tgeneral_address_t ) ** in_IFETCH_ADDRESS_NEXT ;//[nb_context]75 public : SC_IN (Tinst_ifetch_ptr_t ) ** in_IFETCH_INST_IFETCH_PTR ;//[nb_context]76 public : SC_IN (Tbranch_state_t ) ** in_IFETCH_BRANCH_STATE ;//[nb_context]77 public : SC_IN (Tprediction_ptr_t ) ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context]78 public : SC_IN (Texception_t ) ** in_IFETCH_EXCEPTION ;//[nb_context]72 public : SC_IN (Tcontext_t ) *** in_IFETCH_CONTEXT_ID ;//[nb_context][nb_inst_fetch] 73 public : SC_IN (Tgeneral_address_t ) *** in_IFETCH_ADDRESS ;//[nb_context][nb_inst_fetch] 74 //public : SC_IN (Tgeneral_address_t ) *** in_IFETCH_ADDRESS_NEXT ;//[nb_context][nb_inst_fetch] 75 //public : SC_IN (Tinst_ifetch_ptr_t ) *** in_IFETCH_INST_IFETCH_PTR ;//[nb_context][nb_inst_fetch] 76 public : SC_IN (Tbranch_state_t ) *** in_IFETCH_BRANCH_STATE ;//[nb_context][nb_inst_fetch] 77 public : SC_IN (Tprediction_ptr_t ) *** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context][nb_inst_fetch] 78 public : SC_IN (Texception_t ) *** in_IFETCH_EXCEPTION ;//[nb_context][nb_inst_fetch] 79 79 80 80 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp
r123 r136 15 15 namespace front_end { 16 16 namespace decod_unit { 17 18 19 17 20 18 #undef FUNCTION … … 60 58 ALLOC2_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context, _param->_nb_inst_fetch[it1]); 61 59 62 _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); 63 _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); 64 _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); 60 _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); 61 _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); 62 _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 63 _ALLOC2_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 64 _ALLOC2_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address,_param->_nb_context, _param->_nb_inst_fetch[it1]); 65 // _ALLOC2_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address,_param->_nb_context, _param->_nb_inst_fetch[it1]); 66 // _ALLOC2_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 67 _ALLOC2_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 68 _ALLOC2_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 69 _ALLOC2_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch ,_param->_nb_context, _param->_nb_inst_fetch[it1]); 65 70 66 71 ALLOC2_INTERFACE_END(_param->_nb_context, _param->_nb_inst_fetch[it1]); 67 }68 {69 ALLOC1_INTERFACE_BEGIN("ifetch", IN, WEST, _("Instruction's bundle"), _param->_nb_context);70 71 ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );72 ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address );73 // ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address );74 ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr );75 ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state );76 ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth );77 ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);78 79 ALLOC1_INTERFACE_END(_param->_nb_context);80 72 } 81 73 … … 261 253 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_INSTRUCTION", 262 254 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_INSTRUCTION"); 255 if (_param->_have_port_context_id) 256 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" , 257 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); 258 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_ADDRESS" , 259 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); 260 // PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , 261 // dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); 262 // if (_param->_have_port_inst_ifetch_ptr) 263 // PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_INST_IFETCH_PTR" , 264 // dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_INST_IFETCH_PTR" ); 265 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_BRANCH_STATE" , 266 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_BRANCH_STATE" ); 267 if (_param->_have_port_depth) 268 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID", 269 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID"); 270 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_"+toString(j)+"_EXCEPTION" , 271 dest, "in_IFETCH_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); 263 272 } 264 265 #ifdef POSITION 266 _component->interface_map (src ,"ifetch_"+toString(i), 267 dest,"ifetch_"+toString(i)); 268 #endif 269 270 if (_param->_have_port_context_id) 271 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_CONTEXT_ID" , 272 dest, "in_IFETCH_"+toString(i)+"_CONTEXT_ID" ); 273 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_ADDRESS" , 274 dest, "in_IFETCH_"+toString(i)+"_ADDRESS" ); 275 // PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_ADDRESS_NEXT" , 276 // dest, "in_IFETCH_"+toString(i)+"_ADDRESS_NEXT" ); 277 if (_param->_have_port_inst_ifetch_ptr) 278 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_INST_IFETCH_PTR" , 279 dest, "in_IFETCH_"+toString(i)+"_INST_IFETCH_PTR" ); 280 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_BRANCH_STATE" , 281 dest, "in_IFETCH_"+toString(i)+"_BRANCH_STATE" ); 282 if (_param->_have_port_depth) 283 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID", 284 dest, "in_IFETCH_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); 285 PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_EXCEPTION" , 286 dest, "in_IFETCH_"+toString(i)+"_EXCEPTION" ); 273 287 274 } 288 275 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
r128 r136 28 28 delete in_NRESET; 29 29 30 DELETE2_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1],1); 31 DELETE2_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1],1); 32 DELETE2_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1],_param->_size_instruction); 33 34 DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id ); 35 DELETE1_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); 36 // DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); 37 DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr ); 38 DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_size_branch_state ); 39 DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context,_param->_size_depth ); 40 DELETE1_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context,_param->_size_exception_ifetch); 30 DELETE2_SIGNAL( in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1],1); 31 DELETE2_SIGNAL(out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1],1); 32 DELETE2_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction); 33 DELETE2_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_context_id ); 34 DELETE2_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction_address); 35 // DELETE2_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction_address); 36 // DELETE2_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_inst_ifetch_ptr ); 37 DELETE2_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_branch_state ); 38 DELETE2_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_depth ); 39 DELETE2_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_exception_ifetch ); 41 40 42 41 DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r128 r136 70 70 log_printf(TRACE,Address_management,FUNCTION," * PREDICT"); 71 71 72 bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; 72 bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; 73 Tbranch_state_t branch_state = PORT_READ(in_PREDICT_BRANCH_STATE ); 74 Tprediction_ptr_t branch_update_prediction_id = (_param->_have_port_depth )?PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID):0; 75 Tinst_ifetch_ptr_t inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_PREDICT_INST_IFETCH_PTR ):0; 76 77 log_printf(TRACE,Address_management,FUNCTION," * branch_is_current : %d",branch_is_current ); 78 log_printf(TRACE,Address_management,FUNCTION," * branch_state : %d",branch_state ); 79 log_printf(TRACE,Address_management,FUNCTION," * branch_update_prediction_id : %d",branch_update_prediction_id); 80 log_printf(TRACE,Address_management,FUNCTION," * inst_ifetch_ptr : %d",inst_ifetch_ptr ); 81 73 82 if (branch_is_current) 74 83 { 75 if (_param->_have_port_inst_ifetch_ptr) 76 reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); 77 reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); 78 if (_param->_have_port_depth) 79 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); 84 reg_PC_CURRENT_INST_IFETCH_PTR = inst_ifetch_ptr ; 85 reg_PC_CURRENT_BRANCH_STATE = branch_state ; 86 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = branch_update_prediction_id; 80 87 } 81 88 else 82 89 { 83 if (_param->_have_port_inst_ifetch_ptr) 84 reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); 85 reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); 86 if (_param->_have_port_depth) 87 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); 90 reg_PC_NEXT_INST_IFETCH_PTR = inst_ifetch_ptr ; 91 reg_PC_NEXT_BRANCH_STATE = branch_state ; 92 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = branch_update_prediction_id; 88 93 } 89 94 … … 161 166 } 162 167 163 // if (not reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)164 168 if (reg_PC_NEXT_NEXT_VAL and not reg_PC_NEXT_VAL) 165 169 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h
r131 r136 84 84 public : SC_IN (Tcontrol_t ) ** in_DECOD_ACK ;//[nb_instruction] 85 85 public : SC_OUT(Tinstruction_t ) ** out_DECOD_INSTRUCTION ;//[nb_instruction] 86 public : SC_OUT(Tgeneral_address_t ) * out_DECOD_ADDRESS ; 87 public : SC_OUT(Tinst_ifetch_ptr_t ) * out_DECOD_INST_IFETCH_PTR ; 88 public : SC_OUT(Tbranch_state_t ) * out_DECOD_BRANCH_STATE ; 89 public : SC_OUT(Tprediction_ptr_t ) * out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 90 public : SC_OUT(Texception_t ) * out_DECOD_EXCEPTION ; 86 public : SC_OUT(Tgeneral_address_t ) ** out_DECOD_ADDRESS ; 87 public : SC_OUT(Tbranch_state_t ) ** out_DECOD_BRANCH_STATE ; 88 public : SC_OUT(Tprediction_ptr_t ) ** out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 89 public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION ; 90 //public : SC_OUT(Tgeneral_address_t ) * out_DECOD_ADDRESS ; 91 //public : SC_OUT(Tinst_ifetch_ptr_t ) * out_DECOD_INST_IFETCH_PTR ; 92 //public : SC_OUT(Tbranch_state_t ) * out_DECOD_BRANCH_STATE ; 93 //public : SC_OUT(Tprediction_ptr_t ) * out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 94 //public : SC_OUT(Texception_t ) * out_DECOD_EXCEPTION ; 91 95 92 96 // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 110 114 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 111 115 private : Tcontrol_t internal_ADDRESS_ACK ; 112 private : Tcontrol_t * internal_DECOD_VAL ; 116 private : Tcontrol_t * internal_DECOD_VAL ;//[nb_instruction] 117 private : uint32_t * internal_DECOD_PTR ;//[nb_instruction] Only queue_scheme == full_assoc 118 private : uint32_t * internal_DECOD_SLOT ;//[nb_instruction] Only queue_scheme == full_assoc 113 119 private : Tcontrol_t internal_ICACHE_RSP_ACK ; 114 120 private : Tcontrol_t internal_EVENT_RESET_ACK; 121 122 123 124 // function pointer 125 public : void (morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::*function_transition ) (void); 126 public : void (morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::*function_genMoore ) (void); 115 127 #endif 116 128 … … 146 158 #ifdef SYSTEMC 147 159 public : void constant (void); 148 public : void transition (void); 149 public : void genMoore (void); 160 161 public : void transition (void); 162 public : void genMoore (void); 163 164 public : void function_no_assoc_transition (void); 165 public : void function_no_assoc_genMoore (void); 166 167 public : void function_full_assoc_transition (void); 168 public : void function_full_assoc_genMoore (void); 150 169 #endif 151 170 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h
r109 r136 11 11 #include "Common/include/Debug.h" 12 12 #include "Behavioural/include/Parameters.h" 13 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h" 13 14 14 15 namespace morpheo { … … 24 25 { 25 26 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _size_queue ; 27 public : uint32_t _nb_instruction ; 28 //public : uint32_t _size_branch_update_prediction ; 29 //public : uint32_t _size_general_data ; 30 public : uint32_t _nb_instruction_in_queue ; 31 32 //public : uint32_t _size_queue_ptr ; 33 //public : uint32_t _size_instruction_ptr ; 34 35 //public : bool _have_port_queue_ptr ; 36 //public : bool _have_port_instruction_ptr ; 37 //public : bool _have_port_branch_update_prediction_id; 27 public : uint32_t _size_queue ; 28 public : Tifetch_queue_scheme_t _queue_scheme ; 29 public : uint32_t _nb_instruction ; 30 //public : uint32_t _size_branch_update_prediction ; 31 //public : uint32_t _size_general_data ; 32 public : uint32_t _nb_instruction_in_queue ; 33 34 //public : uint32_t _size_queue_ptr ; 35 //public : uint32_t _size_instruction_ptr ; 36 37 //public : bool _have_port_queue_ptr ; 38 //public : bool _have_port_instruction_ptr ; 39 //public : bool _have_port_branch_update_prediction_id; 38 40 39 41 //-----[ methods ]----------------------------------------------------------- 40 public : Parameters (uint32_t size_queue , 41 uint32_t nb_instruction , 42 uint32_t size_branch_update_prediction, 43 uint32_t size_general_data , 44 bool is_toplevel=false); 42 public : Parameters (uint32_t size_queue , 43 Tifetch_queue_scheme_t queue_scheme , 44 uint32_t nb_instruction , 45 uint32_t size_branch_update_prediction, 46 uint32_t size_general_data , 47 bool is_toplevel=false); 45 48 // public : Parameters (Parameters & param) ; 46 49 public : ~Parameters () ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
r135 r136 18 18 namespace ifetch_unit { 19 19 namespace ifetch_queue { 20 21 typedef enum 22 { 23 IFETCH_QUEUE_SCHEME_NO_ASSOC // Read only head 24 ,IFETCH_QUEUE_SCHEME_FULL_ASSOC // Scan all slot 25 } Tifetch_queue_scheme_t; 20 26 21 27 typedef enum … … 60 66 }; // end namespace core 61 67 }; // end namespace behavioural 68 69 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t>(const morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t& x) 70 { 71 switch (x) 72 { 73 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_NO_ASSOC : return "no_assoc" ; break; 74 case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_FULL_ASSOC : return "full_assoc"; break; 75 default : return ""; break; 76 } 77 }; 78 79 template<> inline morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t fromString<morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t>(const std::string& x) 80 { 81 if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_NO_ASSOC ))) == 0) or 82 (x.compare("no_assoc") == 0)) 83 return morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_NO_ASSOC; 84 if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_FULL_ASSOC))) == 0) or 85 (x.compare("full_assoc") == 0)) 86 return morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_SCHEME_FULL_ASSOC; 87 88 throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\"")); 89 }; 62 90 63 91 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t& x) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp
r132 r136 74 74 if (usage_is_set(_usage,USE_SYSTEMC)) 75 75 { 76 // Function pointer 77 switch (_param->_queue_scheme) 78 { 79 case IFETCH_QUEUE_SCHEME_NO_ASSOC : 80 { 81 function_transition = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_no_assoc_transition ; 82 function_genMoore = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_no_assoc_genMoore ; 83 84 break; 85 } 86 case IFETCH_QUEUE_SCHEME_FULL_ASSOC : 87 { 88 function_transition = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_full_assoc_transition ; 89 function_genMoore = &morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue::function_full_assoc_genMoore ; 90 91 break; 92 } 93 default : 94 { 95 break; 96 } 97 } 98 76 99 log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - constant"),_name.c_str()); 77 100 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp
r112 r136 84 84 ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); 85 85 ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); 86 ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction); 86 ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); 87 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 88 ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 89 ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 90 ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 87 91 88 92 ALLOC1_INTERFACE_END(_param->_nb_instruction); 89 93 } 90 {91 ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));94 // { 95 // ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage.")); 92 96 93 ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address );94 ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );95 ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state );96 ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth );97 ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);97 // ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); 98 // ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); 99 // ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); 100 // ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); 101 // ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 98 102 99 ALLOC0_INTERFACE_END();100 }103 // ALLOC0_INTERFACE_END(); 104 // } 101 105 102 106 // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 132 136 if (usage_is_set(_usage,USE_SYSTEMC)) 133 137 { 134 ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction); 135 138 ALLOC1(internal_DECOD_VAL ,Tcontrol_t,_param->_nb_instruction); 139 if (_param->_queue_scheme == IFETCH_QUEUE_SCHEME_FULL_ASSOC) 140 { 141 ALLOC1(internal_DECOD_PTR ,uint32_t ,_param->_nb_instruction); 142 ALLOC1(internal_DECOD_SLOT,uint32_t ,_param->_nb_instruction); 143 } 144 136 145 _queue = new ifetch_queue_entry_t * [_param->_size_queue]; 137 146 for (uint32_t i=0;i<_param->_size_queue; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp
r123 r136 41 41 DELETE1_SIGNAL( in_DECOD_ACK ,_param->_nb_instruction,1); 42 42 DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_nb_instruction,_param->_size_instruction); 43 DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address); 44 DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr ); 45 DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state ); 46 DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth ); 47 DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); 43 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_instruction,_param->_size_instruction_address); 44 DELETE1_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_nb_instruction,_param->_size_branch_state); 45 DELETE1_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_instruction,_param->_size_depth); 46 DELETE1_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_instruction,_param->_size_exception_ifetch); 47 // DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address); 48 // DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr ); 49 // DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state ); 50 // DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth ); 51 // DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); 48 52 49 53 DELETE0_SIGNAL( in_ICACHE_RSP_VAL ,1); … … 60 64 if (usage_is_set(_usage,USE_SYSTEMC)) 61 65 { 62 DELETE1(internal_DECOD_VAL,_param->_nb_instruction); 66 DELETE1(internal_DECOD_VAL ,_param->_nb_instruction); 67 if (_param->_queue_scheme == IFETCH_QUEUE_SCHEME_FULL_ASSOC) 68 { 69 DELETE1(internal_DECOD_PTR ,_param->_nb_instruction); 70 DELETE1(internal_DECOD_SLOT,_param->_nb_instruction); 71 } 63 72 64 73 for (uint32_t i=0;i<_param->_size_queue; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp
r132 r136 24 24 log_function(Ifetch_queue,FUNCTION,_name.c_str()); 25 25 26 if (PORT_READ(in_NRESET)) 27 { 28 // ========================================================== 29 // =====[ ADDRESS ]========================================== 30 // ========================================================== 31 { 32 internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY); 33 34 log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS_ACK : %d",internal_ADDRESS_ACK); 35 36 if (_param->_have_port_ifetch_queue_ptr) 37 PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); 38 } 39 40 // ========================================================== 41 // =====[ DECOD ]============================================ 42 // ========================================================== 43 { 44 bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP); 45 46 for (uint32_t i=0; i<_param->_nb_instruction; i++) 47 { 48 internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i]; 49 50 log_printf(TRACE,Ifetch_queue,FUNCTION," * DECOD_VAL [%d] : %d",i,internal_DECOD_VAL [i]); 51 52 PORT_WRITE(out_DECOD_INSTRUCTION [i], _queue[reg_PTR_READ]->_instruction [i]); 53 } 54 55 PORT_WRITE(out_DECOD_ADDRESS , _queue[reg_PTR_READ]->_address ); 56 if (_param->_have_port_inst_ifetch_ptr) 57 PORT_WRITE(out_DECOD_INST_IFETCH_PTR , _queue[reg_PTR_READ]->_inst_ifetch_ptr ); 58 PORT_WRITE(out_DECOD_BRANCH_STATE , _queue[reg_PTR_READ]->_branch_state ); 59 if (_param->_have_port_depth) 60 PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id); 61 PORT_WRITE(out_DECOD_EXCEPTION , _queue[reg_PTR_READ]->_exception ); 62 } 63 } 64 else 65 { 66 // Reset 67 internal_ADDRESS_ACK = 0; 68 for (uint32_t i=0; i<_param->_nb_instruction; i++) 69 internal_DECOD_VAL [i] = 0; 70 71 } 72 73 // Write Output 74 PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); 75 for (uint32_t i=0; i<_param->_nb_instruction; i++) 76 PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]); 26 (this->*function_genMoore) (); 77 27 78 28 log_end(Ifetch_queue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
r128 r136 25 25 log_function(Ifetch_queue,FUNCTION,_name.c_str()); 26 26 27 if (PORT_READ(in_NRESET) == 0) 28 { 29 reg_PTR_READ = 0; 30 reg_PTR_WRITE = 0; 31 32 for (uint32_t i=0; i<_param->_size_queue; i++) 33 { 34 _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; 35 _queue [i]->_address = 0; // not necessary 36 _queue [i]->_inst_ifetch_ptr = 0; // not necessary 37 _queue [i]->_branch_state = 0; // not necessary 38 _queue [i]->_branch_update_prediction_id = 0; // not necessary 39 _queue [i]->_exception = 0; // not necessary 40 41 for (uint32_t j=0; j<_param->_nb_instruction; j++) 42 { 43 _queue [i]->_instruction [j] = 0; // not necessary 44 _queue [i]->_instruction_enable [j] = 0; // not necessary 45 } 46 } 47 } 48 else 49 { 50 // ========================================================== 51 // =====[ ADDRESS ]========================================== 52 // ========================================================== 53 if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) 54 { 55 log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : Transaction"); 56 log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); 57 log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS)); 58 59 // New slot in ifetch_queue is allocated 60 61 _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; 62 63 #ifdef STATISTICS 64 if (usage_is_set(_usage,USE_STATISTICS)) 65 (*_sum_transaction_address) ++; 66 #endif 67 68 for (uint32_t i=0; i<_param->_nb_instruction; i++) 69 { 70 Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); 71 #ifdef STATISTICS 72 if (usage_is_set(_usage,USE_STATISTICS)) 73 (*_sum_inst_enable) += enable; 74 #endif 75 _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; 76 } 77 78 _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); 79 _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; 80 _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); 81 _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; 82 83 reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; 84 } 85 86 // ========================================================== 87 // =====[ DECOD ]============================================ 88 // ========================================================== 89 bool have_instruction_decod = false; 90 bool have_instruction_enable = false; 91 for (uint32_t i=0; i<_param->_nb_instruction; i++) 92 { 93 if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) 94 { 95 log_printf(TRACE,Ifetch_queue,FUNCTION," * DECOD [%d] : Transaction",i); 96 97 have_instruction_decod = true; 98 _queue[reg_PTR_READ]->_instruction_enable [i] = false; 99 } 100 have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; 101 } 102 103 // Test if all is decoded 104 if (have_instruction_decod and not have_instruction_enable) 105 { 106 // all is decod 107 _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; 108 reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; 109 } 110 111 // ========================================================== 112 // =====[ ICACHE_RSP ]======================================= 113 // ========================================================== 114 if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) 115 { 116 log_printf(TRACE,Ifetch_queue,FUNCTION," * ICACHE_RSP : Transaction"); 117 118 Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; 119 120 for (uint32_t i=0; i<_param->_nb_instruction; i++) 121 _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); 122 123 switch (PORT_READ(in_ICACHE_RSP_ERROR)) 124 { 125 case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; 126 case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; 127 default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); 128 } 129 130 switch (_queue[ptr]->_state) 131 { 132 case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; 133 case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; 134 default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); 135 } 136 } 137 138 // ========================================================== 139 // =====[ EVENT_RESET ]====================================== 140 // ========================================================== 141 if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) 142 { 143 log_printf(TRACE,Ifetch_queue,FUNCTION," * EVENT_RESET : Transaction"); 144 145 // Scan all entry of queue and test the status 146 for (uint32_t i=0; i<_param->_size_queue; i++) 147 switch (_queue[i]->_state) 148 { 149 case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; 150 case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; 151 default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; 152 } 153 154 // all entry is empty (or wait respons to flush) 155 // reset ptr 156 // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 157 // 2) reg_PTR_READ = reg_PTR_WRITE 158 // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) 159 reg_PTR_READ = reg_PTR_WRITE; 160 } 161 162 #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) 163 log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); 164 log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); 165 log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); 166 for (uint32_t i=0; i<_param->_size_queue; i++) 167 { 168 log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", 169 i, 170 _queue [i]->_address, 171 _queue [i]->_address<<2, 172 _queue [i]->_inst_ifetch_ptr, 173 _queue [i]->_branch_state, 174 _queue [i]->_branch_update_prediction_id, 175 _queue [i]->_exception, 176 toString(_queue [i]->_state).c_str() 177 ); 178 179 for (uint32_t j=0; j<_param->_nb_instruction; j++) 180 log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); 181 } 182 #endif 183 184 #ifdef STATISTICS 185 if (usage_is_set(_usage,USE_STATISTICS)) 186 for (uint32_t i=0; i<_param->_size_queue; i++) 187 switch (_queue[i]->_state) 188 { 189 case IFETCH_QUEUE_STATE_EMPTY : break; 190 case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; 191 case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; 192 case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; 193 default : break; 194 } 195 #endif 196 } 27 (this->*function_transition) (); 197 28 198 29 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp
r135 r136 19 19 #undef FUNCTION 20 20 #define FUNCTION "Ifetch_queue::Parameters" 21 Parameters::Parameters (uint32_t size_queue , 22 uint32_t nb_instruction , 23 uint32_t size_branch_update_prediction, 24 uint32_t size_general_data , 25 bool is_toplevel) 21 Parameters::Parameters (uint32_t size_queue , 22 Tifetch_queue_scheme_t queue_scheme , 23 uint32_t nb_instruction , 24 uint32_t size_branch_update_prediction, 25 uint32_t size_general_data , 26 bool is_toplevel) 26 27 { 27 28 log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); … … 29 30 _nb_instruction_in_queue = size_queue ; 30 31 _size_queue = size_queue/nb_instruction ; 32 _queue_scheme = queue_scheme ; 31 33 _nb_instruction = nb_instruction ; 32 34 // _size_branch_update_prediction = size_branch_update_prediction; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp
r113 r136 29 29 test.error(_("Size of ifetch queue must be a multiple of nb_instruction.\n")); 30 30 31 switch (_queue_scheme) 32 { 33 case IFETCH_QUEUE_SCHEME_NO_ASSOC : 34 case IFETCH_QUEUE_SCHEME_FULL_ASSOC : 35 { 36 break; 37 } 38 default : 39 { 40 test.error(toString(_("Ifetch queue scheme '%s' is not supported. Please wait a next revision.\n"),toString(_queue_scheme).c_str())); 41 break; 42 } 43 } 44 31 45 if (_size_queue == 1) 32 46 test.warning(_("To best perfomance, size_queue must be > 1.\n")); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp
r88 r136 28 28 xml.balise_open("ifetch_queue"); 29 29 xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); 30 xml.singleton_begin("queue_scheme "); xml.attribut("value",toString(_queue_scheme )); xml.singleton_end(); 30 31 xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); 31 32 // xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h
r101 r136 98 98 public : SC_IN (Tcontrol_t ) ** in_DECOD_ACK ;//[nb_instruction] 99 99 public : SC_OUT(Tinstruction_t ) ** out_DECOD_INSTRUCTION ;//[nb_instruction] 100 //public : SC_OUT(Tcontext_t ) * out_DECOD_CONTEXT_ID ; 101 public : SC_OUT(Tgeneral_address_t ) * out_DECOD_ADDRESS ; 102 public : SC_OUT(Tinst_ifetch_ptr_t ) * out_DECOD_INST_IFETCH_PTR ; 103 public : SC_OUT(Tbranch_state_t ) * out_DECOD_BRANCH_STATE ; 104 public : SC_OUT(Tprediction_ptr_t ) * out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 105 public : SC_OUT(Texception_t ) * out_DECOD_EXCEPTION ; 100 //public : SC_OUT(Tcontext_t ) ** out_DECOD_CONTEXT_ID ; 101 public : SC_OUT(Tgeneral_address_t ) ** out_DECOD_ADDRESS ; 102 public : SC_OUT(Tbranch_state_t ) ** out_DECOD_BRANCH_STATE ; 103 public : SC_OUT(Tprediction_ptr_t ) ** out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 104 public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION ; 106 105 107 106 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h
r88 r136 27 27 //-----[ fields ]------------------------------------------------------------ 28 28 public : uint32_t _size_queue ; 29 public : ifetch_queue::Tifetch_queue_scheme_t 30 _queue_scheme ; 29 31 public : uint32_t _nb_instruction ; 30 32 //public : uint32_t _size_address ; … … 44 46 //-----[ methods ]----------------------------------------------------------- 45 47 public : Parameters (uint32_t size_queue , 48 ifetch_queue::Tifetch_queue_scheme_t 49 queue_scheme , 46 50 uint32_t nb_instruction , 47 51 uint32_t size_branch_update_prediction, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
r131 r136 116 116 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 117 117 { 118 ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."));119 120 //ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);121 ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address);122 ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);123 ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);124 ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);125 ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);126 127 ALLOC0_INTERFACE_END();128 }129 {130 118 ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); 131 119 132 120 ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); 133 121 ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); 122 134 123 ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); 124 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 125 ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 126 ALLOC1_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 127 ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 135 128 136 129 ALLOC1_INTERFACE_END(_param->_nb_instruction); … … 405 398 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" , 406 399 dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" ); 400 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_ADDRESS" , 401 dest,"out_DECOD_"+toString(i)+"_ADDRESS" ); 402 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_BRANCH_STATE" , 403 dest,"out_DECOD_"+toString(i)+"_BRANCH_STATE" ); 404 if (_param->_have_port_depth) 405 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID", 406 dest,"out_DECOD_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); 407 PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_EXCEPTION" , 408 dest,"out_DECOD_"+toString(i)+"_EXCEPTION" ); 407 409 } 408 409 PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );410 if (_param->_have_port_inst_ifetch_ptr)411 PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );412 PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );413 if (_param->_have_port_depth)414 PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");415 PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );416 410 } 417 411 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp
r128 r136 54 54 DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction,1); 55 55 56 // DELETE0_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_size_context_id);57 DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address);58 DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr);59 DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state);60 DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth);61 DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch);62 56 DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_instruction,1); 63 57 DELETE1_SIGNAL( in_DECOD_ACK ,_param->_nb_instruction,1); 64 58 DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_nb_instruction,_param->_size_instruction); 59 // DELETE1_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_instruction,_param->_size_context_id); 60 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_instruction,_param->_size_instruction_address); 61 DELETE1_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_nb_instruction,_param->_size_branch_state); 62 DELETE1_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_instruction,_param->_size_depth); 63 DELETE1_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_instruction,_param->_size_exception_ifetch); 65 64 66 65 DELETE0_SIGNAL( in_EVENT_VAL ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp
r88 r136 19 19 #define FUNCTION "Ifetch_unit::Parameters" 20 20 Parameters::Parameters (uint32_t size_queue , 21 ifetch_queue::Tifetch_queue_scheme_t 22 queue_scheme , 21 23 uint32_t nb_instruction , 22 24 uint32_t size_branch_update_prediction, … … 28 30 29 31 _size_queue = size_queue ; 32 _queue_scheme = queue_scheme ; 30 33 _nb_instruction = nb_instruction ; 31 34 // _size_branch_update_prediction = size_branch_update_prediction; … … 40 43 _param_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue:: Parameters 41 44 (size_queue , 45 queue_scheme , 42 46 nb_instruction , 43 47 size_branch_update_prediction, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters_print.cpp
r88 r136 27 27 // xml.balise_open("ifetch_unit"); 28 28 // xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); 29 // xml.singleton_begin("queue_scheme "); xml.attribut("value",toString(_queue_scheme )); xml.singleton_end(); 29 30 // xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); 30 31 // // xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters_msg_error.cpp
r81 r136 26 26 Parameters_test test ("Prediction_unit"); 27 27 28 for (uint32_t i=0; i<_nb_context; ++i) 29 if ((_nb_instruction[i] > 1) and (_ufpt_size_queue[i] < 2)) 30 test.error(toString(_("context \"%d\" : can fetch must than 1 instruction per cycle, size of Update Fetch Prediction Table must be less 1\n"),i)); 31 28 32 log_printf(FUNC,Prediction_unit,FUNCTION,"End"); 29 33 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h
r111 r136 41 41 // ifetch_unit 42 42 public : uint32_t * _size_ifetch_queue ;//[nb_context] 43 public : ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t 44 * _ifetch_queue_scheme ;//[nb_context] 43 45 public : uint32_t * _nb_inst_fetch ;//[nb_context] 44 46 public : bool ** _instruction_implemeted ;//[nb_context][nb_inst_fetch] … … 111 113 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), 112 114 // ifetch_unit 113 uint32_t * size_ifetch_queue , 114 uint32_t * nb_inst_fetch , 115 bool ** instruction_implemeted , 116 uint32_t * link_context_to_decod_unit , 115 uint32_t * size_ifetch_queue ,//[nb_context] 116 ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t 117 * ifetch_queue_scheme ,//[nb_context] 118 uint32_t * nb_inst_fetch ,//[nb_context] 119 bool ** instruction_implemeted ,//[nb_context] 120 uint32_t * link_context_to_decod_unit ,//[nb_context] 117 121 // decod_unit 118 122 uint32_t * size_decod_queue ,//[nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r123 r136 449 449 ////out_DECOD_CONTEXT_ID 450 450 451 COMPONENT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest, "in_IFETCH_"+toString(num_context)+"_ADDRESS" );452 if (_param->_have_port_inst_ifetch_ptr)453 COMPONENT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest, "in_IFETCH_"+toString(num_context)+"_INST_IFETCH_PTR" );454 COMPONENT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest, "in_IFETCH_"+toString(num_context)+"_BRANCH_STATE" );455 if (_param->_have_port_depth)456 COMPONENT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest, "in_IFETCH_"+toString(num_context)+"_BRANCH_UPDATE_PREDICTION_ID");457 COMPONENT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest, "in_IFETCH_"+toString(num_context)+"_EXCEPTION" );458 459 451 for (uint32_t j=0; j<_param->_nb_inst_fetch [i];++j) 460 452 { … … 471 463 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j)+ "_INSTRUCTION", 472 464 dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_INSTRUCTION"); 465 466 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j) +"_ADDRESS", 467 dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_ADDRESS"); 468 // if (_param->_have_port_inst_ifetch_ptr) 469 // COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j) +"_INST_IFETCH_PTR", 470 // dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_INST_IFETCH_PTR"); 471 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j) +"_BRANCH_STATE", 472 dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_BRANCH_STATE"); 473 if (_param->_have_port_depth) 474 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j) +"_BRANCH_UPDATE_PREDICTION_ID", 475 dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID"); 476 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j) +"_EXCEPTION", 477 dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_EXCEPTION"); 478 479 473 480 } 474 481 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
r128 r136 24 24 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), 25 25 // ifetch_unit 26 uint32_t * size_ifetch_queue , 27 uint32_t * nb_inst_fetch , 28 bool ** instruction_implemeted , 29 uint32_t * link_context_to_decod_unit , 26 uint32_t * size_ifetch_queue ,//[nb_context] 27 ifetch_unit::ifetch_queue::Tifetch_queue_scheme_t 28 * ifetch_queue_scheme ,//[nb_context] 29 uint32_t * nb_inst_fetch ,//[nb_context] 30 bool ** instruction_implemeted ,//[nb_context] 31 uint32_t * link_context_to_decod_unit ,//[nb_context] 30 32 // decod_unit 31 33 uint32_t * size_decod_queue ,//[nb_decod_unit] … … 74 76 _translate_num_context_to_num_thread = translate_num_context_to_num_thread ; 75 77 _size_ifetch_queue = size_ifetch_queue ; 78 _ifetch_queue_scheme = ifetch_queue_scheme ; 76 79 _nb_inst_fetch = nb_inst_fetch ; 77 80 _instruction_implemeted = instruction_implemeted ; … … 125 128 { 126 129 _param_ifetch_unit [i] = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters 127 (_size_ifetch_queue [i] , 128 _nb_inst_fetch [i] , 129 log2(_upt_size_queue[i]) , 130 (_size_ifetch_queue [i] , 131 _ifetch_queue_scheme[i] , 132 _nb_inst_fetch [i] , 133 log2(_upt_size_queue[i]) , 130 134 size_instruction_address ); 131 135 }
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