Changeset 145 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit
- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit
- Files:
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- 4 added
- 11 edited
- 2 moved
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SelfTest/configuration/config_mono_front_end.gen (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_mono_front_end.cfg)
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SelfTest/configuration/config_multi_front_end.gen (moved) (moved from trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/config_multi_front_end.cfg)
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include/Parameters.h (modified) (1 diff)
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include/Register_Address_Translation_unit.h (modified) (1 diff)
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src/Parameters.cpp (modified) (1 diff)
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src/Register_Address_Translation_unit.cpp (modified) (1 diff)
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src/Register_Address_Translation_unit_allocation.cpp (modified) (3 diffs)
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src/Register_Address_Translation_unit_deallocation.cpp (modified) (3 diffs)
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src/Register_Address_Translation_unit_function_depth_save_constant.cpp (modified) (1 diff)
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src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp (modified) (1 diff)
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src/Register_Address_Translation_unit_function_depth_save_transition.cpp (modified) (12 diffs)
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src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp (modified) (1 diff)
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src/Register_Address_Translation_unit_function_one_save_transition.cpp (modified) (10 diffs)
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src/old (added)
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src/old/Register_Address_Translation_unit_function_depth_save_constant.cpp (added)
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src/old/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp (added)
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src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp (added)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h
r139 r145 36 36 37 37 public : uint32_t _max_nb_context ; 38 public : uint32_t _max_nb_branch_speculated; 38 39 //public : uint32_t _size_front_end_id ; 39 40 //public : uint32_t _size_context_id ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
r139 r145 107 107 108 108 // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 109 public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] 110 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] 111 public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 112 public : SC_IN (Tevent_type_t ) *** in_RETIRE_EVENT_TYPE ;//[nb_front_end][nb_context] 113 public : SC_IN (Tdepth_t ) *** in_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context] 109 public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] 110 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] 111 public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 112 public : SC_IN (Tevent_type_t ) *** in_RETIRE_EVENT_TYPE ;//[nb_front_end][nb_context] 113 public : SC_IN (Tdepth_t ) *** in_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context] 114 115 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] 117 public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] 118 public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] 114 119 115 120 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 121 117 122 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 118 private : Tgeneral_address_t *** rat_gpr_not_speculative; //[nb_front_end][nb_context] [nb_general_register_logic]119 private : Tgeneral_address_t *** rat_gpr_speculative; //[nb_front_end][nb_context] [nb_general_register_logic]120 private : bool *** rat_gpr_speculative_valid; //[nb_front_end][nb_context] [nb_general_register_logic]121 private : Tgeneral_address_t **** rat_gpr_save; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]122 123 private : Tspecial_address_t *** rat_spr_not_speculative; //[nb_front_end][nb_context] [nb_special_register_logic]124 private : Tspecial_address_t *** rat_spr_speculative; //[nb_front_end][nb_context] [nb_special_register_logic]125 private : bool *** rat_spr_speculative_valid; //[nb_front_end][nb_context] [nb_special_register_logic]126 private : Tspecial_address_t **** rat_spr_save; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] 127 128 private : Tdepth_t ** rat_depth; //[nb_front_end][nb_context]123 // NO ONE DEPTH 124 private : Tgeneral_address_t *** RAT_GPR_NOT_SPECULATIVE; //[nb_front_end][nb_context] [nb_general_register_logic] X X X 125 private : Tgeneral_address_t **** RAT_GPR_SPECULATIVE; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic] X X 126 private : bool **** RAT_GPR_SPECULATIVE_VALID; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic] X X 127 128 private : Tspecial_address_t *** RAT_SPR_NOT_SPECULATIVE; //[nb_front_end][nb_context] [nb_special_register_logic] X X X 129 private : Tspecial_address_t **** RAT_SPR_SPECULATIVE; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] X X 130 private : bool **** RAT_SPR_SPECULATIVE_VALID; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] X X 131 132 private : bool *** reg_RAT_USE; //[nb_front_end][nb_context][nb_branch_speculated] X 133 private : bool ** reg_SAVE_RAT; //[nb_front_end][nb_context] X 129 134 130 135 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 136 private : Tcontrol_t * internal_RENAME_ACK; //[nb_inst_insert] 132 private : Tcontrol_t * internal_RENAME_SAVE; //[nb_inst_insert]133 137 private : Tcontrol_t * internal_INSERT_ACK; //[nb_inst_insert] 134 138 private : Tcontrol_t * internal_RETIRE_ACK; //[nb_inst_retire] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp
r144 r145 41 41 _nb_branch_speculated = nb_branch_speculated; 42 42 43 _max_nb_context = max<uint32_t>(_nb_context, _nb_front_end); 43 _max_nb_context = max<uint32_t>(_nb_context, _nb_front_end); 44 _max_nb_branch_speculated= max<uint32_t>(_nb_branch_speculated, _nb_front_end, _nb_context); 44 45 45 46 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
r139 r145 160 160 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 161 161 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 162 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 163 << (*(in_RETIRE_EVENT_STATE [i][j])); 162 { 163 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 164 << (*(in_RETIRE_EVENT_STATE [i][j])) 165 << (*(in_DEPTH_FULL [i][j])); 166 if (_param->_have_port_depth) 167 sensitive << (*(in_DEPTH_MIN [i][j])) 168 << (*(in_DEPTH_MAX [i][j])); 169 } 164 170 165 171 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
r139 r145 131 131 } 132 132 133 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 134 { 135 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 136 137 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 138 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 139 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 140 141 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 142 } 143 133 144 if (usage_is_set(_usage,USE_SYSTEMC)) 134 145 { 135 146 ALLOC1(internal_RENAME_ACK ,Tcontrol_t,_param->_nb_inst_insert); 136 ALLOC1(internal_RENAME_SAVE ,Tcontrol_t,_param->_nb_inst_insert);137 147 ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); 138 148 ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); 139 149 ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); 140 150 141 ALLOC3( rat_gpr_speculative,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);142 ALLOC3( rat_spr_speculative,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);151 ALLOC3(RAT_GPR_NOT_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 152 ALLOC3(RAT_SPR_NOT_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 143 153 144 154 switch(_param->_rat_scheme) … … 150 160 case RAT_ONE_SAVE : 151 161 { 152 ALLOC 3(rat_gpr_not_speculative ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);153 ALLOC 3(rat_gpr_speculative_valid,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);154 155 ALLOC 3(rat_spr_not_speculative ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);156 ALLOC 3(rat_spr_speculative_valid,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);162 ALLOC4(RAT_GPR_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 163 ALLOC4(RAT_SPR_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 164 165 ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 166 ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 157 167 158 168 break; … … 160 170 case RAT_DEPTH_SAVE : 161 171 { 162 ALLOC4(rat_gpr_save ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 163 ALLOC4(rat_spr_save ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 164 ALLOC2(rat_depth ,Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); 165 172 ALLOC4(RAT_GPR_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 173 ALLOC4(RAT_SPR_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 174 175 ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 176 ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 177 178 ALLOC3(reg_RAT_USE ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]); 179 ALLOC2(reg_SAVE_RAT ,bool ,_param->_nb_front_end,_param->_nb_context[it1]); 180 166 181 break; 167 182 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
r139 r145 76 76 DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ,_param->_rat_scheme == RAT_DEPTH_SAVE); 77 77 78 DELETE2_SIGNAL ( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 79 DELETE2_SIGNAL ( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 80 DELETE2_SIGNAL ( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 81 78 82 DELETE1(internal_RENAME_ACK ,_param->_nb_inst_insert); 79 DELETE1(internal_RENAME_SAVE ,_param->_nb_inst_insert);80 DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert);81 83 DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); 82 84 DELETE2(internal_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); 83 85 84 DELETE3( rat_gpr_speculative,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);85 DELETE3( rat_spr_speculative,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);86 86 DELETE3(RAT_GPR_NOT_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 87 DELETE3(RAT_SPR_NOT_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 88 87 89 switch(_param->_rat_scheme) 88 90 { … … 93 95 case RAT_ONE_SAVE : 94 96 { 95 DELETE 3(rat_gpr_not_speculative ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);96 DELETE 3(rat_gpr_speculative_valid ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);97 98 DELETE 3(rat_spr_not_speculative ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);99 DELETE 3(rat_spr_speculative_valid ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);97 DELETE4(RAT_GPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 98 DELETE4(RAT_SPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 99 100 DELETE4(RAT_GPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 101 DELETE4(RAT_SPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 100 102 101 103 break; … … 103 105 case RAT_DEPTH_SAVE : 104 106 { 105 DELETE4(rat_gpr_save ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 106 DELETE4(rat_spr_save ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 107 DELETE2(rat_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 107 DELETE4(RAT_GPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 108 DELETE4(RAT_SPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 109 110 DELETE4(RAT_GPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 111 DELETE4(RAT_SPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 112 113 DELETE3(reg_RAT_USE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]); 114 DELETE2(reg_SAVE_RAT ,_param->_nb_front_end,_param->_nb_context[it1]); 108 115 109 116 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp
r139 r145 30 30 { 31 31 internal_INSERT_ACK [i] = 1; 32 internal_RENAME_ACK [i] = 1; 32 33 33 34 PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]); 35 PORT_WRITE(out_RENAME_ACK[i],internal_RENAME_ACK [i]); 34 36 } 35 37 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
r139 r145 28 28 if (PORT_READ(in_NRESET) != 0) 29 29 { 30 bool have_branch_previous = false; 31 bool can_continue [_param->_nb_front_end][_param->_max_nb_context]; 30 bool rat_gpr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_general_register_logic]; 31 bool rat_spr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_special_register_logic]; 32 // bool reg_save_rat [_param->_nb_front_end][_param->_max_nb_context]; 32 33 33 34 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 34 35 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 35 can_continue [i][j] = true; 36 { 37 // reg_save_rat [i][j] = reg_SAVE_RAT [i][j]; 38 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 39 { 40 for (uint32_t l=0; l<_param->_nb_general_register_logic; ++l) 41 rat_gpr_speculative_valid [i][j][k][l] = RAT_GPR_SPECULATIVE_VALID [i][j][k][l]; 42 for (uint32_t l=0; l<_param->_nb_special_register_logic; ++l) 43 rat_spr_speculative_valid [i][j][k][l] = RAT_SPR_SPECULATIVE_VALID [i][j][k][l]; 44 } 45 } 36 46 37 47 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 38 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access39 {40 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i);41 42 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;43 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID[i]):0;44 // bool have_event = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack45 // (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));46 47 bool have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);48 { 49 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access 50 { 51 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i); 52 53 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 54 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 55 56 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 57 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 48 58 49 // one branch per cycle 50 can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous); 59 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 60 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 61 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 51 62 52 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 53 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 54 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_event : %d",have_event); 55 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_branch_previous : %d",have_branch_previous); 56 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_branch_current : %d",have_branch_current ); 57 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * can_continue : %d",can_continue[front_end_id][context_id]); 58 59 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 60 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 61 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 62 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 63 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 64 65 Tgeneral_address_t num_reg_ra_phy = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]; 66 Tgeneral_address_t num_reg_rb_phy = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]; 67 Tspecial_address_t num_reg_rc_phy = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]; 68 Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]; 69 Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log]; 70 71 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); 72 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); 73 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); 74 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); 75 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); 76 77 internal_RENAME_ACK [i] = can_continue[front_end_id][context_id]; 78 PORT_WRITE(out_RENAME_ACK [i],internal_RENAME_ACK [i]); 79 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); 80 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); 81 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); 82 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); 83 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); 63 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 64 // Tcontrol_t save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); 65 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth/min/max/full : %d - [%d:%d] - %d",depth,depth_min,depth_max,depth_full); 66 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); 67 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",reg_save_rat [front_end_id][context_id]); 68 69 // if (reg_save_rat [front_end_id][context_id]) 70 // { 71 // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) 72 // rat_gpr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; 73 // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) 74 // rat_spr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; 75 // } 76 77 // reg_save_rat[front_end_id][context_id] = save_rat; 78 79 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 80 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 81 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 82 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 83 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 84 85 Tgeneral_address_t num_reg_ra_phy ; 86 Tgeneral_address_t num_reg_rb_phy ; 87 Tspecial_address_t num_reg_rc_phy ; 88 Tgeneral_address_t num_reg_rd_phy_old; 89 Tspecial_address_t num_reg_re_phy_old; 90 91 bool find_ra = false; 92 bool find_rb = false; 93 bool find_rc = false; 94 bool find_rd = false; 95 bool find_re = false; 96 97 for (uint32_t num_branch=0; num_branch<_param->_nb_branch_speculated[front_end_id][context_id]; ++num_branch) 98 { 99 uint32_t index = (depth-num_branch)%_param->_nb_branch_speculated[front_end_id][context_id]; 84 100 85 internal_RENAME_SAVE [i] = have_branch_current; 101 if (not find_ra and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_ra_log]) 102 { 103 find_ra = true; 104 num_reg_ra_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_ra_log]; 105 } 106 107 if (not find_rb and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rb_log]) 108 { 109 find_rb = true; 110 num_reg_rb_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rb_log]; 111 } 112 113 if (not find_rc and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_rc_log]) 114 { 115 find_rc = true; 116 num_reg_rc_phy = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rc_log]; 117 } 118 119 if (not find_rd and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rd_log]) 120 { 121 find_rd = true; 122 num_reg_rd_phy_old = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rd_log]; 123 } 124 125 if (not find_re and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_re_log]) 126 { 127 find_re = true; 128 num_reg_re_phy_old = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_re_log]; 129 } 86 130 87 // save info to the next instruction 88 have_branch_previous |= have_branch_current; 89 } 131 // if index == depth_min, stop because depth_min is the not speculative. 132 // if (index == depth_min) 133 // break; 134 } 135 136 if (not find_ra) 137 num_reg_ra_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log]; 138 if (not find_rb) 139 num_reg_rb_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log]; 140 if (not find_rc) 141 num_reg_rc_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log]; 142 if (not find_rd) 143 num_reg_rd_phy_old = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log]; 144 if (not find_re) 145 num_reg_re_phy_old = RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log]; 146 147 // if rat_SPECULATIVE is valid, 148 // then read rat_SPECULATIVE have the most valid alias register 149 // else, they have an previous event, the rat_NOT_SPECULATIVE have the valid register 150 151 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); 152 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); 153 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); 154 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); 155 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); 156 157 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); 158 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); 159 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); 160 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); 161 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); 162 } 163 } 90 164 } 91 165 92 166 log_end(Register_Address_Translation_unit,FUNCTION); 93 167 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
r144 r145 34 34 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 35 35 { 36 rat_depth [i][j] = 0; 37 rat_gpr_speculative [i][j][0] = 0; 36 RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; 37 RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; 38 RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary 38 39 39 40 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 40 rat_gpr_speculative [i][j][k] = gpr++; 41 { 42 RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; 43 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 44 { 45 RAT_GPR_SPECULATIVE_VALID [i][j][l][k] = false; 46 RAT_GPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 47 } 48 } 41 49 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 42 rat_spr_speculative [i][j][k] = spr++; // not necessary 50 { 51 RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; 52 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 53 { 54 RAT_SPR_SPECULATIVE_VALID [i][j][l][k] = false; 55 RAT_SPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 56 } 57 } 58 59 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 60 reg_RAT_USE [i][j][k] = false; 61 reg_SAVE_RAT [i][j] = false; 43 62 } 44 63 } … … 46 65 { 47 66 // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) 67 bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated]; 68 for (uint32_t i=0; i<_param->_nb_front_end; i++) 69 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 70 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 71 free_rat [i][j][k] = false; 48 72 49 73 // ===================================================== … … 55 79 { 56 80 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j); 81 82 // Test if event have just occure 83 // * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value) 57 84 58 // Test if event have just occure59 85 if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) 60 { 61 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 86 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 87 { 88 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 62 89 { 63 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 64 case EVENT_TYPE_LOAD_MISS_SPECULATION : 65 { 66 // Miss speculation (branch or load) 67 // Restore contexte and update depth 68 69 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * MISS_SPECULATION : Restore RAT"); 70 71 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0; 72 73 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 74 75 // restore GPR 76 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 77 rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr]; 78 79 // restore SPR 80 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 81 rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr]; 82 83 // update rat_depth 84 rat_depth[i][j] = depth; 85 86 break; 87 } 88 // case EVENT_TYPE_EXCEPTION : 89 // case EVENT_TYPE_SPR_ACCESS : 90 // case EVENT_TYPE_MSYNC : 91 // case EVENT_TYPE_PSYNC : 92 // case EVENT_TYPE_CSYNC : 93 default : 94 { 95 // nothing 96 break; 97 } 90 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * BRANCH_MISS_SPECULATION - Reset Update Table"); 91 92 reg_SAVE_RAT [i][j] = true; 93 94 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0; 95 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 96 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 97 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 98 99 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 100 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 101 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 102 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 103 104 Tdepth_t it = depth_min; 105 106 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 107 { 108 it = (it-1)%_param->_nb_branch_speculated[i][j]; 109 110 if (it == depth) 111 break; 112 113 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",it); 114 115 free_rat[i][j][it] = true; 116 } 117 118 break; 98 119 } 99 100 } 120 case EVENT_TYPE_EXCEPTION : 121 { 122 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * EXCEPTION - Reset Update Table"); 123 124 reg_SAVE_RAT [i][j] = true; 125 126 // Reset validity table 127 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 128 free_rat [i][j][k] = true; 129 130 break; 131 } 132 default : 133 { 134 break; 135 } 136 } 101 137 } 102 138 … … 114 150 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 115 151 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 116 Tcontrol_t save = internal_RENAME_SAVE [i]; 152 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 153 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 154 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 155 Tcontrol_t save_rat = reg_SAVE_RAT[front_end_id][context_id]; 156 // TODO SAVE_RAT 117 157 118 158 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); 119 159 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); 120 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save : %d",save); 121 122 // Test if write and modifie RAT (RD and RE) 123 124 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 125 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 126 160 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 161 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",save_rat); 162 163 if (save_rat) 164 { 165 // #ifdef DEBUG_TEST 166 // if (reg_RAT_USE[front_end_id][context_id][depth]) 167 // throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth)); 168 // #endif 169 reg_RAT_USE[front_end_id][context_id][depth] = true; 170 171 // new branch, new RAT 172 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) 173 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 174 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) 175 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 176 } 177 178 save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); 179 reg_SAVE_RAT[front_end_id][context_id] = save_rat; 180 181 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); 182 183 // Test if write and modifie RAT 127 184 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); 128 185 if (write_rd == 1) … … 134 191 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); 135 192 136 rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; 193 RAT_GPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy; 194 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true; 137 195 } 138 196 … … 146 204 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); 147 205 148 rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; 149 } 150 151 if (save) 152 { 153 // Need save RAT 154 155 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 156 157 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth old - new : %d",depth); 158 159 // #ifdef DEBUG_TEST 160 // if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id])) 161 // throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth)); 162 // #endif 163 164 // save GPR 165 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 166 rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr]; 167 168 // save SPR 169 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 170 rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr]; 171 172 // update rat_depth with new depth 173 rat_depth[front_end_id][context_id] = depth; 206 RAT_SPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy; 207 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true; 174 208 } 175 209 } … … 179 213 // ===================================================== 180 214 // Second : interface retire 181 // (because if an event on the same thread : the instruction is already renamed) 182 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 183 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 184 { 215 // if event AND event is exception, restore rat_NOT_SPECULATIVE 216 217 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 218 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 219 { 185 220 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); 186 221 187 // if no event : no effect, because the RAT content the most recently register188 // but if they have a event (exception or miss speculation), the rat must restore the oldest value189 // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register190 // the retire interface became of the Re Order Buffer, also is in program sequence !191 192 #ifdef DEBUG193 222 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; 194 223 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; 195 #endif196 224 Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); 197 225 Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); … … 206 234 if (write_rd == 1) 207 235 { 208 #ifdef DEBUG209 236 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); 210 #endif211 237 212 238 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); … … 214 240 if (not restore) 215 241 { 216 #ifdef DEBUG217 242 Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 218 #endif 243 219 244 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); 220 245 221 // rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;246 RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; 222 247 } 223 248 } … … 226 251 if (write_re == 1) 227 252 { 228 #ifdef DEBUG229 253 Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); 254 255 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 256 257 if (not restore) 258 { 259 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 260 261 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 262 263 RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 264 } 265 } 266 } 267 268 // ===================================================== 269 // ====[ DEPTH ]======================================== 270 // ===================================================== 271 #if 1 272 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 273 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 274 { 275 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * DEPTH[%d][%d]",i,j); 276 277 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 278 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 279 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 280 281 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 282 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 283 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 284 285 if (not depth_full) 286 { 287 Tdepth_t depth = depth_max; 288 289 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 290 { 291 if (depth == depth_min) 292 break; 293 294 if (reg_RAT_USE[i][j][depth]) 295 { 296 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",depth); 297 298 free_rat [i][j][depth] = true; 299 // reg_RAT_USE[i][j][depth] = false; 300 301 // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 302 // RAT_GPR_SPECULATIVE_VALID [i][j][depth][l] = false; 303 // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 304 // RAT_SPR_SPECULATIVE_VALID [i][j][depth][l] = false; 305 } 306 307 depth = (depth+1)%_param->_nb_branch_speculated[i][j]; 308 } 309 } 310 } 230 311 #endif 231 232 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 233 234 if (not restore) 235 { 236 #ifdef DEBUG 237 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 238 #endif 239 240 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 241 242 // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 243 } 244 } 245 246 } 312 // ===================================================== 313 // ====[ FREE RAT ]===================================== 314 // ===================================================== 315 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 316 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 317 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 318 if (free_rat[i][j][k]) 319 { 320 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Free RAT : [%d][%d][%d]",i,j,k); 321 322 reg_RAT_USE[i][j][k] = false; 323 324 for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 325 RAT_GPR_SPECULATIVE_VALID [i][j][k][l] = false; 326 for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 327 RAT_SPR_SPECULATIVE_VALID [i][j][k][l] = false; 328 } 329 247 330 } 248 331 … … 255 338 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 256 339 { 257 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);258 259 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)340 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]); 341 342 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 260 343 { 261 344 std::string str = ""; 262 345 for (uint32_t x=0; x<limit; x++) 263 346 { 264 uint32_t index = k+x;347 uint32_t index = l+x; 265 348 if (index >= _param->_nb_general_register_logic) 266 349 break; 267 350 else 268 str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative[i][j][index]);351 str+=toString("GPR[%.4d] - %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]); 269 352 } 270 353 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 271 354 } 272 355 273 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 274 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) 275 { 276 std::string str = ""; 277 for (uint32_t x=0; x<limit; x++) 278 { 279 uint32_t index = k+x; 280 if (index >= _param->_nb_general_register_logic) 281 break; 282 else 283 str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]); 284 } 285 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 286 } 287 288 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 356 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 357 { 358 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 359 360 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 361 { 362 std::string str = ""; 363 for (uint32_t x=0; x<limit; x++) 364 { 365 uint32_t index = l+x; 366 if (index >= _param->_nb_general_register_logic) 367 break; 368 else 369 str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]); 370 } 371 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 372 } 373 } 374 375 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 289 376 { 290 377 std::string str = ""; … … 292 379 for (uint32_t x=0; x<limit; x++) 293 380 { 294 uint32_t index = k+x;381 uint32_t index = l+x; 295 382 if (index >= _param->_nb_special_register_logic) 296 383 break; 297 384 else 298 str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative[i][j][index]);385 str+=toString("SPR[%.4d] - %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]); 299 386 } 300 387 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 301 388 } 302 389 303 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 304 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 305 { 306 std::string str = ""; 307 for (uint32_t x=0; x<limit; x++) 308 { 309 uint32_t index = k+x; 310 if (index >= _param->_nb_special_register_logic) 311 break; 312 else 313 str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]); 314 } 315 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 316 } 317 390 391 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 392 { 393 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 394 395 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 396 { 397 std::string str = ""; 398 399 for (uint32_t x=0; x<limit; x++) 400 { 401 uint32_t index = l+x; 402 if (index >= _param->_nb_special_register_logic) 403 break; 404 else 405 str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]); 406 } 407 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 408 } 409 } 318 410 } 319 411 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp
r139 r145 52 52 // else, they have an previous event, the rat_not_speculative have the valid register 53 53 54 Tgeneral_address_t num_reg_ra_phy = ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_ra_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_ra_log];55 Tgeneral_address_t num_reg_rb_phy = ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rb_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rb_log];56 Tspecial_address_t num_reg_rc_phy = ( rat_spr_speculative_valid[front_end_id][context_id][num_reg_rc_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_rc_log];57 Tgeneral_address_t num_reg_rd_phy_old= ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rd_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log];58 Tspecial_address_t num_reg_re_phy_old= ( rat_spr_speculative_valid[front_end_id][context_id][num_reg_re_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_re_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log];54 Tgeneral_address_t num_reg_ra_phy = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_ra_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_ra_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log]; 55 Tgeneral_address_t num_reg_rb_phy = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rb_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rb_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log]; 56 Tspecial_address_t num_reg_rc_phy = (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rc_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rc_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log]; 57 Tgeneral_address_t num_reg_rd_phy_old= (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rd_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rd_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log]; 58 Tspecial_address_t num_reg_re_phy_old= (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_re_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_re_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log]; 59 59 60 60 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp
r139 r145 34 34 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 35 35 { 36 rat_gpr_not_speculative [i][j][0]= 0;37 rat_gpr_speculative_valid [i][j][0] = false;38 rat_gpr_speculative [i][j][0] = 0 ; // not necessary36 RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; 37 RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; 38 RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary 39 39 40 40 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 41 41 { 42 rat_gpr_not_speculative [i][j][k]= gpr++;43 rat_gpr_speculative_valid [i][j][k] = false;44 rat_gpr_speculative [i][j][k] = 0 ; // not necessary42 RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; 43 RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; 44 RAT_GPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary 45 45 } 46 46 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 47 47 { 48 rat_spr_not_speculative [i][j][k]= spr++;49 rat_spr_speculative_valid [i][j][k] = false;50 rat_spr_speculative [i][j][k] = 0 ; // not necessary48 RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; 49 RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; 50 RAT_SPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary 51 51 } 52 52 } … … 69 69 // Reset validity table 70 70 for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) 71 rat_gpr_speculative_valid [i][j][k] = false;71 RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; 72 72 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 73 rat_spr_speculative_valid [i][j][k] = false;73 RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; 74 74 } 75 75 … … 103 103 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); 104 104 105 rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;106 rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;105 RAT_GPR_SPECULATIVE [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy; 106 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true; 107 107 } 108 108 … … 116 116 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); 117 117 118 rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;119 rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;118 RAT_SPR_SPECULATIVE [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy; 119 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true; 120 120 } 121 121 } … … 160 160 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); 161 161 162 rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;162 RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; 163 163 } 164 164 } … … 177 177 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 178 178 179 rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;179 RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 180 180 } 181 181 } … … 203 203 break; 204 204 else 205 str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index, rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative[i][j][index]);205 str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]); 206 206 } 207 207 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); … … 218 218 break; 219 219 else 220 str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index, rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative[i][j][index]);220 str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]); 221 221 } 222 222 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); … … 235 235 for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) 236 236 { 237 if ( rat_gpr_speculative_valid [i][j][x] and238 rat_gpr_speculative_valid [i][j][y] and239 ( rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))240 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));241 if ( rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])242 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));237 if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and 238 RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and 239 (RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y])) 240 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x])); 241 if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y]) 242 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x])); 243 243 244 244 } … … 246 246 for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) 247 247 { 248 if( rat_spr_speculative_valid [i][j][x] and249 rat_spr_speculative_valid [i][j][y] and250 ( rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))251 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));252 if ( rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])253 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));248 if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and 249 RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and 250 (RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y])) 251 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x])); 252 if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y]) 253 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x])); 254 254 255 255 }
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