Ignore:
Timestamp:
Jul 5, 2007, 5:50:19 PM (17 years ago)
Author:
rosiere
Message:

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table
Files:
2 deleted
12 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/configuration.cfg

    r2 r42  
    11Pattern_History_Table
    2 2       8       *2      # size_counter         
    3 2       64      *4      # nb_counter       
    4 1       2       +1      # nb_prediction     
    5 1       2       +1      # nb_branch_complete
     28       8       *2      # size_counter         
     364      64      *4      # nb_counter       
     42       2       +1      # nb_prediction     
     52       2       +1      # nb_branch_complete

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/mkf.info

    r15 r42  
     1
     2# Pattern_History_Table_0
     3target_dep      all     Pattern_History_Table_0.ngc
     4target_dep      Pattern_History_Table_0.ngc     Pattern_History_Table_0.prj
     5target_dep      Pattern_History_Table_0.prj     Pattern_History_Table_0_Counter_Pack.vhdl Pattern_History_Table_0_Counter.vhdl Pattern_History_Table_0_Pack.vhdl Pattern_History_Table_0_RegisterFile_Pack.vhdl Pattern_History_Table_0_RegisterFile.vhdl Pattern_History_Table_0.vhdl
     6

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/src/test.cpp

    r15 r42  
    77 */
    88
    9 #define NB_ITERATION 1024
     9#define NB_ITERATION 512
    1010
    1111#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/SelfTest/include/test.h"
    … …  
    9393
    9494  sc_start(0);
    95   _Pattern_History_Table->vhdl_testbench_label("Initialisation");
    9695  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
    9796 
    … …  
    127126  sc_start(0);
    128127
    129   _Pattern_History_Table->vhdl_testbench_label("Loop of Test");
    130128  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl;
    131129
    132130  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
    133131    {
    134       _Pattern_History_Table->vhdl_testbench_label("Iteration "+toString(iteration));
    135132      num_port_branch_complete = rand() % param._nb_branch_complete;
    136133      num_port_predict         = rand() % param._nb_prediction     ;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h

    r15 r42  
    2929#include "Behavioural/include/Vhdl.h"
    3030#endif
    31 #ifdef VHDL_TESTBENCH
    32 #include "Behavioural/include/Vhdl_Testbench.h"
    33 #endif
     31#include "Behavioural/include/Component.h"
    3432
    3533using namespace std;
    … …  
    6260#endif
    6361
    64 #ifdef VHDL_TESTBENCH
    65   private   : Vhdl_Testbench                 * _vhdl_testbench;
    66 #endif
     62  public    : Component                      * _component;
     63  private   : Interfaces                     * _interfaces;
    6764
    6865#ifdef SYSTEMC
    … …  
    125122  public  : string   statistics                (uint32_t depth);
    126123#endif
    127                                                
    128124#if VHDL                                       
    129125  public  : void     vhdl                      (void);
    130   private : void     vhdl_port                 (Vhdl & vhdl);
    131   private : void     vhdl_declaration          (Vhdl & vhdl);
    132   private : void     vhdl_body                 (Vhdl & vhdl);
     126  private : void     vhdl_declaration          (Vhdl * & vhdl);
     127  private : void     vhdl_body                 (Vhdl * & vhdl);
    133128#endif                                         
    134                                                
    135129#ifdef VHDL_TESTBENCH                         
    136   private : void     vhdl_testbench_port       (void);
    137130  private : void     vhdl_testbench_transition (void);
    138131#endif
    139   public  : void     vhdl_testbench_label      (string label);
    140132  };
    141133

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table.cpp

    r15 r42  
    3333  {
    3434    log_printf(FUNC,Pattern_History_Table,"Pattern_History_Table","Begin");
    35    
     35   
     36#ifdef SYSTEMC
     37    allocation ();
     38#endif
     39 
    3640#ifdef STATISTICS
    3741    // Allocation of statistics
    … …  
    3943                            param_statistics          ,
    4044                            param);
    41 #endif
    42 
    43 #ifdef VHDL_TESTBENCH
    44     // Creation of a testbench
    45     //  -> port
    46     //  -> clock's signals
    47     _vhdl_testbench = new Vhdl_Testbench (_name);
    48     vhdl_testbench_port           ();
    49     _vhdl_testbench->set_clock    ("in_CLOCK",true);
    5045#endif
    5146
    … …  
    5651
    5752#ifdef SYSTEMC
    58     allocation ();
    59 
    6053//     // Constant
    6154//     for (uint32_t i=0; i<_param._nb_prediction     ; i++)
    … …  
    8275    log_printf(FUNC,Pattern_History_Table,"~Pattern_History_Table","Begin");
    8376
    84 #ifdef VHDL_TESTBENCH
    85     // generate the test bench
    86     _vhdl_testbench->generate_file();
    87     delete _vhdl_testbench;
    88 #endif
    89 
    9077#ifdef STATISTICS
    9178    _stat->generate_file(statistics(0));

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_allocation.cpp

    r15 r42  
    2020  void Pattern_History_Table::allocation (void)
    2121  {
    22     string rename;
    23 
    2422    log_printf(FUNC,Pattern_History_Table,"allocation","Begin");
    2523
    26     in_CLOCK  = new SC_CLOCK           ("in_CLOCK");
    27     in_NRESET = new SC_IN (Tcontrol_t) ("in_NRESET");
    28 
     24    _component   = new Component ();
     25
     26    Entity * entity = _component->set_entity (_name                 
     27                                             ,"Pattern_History_Table"
     28#ifdef POSITION
     29                                             ,MIXTE               
     30#endif
     31                                              );
     32   
     33    _interfaces = entity->set_interfaces();
     34
     35    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     36    {
     37      Interface * interface = _interfaces->set_interface(""
     38#ifdef POSITION
     39                                                         , IN 
     40                                                         , SOUTH
     41                                                         , "Generalist interface"
     42#endif
     43                                                         );
     44     
     45      in_CLOCK              = interface->set_signal_clk              ("clock" ,1);
     46      in_NRESET             = interface->set_signal_in  <Tcontrol_t> ("nreset",1,RESET_VHDL_YES);
     47    }
     48
     49    // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    2950     in_PREDICT_VAL     = new SC_IN (Tcontrol_t) * [_param._nb_prediction];
    3051    out_PREDICT_ACK     = new SC_OUT(Tcontrol_t) * [_param._nb_prediction];
    … …  
    3455    for (uint32_t i=0; i<_param._nb_prediction; i++)
    3556      {
    36         rename = "in_PREDICT_VAL["     +toString(i)+"]";
    37          in_PREDICT_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
    38 
    39         rename = "out_PREDICT_ACK["    +toString(i)+"]";
    40         out_PREDICT_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
    41 
    42         rename = "in_PREDICT_ADDRESS["+toString(i)+"]";
    43          in_PREDICT_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
    44 
    45         rename = "out_PREDICT_HISTORY["+toString(i)+"]";
    46         out_PREDICT_HISTORY [i] = new SC_OUT(Thistory_t) (rename.c_str());
    47       }
     57        Interface_fifo * interface = _interfaces->set_interface("predict_"+toString(i)
     58#ifdef POSITION
     59                                                                , IN 
     60                                                                , WEST
     61                                                                , "Interface Predict"
     62#endif
     63                                                                );
     64
     65         in_PREDICT_VAL     [i] = interface->set_signal_valack_in        ("val"    , VAL);
     66        out_PREDICT_ACK     [i] = interface->set_signal_valack_out       ("ack"    , ACK);
     67         in_PREDICT_ADDRESS [i] = interface->set_signal_in  <Taddress_t> ("address", static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
     68        out_PREDICT_HISTORY [i] = interface->set_signal_out <Thistory_t> ("history", _param._size_counter);
     69      }
     70   
     71    // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    4872
    4973        in_BRANCH_COMPLETE_VAL       = new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
    … …  
    5276        in_BRANCH_COMPLETE_HISTORY   = new SC_IN     (Thistory_t) * [_param._nb_branch_complete];
    5377        in_BRANCH_COMPLETE_DIRECTION = new SC_IN     (Tcontrol_t) * [_param._nb_branch_complete];
    54     signal_BRANCH_COMPLETE_HISTORY   = new SC_SIGNAL (Thistory_t) * [_param._nb_branch_complete];
    5578
    5679    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    5780      {
    58          rename = "in_BRANCH_COMPLETE_VAL["    +toString(i)+"]";
    59           in_BRANCH_COMPLETE_VAL     [i] = new SC_IN (Tcontrol_t) (rename.c_str());
    60 
    61          rename = "out_BRANCH_COMPLETE_ACK["   +toString(i)+"]";
    62          out_BRANCH_COMPLETE_ACK     [i] = new SC_OUT(Tcontrol_t) (rename.c_str());
    63 
    64          rename = "in_BRANCH_COMPLETE_ADDRESS["+toString(i)+"]";
    65           in_BRANCH_COMPLETE_ADDRESS [i] = new SC_IN (Taddress_t) (rename.c_str());
    66 
    67          rename = "in_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
    68           in_BRANCH_COMPLETE_HISTORY [i] = new SC_IN (Thistory_t) (rename.c_str());
    69 
    70          rename = "in_BRANCH_COMPLETE_DIRECTION["    +toString(i)+"]";
    71           in_BRANCH_COMPLETE_DIRECTION [i] = new SC_IN (Tcontrol_t) (rename.c_str());
    72 
    73          rename = "signal_BRANCH_COMPLETE_HISTORY["+toString(i)+"]";
    74          signal_BRANCH_COMPLETE_HISTORY [i] = new SC_SIGNAL (Thistory_t) (rename.c_str());
    75 
    76       }
    77    
     81        Interface_fifo * interface = _interfaces->set_interface("branch_complete_"+toString(i)
     82#ifdef POSITION
     83                                                                , IN 
     84                                                                , EAST
     85                                                                , "Interface branch complete"
     86#endif
     87                                                                );
     88
     89         in_BRANCH_COMPLETE_VAL        [i] = interface->set_signal_valack_in        ("val"      , VAL);
     90        out_BRANCH_COMPLETE_ACK        [i] = interface->set_signal_valack_out       ("ack"      , ACK);
     91         in_BRANCH_COMPLETE_ADDRESS    [i] = interface->set_signal_in  <Taddress_t> ("address"  , static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
     92         in_BRANCH_COMPLETE_HISTORY    [i] = interface->set_signal_in  <Thistory_t> ("history"  , _param._size_counter);
     93         in_BRANCH_COMPLETE_DIRECTION  [i] = interface->set_signal_in  <Tcontrol_t> ("direction", 1);
     94      }
     95
    7896    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    7997    string name_component;
     98
    8099    // =====[ component_Counter ]=========================================   
    81100   
    82101    name_component = _name+"_Counter";
    83102
    84     component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str(),
     103    component_Counter = new morpheo::behavioural::generic::counter::Counter (name_component.c_str()
    85104#ifdef STATISTICS
    86                                                                              _param_statistics             ,
    87 #endif
    88                                                                              *(_param._param_counter)      );
    89    
    90    
    91     // Instantiation
     105                                                                             ,_param_statistics
     106#endif
     107                                                                             ,*(_param._param_counter));
     108
     109    _component->set_component (component_Counter->_component
     110#ifdef POSITION
     111                               , 25
     112                               , 25
     113                               , 10
     114                               , 10
     115#endif
     116                               );
     117
     118     // =====[ component_RegisterFile ]====================================   
     119   
     120    name_component = _name+"_RegisterFile";
     121   
     122    component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic(name_component.c_str(),
     123#ifdef STATISTICS
     124                                                                                                                               _param_statistics            ,
     125#endif
     126                                                                                                                               *(_param._param_registerfile));
     127
     128    _component->set_component (component_RegisterFile->_component
     129#ifdef POSITION
     130                               , 75
     131                               , 75
     132                               , 10
     133                               , 10
     134#endif
     135                               );
     136     
     137    // ~~~~~[ Component - Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
     138
     139    // =====[ component_RegisterFile - Instanciation ]====================   
     140
     141#ifdef POSITION
     142    _component->interface_map (_name+"_RegisterFile","",
     143                               _name                ,"");
     144#endif
     145
     146    _component->port_map(_name+"_RegisterFile", "in_CLOCK" , _name,"in_CLOCK" );
     147    _component->port_map(_name+"_RegisterFile", "in_NRESET", _name,"in_NRESET");
     148   
     149    for (uint32_t i=0; i<_param._nb_prediction; i++)
     150      {
     151#ifdef POSITION
     152        _component->interface_map (_name+"_RegisterFile","read_"   +toString(i),
     153                                   _name                ,"predict_"+toString(i));
     154#endif
     155
     156        _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_VAL"    , _name, "in_PREDICT_"+toString(i)+"_VAL"    );
     157        _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_ACK"    , _name,"out_PREDICT_"+toString(i)+"_ACK"    );
     158        _component->port_map(_name+"_RegisterFile", "in_READ_"+toString(i)+"_ADDRESS", _name, "in_PREDICT_"+toString(i)+"_ADDRESS");
     159        _component->port_map(_name+"_RegisterFile","out_READ_"+toString(i)+"_DATA"   , _name,"out_PREDICT_"+toString(i)+"_HISTORY");
     160      }
     161   
     162    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
     163      {
     164#ifdef POSITION
     165        _component->interface_map (_name+"_RegisterFile","write_"  +toString(i),
     166                                   _name+"_Counter"     ,"counter_"+toString(i));
     167#endif
     168
     169        _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_VAL"    , _name           , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL"    );
     170        _component->port_map(_name+"_RegisterFile","out_WRITE_"+toString(i)+"_ACK"    , _name           ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK"    );
     171        _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_ADDRESS", _name           , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS");
     172        _component->port_map(_name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA"   , _name+"_Counter","out_COUNTER_"        +toString(i)+"_DATA");
     173      }
     174
     175    // =====[ component_Counter - Instanciation ]=========================   
     176
    92177#if (defined(STATISTICS) || defined (VHDL_TESTBENCH))
    93     (*(component_Counter->in_CLOCK))        (*(in_CLOCK));
     178
     179#ifdef POSITION
     180    _component->interface_map (_name+"_Counter","",
     181                               _name           ,"");
     182#endif
     183
     184    _component->port_map(_name+"_Counter", "in_CLOCK" , _name,"in_CLOCK" );
     185    _component->port_map(_name+"_Counter", "in_NRESET", _name,"in_NRESET");
     186
    94187#endif
    95188
    96189    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    97190      {
    98         (*(component_Counter-> in_COUNTER_DATA       [i]))    (*(    in_BRANCH_COMPLETE_HISTORY   [i]));
    99         (*(component_Counter-> in_COUNTER_ADDSUB     [i]))    (*(    in_BRANCH_COMPLETE_DIRECTION [i]));
    100         (*(component_Counter->out_COUNTER_DATA       [i]))    (*(signal_BRANCH_COMPLETE_HISTORY   [i]));
    101       }
    102    
    103      // =====[ component_RegisterFile ]====================================   
    104    
    105     name_component = _name+"_RegisterFile";
    106    
    107     component_RegisterFile = new morpheo::behavioural::generic::registerfile::registerfile_monolithic::RegisterFile_Monolithic (name_component.c_str(),
    108 #ifdef STATISTICS
    109                                                                                                                                 _param_statistics            ,
    110 #endif
    111                                                                                                                                 *(_param._param_registerfile));
    112    
    113     // Instantiation
    114     (*(component_RegisterFile->in_CLOCK))        (*(in_CLOCK));
    115     (*(component_RegisterFile->in_NRESET))       (*(in_NRESET));
    116 
    117     for (uint32_t i=0; i<_param._nb_prediction; i++)
    118       {
    119         (*(component_RegisterFile-> in_READ_VAL      [i])) (*( in_PREDICT_VAL      [i]));
    120         (*(component_RegisterFile->out_READ_ACK      [i])) (*(out_PREDICT_ACK      [i]));
    121         (*(component_RegisterFile-> in_READ_ADDRESS  [i])) (*( in_PREDICT_ADDRESS  [i]));
    122         (*(component_RegisterFile->out_READ_DATA     [i])) (*(out_PREDICT_HISTORY  [i]));   
    123       }
    124    
    125     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    126       {
    127         (*(component_RegisterFile-> in_WRITE_VAL     [i])) (*(    in_BRANCH_COMPLETE_VAL      [i]));
    128         (*(component_RegisterFile->out_WRITE_ACK     [i])) (*(   out_BRANCH_COMPLETE_ACK      [i]));
    129         (*(component_RegisterFile-> in_WRITE_ADDRESS [i])) (*(    in_BRANCH_COMPLETE_ADDRESS  [i]));
    130         (*(component_RegisterFile-> in_WRITE_DATA    [i])) (*(signal_BRANCH_COMPLETE_HISTORY  [i]));   
    131       }
     191#ifdef POSITION
     192        _component->interface_map (_name+"_Counter","counter_"+toString(i),
     193                                   _name           ,"branch_complete_"+toString(i));
     194
     195#endif
     196
     197        _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_DATA"    , _name                , "in_BRANCH_COMPLETE_"+toString(i)+"_HISTORY");
     198        _component->port_map(_name+"_Counter", "in_COUNTER_" +toString(i)+"_ADDSUB"  , _name                , "in_BRANCH_COMPLETE_"+toString(i)+"_DIRECTION");
     199        _component->port_map(_name+"_Counter", "out_COUNTER_"+toString(i)+"_DATA"    , _name+"_RegisterFile", "in_WRITE_"+toString(i)+"_DATA");
     200      }
     201
     202#ifdef POSITION
     203    _component->generate_file();
     204#endif
    132205
    133206    log_printf(FUNC,Pattern_History_Table,"allocation","End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_deallocation.cpp

    r15 r42  
    2222    log_printf(FUNC,Pattern_History_Table,"deallocation","Begin");
    2323
    24     delete in_CLOCK;
    25     delete in_NRESET;
     24    delete     in_CLOCK;
     25    delete     in_NRESET;
    2626
    27     for (uint32_t i=0; i<_param._nb_prediction; i++)
    28       {
    29         delete  in_PREDICT_VAL     [i];
    30         delete out_PREDICT_ACK     [i];
    31         delete  in_PREDICT_ADDRESS [i];
    32         delete out_PREDICT_HISTORY [i];
    33       }
     27    delete []  in_PREDICT_VAL    ;
     28    delete [] out_PREDICT_ACK    ;
     29    delete []  in_PREDICT_ADDRESS;
     30    delete [] out_PREDICT_HISTORY;
    3431
    35     delete  in_PREDICT_VAL    ;
    36     delete out_PREDICT_ACK    ;
    37     delete  in_PREDICT_ADDRESS;
    38     delete out_PREDICT_HISTORY;
    39 
    40      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    41        {
    42          delete  in_BRANCH_COMPLETE_VAL       [i];
    43          delete out_BRANCH_COMPLETE_ACK       [i];
    44          delete  in_BRANCH_COMPLETE_ADDRESS   [i];
    45          delete  in_BRANCH_COMPLETE_HISTORY   [i];
    46          delete  in_BRANCH_COMPLETE_DIRECTION [i];
    47        }
    48     delete  in_BRANCH_COMPLETE_VAL    ;
    49     delete out_BRANCH_COMPLETE_ACK    ;
    50     delete  in_BRANCH_COMPLETE_ADDRESS;
    51     delete  in_BRANCH_COMPLETE_HISTORY;
    52     delete  in_BRANCH_COMPLETE_DIRECTION;
     32    delete []  in_BRANCH_COMPLETE_VAL    ;
     33    delete [] out_BRANCH_COMPLETE_ACK    ;
     34    delete []  in_BRANCH_COMPLETE_ADDRESS;
     35    delete []  in_BRANCH_COMPLETE_HISTORY;
     36    delete []  in_BRANCH_COMPLETE_DIRECTION;
    5337
    5438     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    5539    delete component_Counter;
    5640    delete component_RegisterFile;
     41   
     42    delete _component;
    5743
    5844    log_printf(FUNC,Pattern_History_Table,"deallocation","End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl.cpp

    r2 r42  
    2222  {
    2323    log_printf(FUNC,Pattern_History_Table,"vhdl","Begin");
    24     Vhdl vhdl (_name);
     24    Vhdl * vhdl = new Vhdl (_name);
    2525
    26     vhdl.set_library_work (_name + "_Pack");
    27     vhdl.set_library_work (_name + "_RegisterFile_Pack");
    28     vhdl.set_library_work (_name + "_Counter_Pack");
     26    _interfaces->set_port(vhdl);
     27    _component->vhdl_instance(vhdl);
    2928
    30     vhdl_port        (vhdl);
    3129    vhdl_declaration (vhdl);
    3230    vhdl_body        (vhdl);
    3331
    34     vhdl.generate_file();
     32    vhdl->generate_file();
     33
     34    delete vhdl;
     35
    3536    log_printf(FUNC,Pattern_History_Table,"vhdl","End");
    3637

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp

    r15 r42  
    1818
    1919
    20   void Pattern_History_Table::vhdl_body (Vhdl & vhdl)
     20  void Pattern_History_Table::vhdl_body (Vhdl * & vhdl)
    2121  {
    2222    log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin");
    2323
    24 //     vhdl.set_body ("-- Output : always at '1'");
     24//     vhdl->set_body ("-- Output : always at '1'");
    2525//     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    26 //       vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
     26//       vhdl->set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
    2727//     for (uint32_t i=0; i<_param._nb_prediction     ; i++)
    28 //       vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
    29 //     vhdl.set_body ("");
    30 
    31     list<string> list_port_map;
    32 
    33     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    34       {
    35         vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+"     ","    in_BRANCH_COMPLETE_HISTORY_"+toString(i));
    36         vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+"   ","    in_BRANCH_COMPLETE_DIRECTION_"+toString(i)    );
    37         vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+"     ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
    38       }
    39     vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map);
    40 
    41 
    42     list_port_map.clear();
    43     vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK ");
    44     vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET");
    45 
    46     for (uint32_t i=0; i<_param._nb_prediction; i++)
    47       {
    48         vhdl.set_body_component_port_map (list_port_map," in_READ_VAL_"+toString(i)+"     "," in_PREDICT_VAL_"+toString(i));
    49         vhdl.set_body_component_port_map (list_port_map,"out_READ_ACK_"+toString(i)+"     ","out_PREDICT_ACK_"+toString(i));
    50         vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));
    51         vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+"    ","out_PREDICT_HISTORY_"+toString(i));   
    52       }
    53    
    54     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    55       {
    56         vhdl.set_body_component_port_map (list_port_map," in_WRITE_VAL_"+toString(i)+"    ","    in_BRANCH_COMPLETE_VAL_"+toString(i)+"");
    57         vhdl.set_body_component_port_map (list_port_map,"out_WRITE_ACK_"+toString(i)+"    ","   out_BRANCH_COMPLETE_ACK_"+toString(i)+"");
    58         vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+"","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
    59         vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+"   ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
    60       }
    61     vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);
     28//       vhdl->set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
     29//     vhdl->set_body ("");
    6230
    6331    log_printf(FUNC,Pattern_History_Table,"vhdl_body","End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_port.cpp

    r15 r42  
    1818
    1919
    20   void Pattern_History_Table::vhdl_port (Vhdl & vhdl)
    21   {
    22     log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin");
     20//   void Pattern_History_Table::vhdl_port (Vhdl * & vhdl)
     21//   {
     22//     log_printf(FUNC,Pattern_History_Table,"vhdl_port","Begin");
    2323
    24     vhdl.set_port (" in_CLOCK" , IN, 1);
    25     vhdl.set_port (" in_NRESET", IN, 1);
     24//     _interfaces->set_port(vhdl);
    2625
    27     for (uint32_t i=0; i<_param._nb_prediction; i++)
    28       {
    29         vhdl.set_port(" in_PREDICT_VAL_"+toString(i)+"               ", IN, 1);
    30         vhdl.set_port("out_PREDICT_ACK_"+toString(i)+"               ",OUT, 1);
    31         vhdl.set_port(" in_PREDICT_ADDRESS_"+toString(i)+"           ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
    32         vhdl.set_port("out_PREDICT_HISTORY_"+toString(i)+"           ",OUT, _param._size_counter);
    33       }
    34      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    35        {
    36          vhdl.set_port (" in_BRANCH_COMPLETE_VAL_"+toString(i)+"      ", IN, 1);
    37          vhdl.set_port ("out_BRANCH_COMPLETE_ACK_"+toString(i)+"      ",OUT, 1);
    38          vhdl.set_port (" in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+"  ", IN, static_cast<uint32_t>(ceil(log2(_param._nb_counter))));
    39          vhdl.set_port (" in_BRANCH_COMPLETE_HISTORY_"+toString(i)+"  ", IN, _param._size_counter);
    40          vhdl.set_port (" in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+"", IN, 1);
    41        }
    42 
    43     log_printf(FUNC,Pattern_History_Table,"vhdl_port","End");
    44   };
     26//     log_printf(FUNC,Pattern_History_Table,"vhdl_port","End");
     27//   };
    4528
    4629}; // end namespace pattern_history_table

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_signal.cpp

    r2 r42  
    1818
    1919
    20   void Pattern_History_Table::vhdl_declaration (Vhdl & vhdl)
     20  void Pattern_History_Table::vhdl_declaration (Vhdl * & vhdl)
    2121  {
    2222    log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","Begin");
    23 
    24     for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    25       vhdl.set_signal  ("signal_BRANCH_COMPLETE_HISTORY_"+toString(i), _param._size_counter);
    2623
    2724    log_printf(FUNC,Pattern_History_Table,"vhdl_declaration","End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_testbench_transition.cpp

    r15 r42  
    2222    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","Begin");
    2323
    24 #ifndef SYSTEMCASS_SPECIFIC
    25     sc_cycle(0);
    26 #endif   
     24    sc_start(0);
    2725
    28     // In order with file Pattern_History_Table_vhdl_testbench_port.cpp
    29     // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    30     // (because we have no control on the ordonnancer's policy)
    31 
    32     _vhdl_testbench->add_input  (PORT_READ( in_NRESET));
    33 
    34     for (uint32_t i=0; i<_param._nb_prediction; i++)
    35       {
    36         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_VAL     [i]));
    37         _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_ACK  [i]));
    38         _vhdl_testbench->add_input  (PORT_READ( in_PREDICT_ADDRESS [i]));
    39         _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_READ_DATA [i]));
    40       //_vhdl_testbench->add_output (PORT_READ(out_PREDICT_HISTORY [i]));
    41       }
    42 
    43      for (uint32_t i=0; i<_param._nb_branch_complete; i++)
    44        {
    45          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_VAL      [i]));
    46          _vhdl_testbench->add_output (PORT_READ(component_RegisterFile->out_WRITE_ACK [i]));
    47          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_ADDRESS  [i]));
    48          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_HISTORY  [i]));
    49          _vhdl_testbench->add_input  (PORT_READ( in_BRANCH_COMPLETE_DIRECTION[i]));
    50        }
    51        
    52     // add_test :
    53     //  - True  : the cycle must be compare with the output of systemC
    54     //  - False : no test
    55     _vhdl_testbench->add_test(true);
    56 
    57     _vhdl_testbench->new_cycle (); // always at the end
     26    _interfaces->testbench();
    5827
    5928    log_printf(FUNC,Pattern_History_Table,"vhdl_testbench_transition","End");
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