Ignore:
Timestamp:
Apr 9, 2014, 11:19:58 PM (11 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer
Files:
14 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.gise

    r136 r137  
    2828    <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/>
    2929    <file xil_pn:fileType="FILE_NCD" xil_pn:name="IP_Timer_guide.ncd" xil_pn:origination="imported"/>
     30    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/>
     31    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/>
     32    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/>
     33    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/>
     34    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MultiMPITest.ngc"/>
     35    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MultiMPITest.ngd"/>
     36    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MultiMPITest.ngr"/>
     37    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="MultiMPITest.pad"/>
     38    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MultiMPITest.par" xil_pn:subbranch="Par"/>
     39    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MultiMPITest.pcf" xil_pn:subbranch="Map"/>
     40    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest.prj"/>
     41    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="MultiMPITest.ptwx"/>
     42    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MultiMPITest.stx"/>
     43    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MultiMPITest.syr"/>
     44    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest.twr" xil_pn:subbranch="Par"/>
     45    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest.twx" xil_pn:subbranch="Par"/>
     46    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MultiMPITest.unroutes" xil_pn:subbranch="Par"/>
     47    <file xil_pn:fileType="FILE_XPI" xil_pn:name="MultiMPITest.xpi"/>
     48    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MultiMPITest.xst"/>
     49    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_envsettings.html"/>
    3050    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_guide.ncd" xil_pn:origination="imported"/>
     51    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.map" xil_pn:subbranch="Map"/>
     52    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.mrp" xil_pn:subbranch="Map"/>
     53    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_map.ncd" xil_pn:subbranch="Map"/>
     54    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/>
     55    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_map.xrpt"/>
     56    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
     57    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/>
     58    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/>
     59    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_par.xrpt"/>
     60    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest_preroute.twr" xil_pn:subbranch="Map"/>
     61    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest_preroute.twx" xil_pn:subbranch="Map"/>
     62    <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_summary.html"/>
     63    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MultiMPITest_summary.xml"/>
     64    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="MultiMPITest_usage.xml"/>
     65    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_xst.xrpt"/>
    3166    <file xil_pn:fileType="FILE_NCD" xil_pn:name="RAM_v_guide.ncd" xil_pn:origination="imported"/>
    3267    <file xil_pn:fileType="FILE_NCD" xil_pn:name="Scheduler_guide.ncd" xil_pn:origination="imported"/>
     68    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
     69    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
     70    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
     71    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
     72    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
     73    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
     74    <file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
     75    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="mpi_test.cmd_log"/>
     76    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="mpi_test.lso"/>
     77    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test.prj"/>
     78    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="mpi_test.syr"/>
     79    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="mpi_test.xst"/>
     80    <file xil_pn:fileType="FILE_HTML" xil_pn:name="mpi_test_envsettings.html"/>
     81    <file xil_pn:fileType="FILE_HTML" xil_pn:name="mpi_test_summary.html"/>
     82    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="mpi_test_xst.xrpt"/>
     83    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
     84    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
     85    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
    3386  </files>
    3487
    3588  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    36     <transform xil_pn:end_ts="1396892054" xil_pn:in_ck="-1335772100541163525" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1396892054">
     89    <transform xil_pn:end_ts="1397065166" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1397065166">
     90      <status xil_pn:value="SuccessfullyRun"/>
     91    </transform>
     92    <transform xil_pn:end_ts="1397065166" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8802460352089655353" xil_pn:start_ts="1397065166">
    3793      <status xil_pn:value="SuccessfullyRun"/>
    3894      <status xil_pn:value="ReadyToRun"/>
     95    </transform>
     96    <transform xil_pn:end_ts="1397065167" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="491076837086602063" xil_pn:start_ts="1397065166">
     97      <status xil_pn:value="SuccessfullyRun"/>
     98      <status xil_pn:value="ReadyToRun"/>
     99      <outfile xil_pn:name="ipcore_dir/mem8k8.ngc"/>
     100      <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/>
     101    </transform>
     102    <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
     103      <status xil_pn:value="SuccessfullyRun"/>
     104      <status xil_pn:value="ReadyToRun"/>
     105    </transform>
     106    <transform xil_pn:end_ts="1397065167" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1397065167">
     107      <status xil_pn:value="SuccessfullyRun"/>
     108      <status xil_pn:value="ReadyToRun"/>
     109    </transform>
     110    <transform xil_pn:end_ts="1397065167" xil_pn:in_ck="-1335772100541163525" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-7782322491054780976" xil_pn:start_ts="1397065167">
     111      <status xil_pn:value="SuccessfullyRun"/>
     112      <status xil_pn:value="ReadyToRun"/>
     113    </transform>
     114    <transform xil_pn:end_ts="1397065167" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4953193664677071463" xil_pn:start_ts="1397065167">
     115      <status xil_pn:value="SuccessfullyRun"/>
     116      <status xil_pn:value="ReadyToRun"/>
     117    </transform>
     118    <transform xil_pn:end_ts="1397065387" xil_pn:in_ck="1277596895833658219" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4264687095207808167" xil_pn:start_ts="1397065167">
     119      <status xil_pn:value="SuccessfullyRun"/>
     120      <status xil_pn:value="WarningsGenerated"/>
     121      <status xil_pn:value="ReadyToRun"/>
     122      <status xil_pn:value="OutOfDateForOutputs"/>
     123      <status xil_pn:value="OutputChanged"/>
     124      <outfile xil_pn:name="MultiMPITest.lso"/>
     125      <outfile xil_pn:name="MultiMPITest.ngc"/>
     126      <outfile xil_pn:name="MultiMPITest.ngr"/>
     127      <outfile xil_pn:name="MultiMPITest.prj"/>
     128      <outfile xil_pn:name="MultiMPITest.stx"/>
     129      <outfile xil_pn:name="MultiMPITest.syr"/>
     130      <outfile xil_pn:name="MultiMPITest.xst"/>
     131      <outfile xil_pn:name="MultiMPITest_xst.xrpt"/>
     132      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
     133      <outfile xil_pn:name="webtalk_pn.xml"/>
     134      <outfile xil_pn:name="xst"/>
     135    </transform>
     136    <transform xil_pn:end_ts="1397065387" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1397065387">
     137      <status xil_pn:value="SuccessfullyRun"/>
     138      <status xil_pn:value="ReadyToRun"/>
     139    </transform>
     140    <transform xil_pn:end_ts="1397065428" xil_pn:in_ck="-8086002020225495248" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="6806536488953865956" xil_pn:start_ts="1397065387">
     141      <status xil_pn:value="SuccessfullyRun"/>
     142      <status xil_pn:value="ReadyToRun"/>
     143      <outfile xil_pn:name="MultiMPITest.bld"/>
     144      <outfile xil_pn:name="MultiMPITest.ngd"/>
     145      <outfile xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
     146      <outfile xil_pn:name="_ngo"/>
     147      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
     148    </transform>
     149    <transform xil_pn:end_ts="1397065815" xil_pn:in_ck="2034496922163271928" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="-9088675071633060577" xil_pn:start_ts="1397065428">
     150      <status xil_pn:value="SuccessfullyRun"/>
     151      <status xil_pn:value="WarningsGenerated"/>
     152      <status xil_pn:value="ReadyToRun"/>
     153      <outfile xil_pn:name="MultiMPITest.pcf"/>
     154      <outfile xil_pn:name="MultiMPITest_map.map"/>
     155      <outfile xil_pn:name="MultiMPITest_map.mrp"/>
     156      <outfile xil_pn:name="MultiMPITest_map.ncd"/>
     157      <outfile xil_pn:name="MultiMPITest_map.ngm"/>
     158      <outfile xil_pn:name="MultiMPITest_map.xrpt"/>
     159      <outfile xil_pn:name="MultiMPITest_summary.xml"/>
     160      <outfile xil_pn:name="MultiMPITest_usage.xml"/>
     161      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
     162    </transform>
     163    <transform xil_pn:end_ts="1397066096" xil_pn:in_ck="-7713434038111607791" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4101483914851371285" xil_pn:start_ts="1397065815">
     164      <status xil_pn:value="SuccessfullyRun"/>
     165      <status xil_pn:value="WarningsGenerated"/>
     166      <status xil_pn:value="ReadyToRun"/>
     167      <outfile xil_pn:name="MultiMPITest.ncd"/>
     168      <outfile xil_pn:name="MultiMPITest.pad"/>
     169      <outfile xil_pn:name="MultiMPITest.par"/>
     170      <outfile xil_pn:name="MultiMPITest.ptwx"/>
     171      <outfile xil_pn:name="MultiMPITest.unroutes"/>
     172      <outfile xil_pn:name="MultiMPITest.xpi"/>
     173      <outfile xil_pn:name="MultiMPITest_pad.csv"/>
     174      <outfile xil_pn:name="MultiMPITest_pad.txt"/>
     175      <outfile xil_pn:name="MultiMPITest_par.xrpt"/>
     176      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
     177    </transform>
     178    <transform xil_pn:end_ts="1397066096" xil_pn:in_ck="2034496922163271796" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1397066041">
     179      <status xil_pn:value="SuccessfullyRun"/>
     180      <status xil_pn:value="ReadyToRun"/>
     181      <status xil_pn:value="OutOfDateForOutputs"/>
     182      <status xil_pn:value="OutputChanged"/>
     183      <outfile xil_pn:name="MultiMPITest.twr"/>
     184      <outfile xil_pn:name="MultiMPITest.twx"/>
     185      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
     186    </transform>
     187    <transform xil_pn:end_ts="1397066405" xil_pn:in_ck="-7713434038111607791" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1397066336">
     188      <status xil_pn:value="SuccessfullyRun"/>
     189      <status xil_pn:value="ReadyToRun"/>
     190      <outfile xil_pn:name="MultiMPITest_preroute.twr"/>
     191      <outfile xil_pn:name="MultiMPITest_preroute.twx"/>
     192      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
    39193    </transform>
    40194  </transforms>

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.xise

    r136 r137  
    3333    <file xil_pn:name="../NoC/Crossbar.vhd" xil_pn:type="FILE_VHDL">
    3434      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
    35       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     35      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    3636      <library xil_pn:name="NoCLib"/>
    3737    </file>
    3838    <file xil_pn:name="../NoC/Crossbit.vhd" xil_pn:type="FILE_VHDL">
    3939      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
    40       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     40      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    4141      <library xil_pn:name="NoCLib"/>
    4242    </file>
    4343    <file xil_pn:name="../NoC/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
    4444      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
    45       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     45      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    4646      <library xil_pn:name="NoCLib"/>
    4747    </file>
    … …  
    5353    <file xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    5454      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
    55       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     55      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    5656      <library xil_pn:name="NoCLib"/>
    5757    </file>
    5858    <file xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
    5959      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
    60       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     60      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    6161      <library xil_pn:name="NoCLib"/>
    6262    </file>
    … …  
    6868    <file xil_pn:name="../NoC/Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
    6969      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
    70       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     70      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    7171      <library xil_pn:name="NoCLib"/>
    7272    </file>
    7373    <file xil_pn:name="../NoC/proto_send.vhd" xil_pn:type="FILE_VHDL">
    7474      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
    75       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     75      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    7676      <library xil_pn:name="NoCLib"/>
    7777    </file>
    … …  
    8383    <file xil_pn:name="../NoC/Scheduler.vhd" xil_pn:type="FILE_VHDL">
    8484      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
    85       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     85      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    8686      <library xil_pn:name="NoCLib"/>
    8787    </file>
    … …  
    168168    <file xil_pn:name="../NoC/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
    169169      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
    170       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     170      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    171171      <library xil_pn:name="NoCLib"/>
    172172    </file>
    … …  
    183183    <file xil_pn:name="../Core_MPI/CORE_MPI.vhd" xil_pn:type="FILE_VHDL">
    184184      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
    185       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     185      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    186186      <library xil_pn:name="MPI_HCL"/>
    187187    </file>
    188188    <file xil_pn:name="../Core_MPI/DEMUX1.vhd" xil_pn:type="FILE_VHDL">
    189189      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
    190       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     190      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    191191      <library xil_pn:name="MPI_HCL"/>
    192192    </file>
    193193    <file xil_pn:name="../Core_MPI/DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL">
    194194      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
    195       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     195      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    196196      <library xil_pn:name="MPI_HCL"/>
    197197    </file>
    198198    <file xil_pn:name="../Core_MPI/Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL">
    199199      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
    200       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     200      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    201201      <library xil_pn:name="MPI_HCL"/>
    202202    </file>
    203203    <file xil_pn:name="../Core_MPI/EX1_FSM.vhd" xil_pn:type="FILE_VHDL">
    204204      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
    205       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     205      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    206206      <library xil_pn:name="MPI_HCL"/>
    207207    </file>
    208208    <file xil_pn:name="../Core_MPI/EX2_FSM.vhd" xil_pn:type="FILE_VHDL">
    209209      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
    210       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     210      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    211211      <library xil_pn:name="MPI_HCL"/>
    212212    </file>
    213213    <file xil_pn:name="../Core_MPI/EX3_FSM.vhd" xil_pn:type="FILE_VHDL">
    214214      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
    215       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     215      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    216216      <library xil_pn:name="MPI_HCL"/>
    217217    </file>
    218218    <file xil_pn:name="../Core_MPI/EX4_FSM.vhd" xil_pn:type="FILE_VHDL">
    219219      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
    220       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     220      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    221221      <library xil_pn:name="MPI_HCL"/>
    222222    </file>
    … …  
    228228    <file xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL">
    229229      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
    230       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     230      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    231231      <library xil_pn:name="MPI_HCL"/>
    232232    </file>
    … …  
    248248    <file xil_pn:name="../Core_MPI/load_instr.vhd" xil_pn:type="FILE_VHDL">
    249249      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
    250       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     250      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    251251      <library xil_pn:name="MPI_HCL"/>
    252252    </file>
    … …  
    258258    <file xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL">
    259259      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
    260       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     260      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    261261      <library xil_pn:name="MPI_HCL"/>
    262262    </file>
    263263    <file xil_pn:name="../Core_MPI/MPI_NOC.vhd" xil_pn:type="FILE_VHDL">
    264264      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
    265       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     265      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    266266      <library xil_pn:name="MPI_HCL"/>
    267267    </file>
    … …  
    273273    <file xil_pn:name="../Core_MPI/MPI_RMA.vhd" xil_pn:type="FILE_VHDL">
    274274      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
    275       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     275      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    276276      <library xil_pn:name="MPI_HCL"/>
    277277    </file>
    278278    <file xil_pn:name="../Core_MPI/MultiMPITest.vhd" xil_pn:type="FILE_VHDL">
    279279      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
    280       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     280      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    281281    </file>
    282282    <file xil_pn:name="../Core_MPI/MUX1.vhd" xil_pn:type="FILE_VHDL">
    283283      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
    284       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     284      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    285285      <library xil_pn:name="MPI_HCL"/>
    286286    </file>
    287287    <file xil_pn:name="../Core_MPI/MUX8.vhd" xil_pn:type="FILE_VHDL">
    288288      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
    289       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     289      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    290290      <library xil_pn:name="MPI_HCL"/>
    291291    </file>
    292292    <file xil_pn:name="../Core_MPI/Packet_type.vhd" xil_pn:type="FILE_VHDL">
    293293      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
    294       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     294      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    295295      <library xil_pn:name="MPI_HCL"/>
    296296    </file>
    … …  
    312312    <file xil_pn:name="../Core_MPI/round_robbin_machine.vhd" xil_pn:type="FILE_VHDL">
    313313      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
    314       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     314      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    315315      <library xil_pn:name="MPI_HCL"/>
    316316    </file>
    317317    <file xil_pn:name="../Core_MPI/SetBit.vhd" xil_pn:type="FILE_VHDL">
    318318      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
    319       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     319      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    320320      <library xil_pn:name="MPI_HCL"/>
    321321    </file>
    … …  
    327327    <file xil_pn:name="../HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">
    328328      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
    329       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     329      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
    330330    </file>
    331331    <file xil_pn:name="../Hold_FSM.vhd" xil_pn:type="FILE_VHDL">
    332332      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
    333       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     333      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
    334334    </file>
    335335    <file xil_pn:name="../HT_process.vhd" xil_pn:type="FILE_VHDL">
    336336      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
    337       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     337      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
    338338    </file>
    339339    <file xil_pn:name="../IP_Timer.vhd" xil_pn:type="FILE_VHDL">
    340340      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
    341       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     341      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    342342    </file>
    343343    <file xil_pn:name="../PE.vhd" xil_pn:type="FILE_VHDL">
    344344      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
    345       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     345      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
    346346    </file>
    347347    <file xil_pn:name="../mpi_test.vhd" xil_pn:type="FILE_VHDL">
    … …  
    355355    <file xil_pn:name="ipcore_dir/mem8k8.xco" xil_pn:type="FILE_COREGEN">
    356356      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
    357       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     357      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
    358358    </file>
    359359    <file xil_pn:name="../NOC/Def_Request.vhd" xil_pn:type="FILE_VHDL">
    … …  
    371371
    372372  <properties>
    373     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    374     <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     373    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
     374    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
    375375    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    376376    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    386386    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    387387    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
     388    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
     389    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
    388390    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    389391    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    392394    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    393395    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    394     <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    395     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
     396    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
     397    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
    396398    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
    397399    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    401403    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    402404    <property xil_pn:name="Compiled Library Directory" xil_pn:value="modelsim10.1c" xil_pn:valueState="non-default"/>
     405    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    403406    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
    404407    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     408    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     409    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     410    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     411    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    405412    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    406     <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     413    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
    407414    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    408415    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    410417    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    411418    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    412     <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     419    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    413420    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    414421    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    416423    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    417424    <property xil_pn:name="Custom Do File Behavioral" xil_pn:value="wave.do" xil_pn:valueState="non-default"/>
     425    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
     426    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
    418427    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    419428    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
    420429    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    421430    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    422     <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
    423     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    424     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
     431    <property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/>
     432    <property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>
     433    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
    425434    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
     435    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
    426436    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    427437    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    428     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    429438    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    430439    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    431     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     440    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    432441    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    433     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     442    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
    434443    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    435     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
     444    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
    436445    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    437     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    438446    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
    439     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     447    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
    440448    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    441     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    442     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    443     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    444     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     449    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
     450    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    445451    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    446452    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    448454    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    449455    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    450     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
     456    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
    451457    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    452458    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    453459    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    454460    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
     461    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
    455462    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    456463    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    458465    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    459466    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    460     <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    461     <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    462467    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    463468    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    480485    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    481486    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    482     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     487    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
    483488    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    484489    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    485490    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     491    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
    486492    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
     493    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
    487494    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    488495    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
    489496    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    490497    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    491     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
    492     <property xil_pn:name="Implementation Top File" xil_pn:value="../mpi_test.vhd" xil_pn:valueState="non-default"/>
    493     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test" xil_pn:valueState="non-default"/>
     498    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
     499    <property xil_pn:name="Implementation Top File" xil_pn:value="../Core_MPI/MultiMPITest.vhd" xil_pn:valueState="non-default"/>
     500    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mpi_test/uut" xil_pn:valueState="non-default"/>
    494501    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    495502    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    503510    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    504511    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     512    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
    505513    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    506514    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    … …  
    521529    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
    522530    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
    523     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    524531    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    525532    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    531538    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    532539    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    533     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    534     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    535     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    536     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    537     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    538540    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
    539541    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    540542    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    541     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
     543    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="non-default"/>
    542544    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    543545    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    544546    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
    545     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     547    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    546548    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    547549    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    548     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     550    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    549551    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    550552    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    … …  
    566568    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    567569    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    568     <property xil_pn:name="Output File Name" xil_pn:value="mpi_test" xil_pn:valueState="default"/>
     570    <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    569571    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    570572    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
    571573    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    572574    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    573     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
     575    <property xil_pn:name="Package" xil_pn:value="ffg1761" xil_pn:valueState="non-default"/>
    574576    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    575577    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    576578    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    577579    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    578     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    579     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     580    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
    580581    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    581582    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    582583    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    583     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="mpi_test_map.vhd" xil_pn:valueState="default"/>
    584     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="mpi_test_timesim.vhd" xil_pn:valueState="default"/>
    585     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="mpi_test_synthesis.vhd" xil_pn:valueState="default"/>
    586     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="mpi_test_translate.vhd" xil_pn:valueState="default"/>
    587     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     584    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/>
     585    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/>
     586    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/>
     587    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/>
     588    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
     589    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
    588590    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    589591    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    603605    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    604606    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    605     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
     607    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
    606608    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    607609    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    608610    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    609     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="mpi_test" xil_pn:valueState="default"/>
     611    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    610612    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    611613    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    620622    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    621623    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    622     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     624    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
     625    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
    623626    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    624627    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    626629    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    627630    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     631    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
    628632    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    629633    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    … …  
    634638    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    635639    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    636     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    637     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     640    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
    638641    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    639     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     642    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
    640643    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    641644    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
    … …  
    656659    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    657660    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    658     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    659     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     661    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
     662    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
     663    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
    660664    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    661665    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    … …  
    688692    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    689693    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    690     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     694    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
    691695    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
    692696    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    693697    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
     698    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
    694699    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    695700    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    696701    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    697702    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     703    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
    698704    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    699705    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    700     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    701706    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    702707    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
    … …  
    705710    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    706711    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    707     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    708     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    709     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
     712    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
     713    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
     714    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
     715    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    710716    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
    711717    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    … …  
    716722    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|mpi_test|behavior" xil_pn:valueState="non-default"/>
    717723    <property xil_pn:name="PROP_DesignName" xil_pn:value="Test_Timer" xil_pn:valueState="non-default"/>
    718     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     724    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>
    719725    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    720726    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs

    r115 r137  
    66     users do not edit the contents of this file. -->
    77<messages>
    8 <msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem_4k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
     8<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem8k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
     9</msg>
     10
     11<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;mem8k8&apos; already exists in the project. Output products for this core may be overwritten.</arg>
     12</msg>
     13
     14<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;mem8k8&apos;...</arg>
     15</msg>
     16
     17<msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol.
     18</msg>
     19
     20<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
    921</msg>
    1022

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs

    r115 r137  
    99
    1010<messages>
    11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem_4k8.vhd&quot; into library work</arg>
     11<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd&quot; into library work</arg>
    1212</msg>
    1313

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vhd

    r115 r137  
    8585      c_disable_warn_bhv_coll => 0,
    8686      c_disable_warn_bhv_range => 0,
    87       c_family => "spartan6",
     87      c_family => "artix7",
    8888      c_has_axi_id => 0,
    8989      c_has_ena => 1,
    … …  
    131131      c_write_width_a => 8,
    132132      c_write_width_b => 8,
    133       c_xdevicefamily => "spartan6"
     133      c_xdevicefamily => "artix7"
    134134    );
    135135-- synthesis translate_on

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xco

    r115 r137  
    22#
    33# Xilinx Core Generator version 13.3
    4 # Date: Mon Mar 03 16:26:23 2014
     4# Date: Wed Apr 09 13:43:42 2014
    55#
    66##############################################################
    … …  
    2323SET createndf = false
    2424SET designentry = VHDL
    25 SET device = xc6slx45
    26 SET devicefamily = spartan6
     25SET device = xc7a100t
     26SET devicefamily = artix7
    2727SET flowvendor = Other
    2828SET formalverification = false
    … …  
    103103# END Extra information
    104104GENERATE
    105 # CRC: c197a96c
     105# CRC:  7a5cdcc

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xise

    r115 r137  
    3131  <properties>
    3232    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    33     <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
    34     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
     33    <property xil_pn:name="Device" xil_pn:value="xc7a100t" xil_pn:valueState="non-default"/>
     34    <property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/>
    3535    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
    3636    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem8k8|mem8k8_a" xil_pn:valueState="non-default"/>
    3737    <property xil_pn:name="Implementation Top File" xil_pn:value="mem8k8.vhd" xil_pn:valueState="non-default"/>
    3838    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem8k8" xil_pn:valueState="non-default"/>
    39     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
     39    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
    4040    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    4141    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
    … …  
    5050    <!--                                                                                  -->
    5151    <property xil_pn:name="PROP_DesignName" xil_pn:value="mem8k8" xil_pn:valueState="non-default"/>
    52     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    53     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-03-03T17:27:19" xil_pn:valueState="non-default"/>
    54     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A940284CDED41488E19E27EE9472069" xil_pn:valueState="non-default"/>
     52    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
     53    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-09T15:44:54" xil_pn:valueState="non-default"/>
     54    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0A14F46BA6CA40C6870EDAC9BBAA198D" xil_pn:valueState="non-default"/>
    5555    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    5656    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd

    r115 r137  
    6868-- (Refer to the SIM Parameters table in the datasheet for more information on
    6969-- the these parameters.)
    70 --    C_FAMILY                    :  spartan6
    71 --    C_XDEVICEFAMILY             :  spartan6
     70--    C_FAMILY                    :  artix7
     71--    C_XDEVICEFAMILY             :  artix7
    7272--    C_INTERFACE_TYPE            :  0
    7373--    C_AXI_TYPE                  :  1

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat

    r115 r137  
    2424
    2525echo 'Running ngdbuild'
    26 ngdbuild -p xc6slx45-csg324-3 mem8k8_top
     26ngdbuild -p xc7a100t-csg324-3 mem8k8_top
    2727
    2828echo 'Running map'

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh

    r115 r137  
    2323
    2424echo 'Running ngdbuild'
    25 ngdbuild -p xc6slx45-csg324-3 mem8k8_top
     25ngdbuild -p xc7a100t-csg324-3 mem8k8_top
    2626
    2727echo 'Running map'

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl

    r115 r137  
    4646
    4747
    48 set device xc6slx45csg324-3
     48set device xc7a100tcsg324-3
    4949set projName mem8k8
    5050set design mem8k8

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr

    r115 r137  
    22-ifmt VHDL
    33-ent mem8k8_top
    4 -p xc6slx45-csg324-3
     4-p xc7a100t-csg324-3
    55-ifn xst.prj
    66-write_timing_constraints No

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs

    r115 r137  
    99
    1010<messages>
    11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/blk_mem_gen_v6_2.vhd&quot; into library work</arg>
     11<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd&quot; into library work</arg>
    1212</msg>
    1313

  • PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs

    r115 r137  
    99</msg>
    1010
    11 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    12 </msg>
    13 
    14 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    15 </msg>
    16 
    17 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    18 </msg>
    19 
    20 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    21 </msg>
    22 
    23 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    24 </msg>
    25 
    26 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    27 </msg>
    28 
    29 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    30 </msg>
    31 
    32 <msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">2</arg>
    33 </msg>
    34 
    35 <msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
    36 </msg>
    37 
    38 <msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
     11<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">4</arg>
     12</msg>
     13
     14<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">4</arg>
     15</msg>
     16
     17<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">4</arg>
     18</msg>
     19
     20<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>)      : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">8192</arg>    u:<arg fmt="%d" index="6">4</arg>
    3921</msg>
    4022
    … …  
    5133</msg>
    5234
    53 <msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_wrapper_s6.vhd" Line 490: Net &lt;<arg fmt="%s" index="1">douta_i[1]</arg>&gt; does not have a driver.
    54 </msg>
    55 
    56 <msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1544: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
    57 </msg>
    58 
    59 <msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1557: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
    60 </msg>
    61 
    62 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">douta</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    63 </msg>
    64 
    65 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    66 </msg>
    67 
    68 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    69 </msg>
    70 
    71 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    72 </msg>
    73 
    74 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    75 </msg>
    76 
    77 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    78 </msg>
    79 
    80 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    81 </msg>
    82 
    83 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    84 </msg>
    85 
    86 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    87 </msg>
    88 
    89 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    90 </msg>
    91 
    92 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    93 </msg>
    94 
    95 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    96 </msg>
    97 
    98 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    99 </msg>
    100 
    101 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    102 </msg>
    103 
    104 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    105 </msg>
    106 
    107 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    108 </msg>
    109 
    110 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    111 </msg>
    112 
    113 <msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     35<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_wrapper_v6.vhd" Line 510: Net &lt;<arg fmt="%s" index="1">douta_i[3]</arg>&gt; does not have a driver.
     36</msg>
     37
     38<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">douta</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     39</msg>
     40
     41<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     42</msg>
     43
     44<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     45</msg>
     46
     47<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     48</msg>
     49
     50<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     51</msg>
     52
     53<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     54</msg>
     55
     56<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     57</msg>
     58
     59<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     60</msg>
     61
     62<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     63</msg>
     64
     65<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     66</msg>
     67
     68<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     69</msg>
     70
     71<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     72</msg>
     73
     74<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     75</msg>
     76
     77<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     78</msg>
     79
     80<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     81</msg>
     82
     83<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     84</msg>
     85
     86<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
     87</msg>
     88
     89<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
    11490</msg>
    11591
    … …  
    252228</msg>
    253229
    254 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    255 </msg>
    256 
    257 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     230<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     231</msg>
     232
     233<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    258234</msg>
    259235
    … …  
    276252</msg>
    277253
    278 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
    279 </msg>
    280 
    281 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
    282 </msg>
    283 
    284 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
    285 </msg>
    286 
    287 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
    288 </msg>
    289 
    290254<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    291255</msg>
    … …  
    297261</msg>
    298262
     263<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     264</msg>
     265
     266<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     267</msg>
     268
     269<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SSRA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     270</msg>
     271
     272<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     273</msg>
     274
     275<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SSRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     276</msg>
     277
    299278<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    300279</msg>
    … …  
    303282</msg>
    304283
     284<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_v6_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
     285</msg>
     286
    305287<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    306288</msg>
    … …  
    312294</msg>
    313295
    314 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    315 </msg>
    316 
    317 <msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
     296<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     297</msg>
     298
     299<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SSRA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     300</msg>
     301
     302<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     303</msg>
     304
     305<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SSRB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    318306</msg>
    319307
    … …  
    324312</msg>
    325313
     314<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_v6_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
     315</msg>
     316
    326317<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    327318</msg>
    … …  
    330321</msg>
    331322
    332 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    333 </msg>
    334 
    335 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    336 </msg>
    337 
    338 <msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
    339 </msg>
    340 
    341 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    342 </msg>
    343 
    344 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     323<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DOUTA_I&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     324</msg>
     325
     326<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;12:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     327</msg>
     328
     329<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     330</msg>
     331
     332<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     333</msg>
     334
     335<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
     336</msg>
     337
     338<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    345339</msg>
    346340
    … …  
    351345</msg>
    352346
    353 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    354 </msg>
    355 
    356 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    357 </msg>
    358 
    359 <msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_3</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
    360 </msg>
    361 
    362 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    363 </msg>
    364 
    365 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    366 </msg>
    367 
    368 <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    369 </msg>
    370 
    371 <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    372 </msg>
    373 
    374 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    375 </msg>
    376 
    377 <msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    378 </msg>
    379 
    380 <msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_4</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
    381 </msg>
    382 
    383 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DOUTA_I&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    384 </msg>
    385 
    386 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;12:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    387 </msg>
    388 
    389 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    390 </msg>
    391 
    392 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    393 </msg>
    394 
    395 <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    396 </msg>
    397 
    398 <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    399 </msg>
    400 
    401 <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    402 </msg>
    403 
    404 <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
    405 </msg>
    406 
    407347<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
    408348</msg>
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