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Changeset 65 for PROJECT_CORE_MPI/SWITCH_GEN
- Timestamp:
- Apr 22, 2013, 11:35:33 AM (12 years ago)
- Location:
- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03
- Files:
-
- 15 edited
-
Arbiter.vhd (modified) (2 diffs)
-
CoreTypes.vhd (modified) (1 diff)
-
Crossbar.vhd (modified) (139 diffs)
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Crossbit.vhd (modified) (18 diffs)
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FIFO_256_FWFT.vhd (modified) (3 diffs)
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INPUT_PORT_MODULE.vhd (modified) (22 diffs)
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Proto_receiv.vhd (modified) (1 diff)
-
SCHEDULER12_12.VHD (modified) (2 diffs)
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SCHEDULER13_13.VHD (modified) (2 diffs)
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SCHEDULER14_14.VHD (modified) (2 diffs)
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SCHEDULER15_15.VHD (modified) (2 diffs)
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SCHEDULER16_16.VHD (modified) (2 diffs)
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SWITCH_GEN.vhd (modified) (21 diffs)
-
Scheduler.vhd (modified) (10 diffs)
-
proto_send.vhd (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Arbiter.vhd
r22 r65 46 46 signal grant_signal : STD_LOGIC; 47 47 --signal not_fifo_full : STD_LOGIC; 48 signal Mask : STD_LOGIC; 48 signal Mask : STD_LOGIC:='0'; 49 signal RNW : std_logic:='0'; 49 50 begin 50 51 --Grant<=grant_signal; -- Grant n'a pas été déclarée InOut 51 52 Mask <= P AND (not Fifo_full); 52 process(Mask, Request, North, West)-- genere de la logique purement combinatoire 53 RNW<= Request And North And West; 54 process(Mask, RNW, North, West)-- genere de la logique purement combinatoire 53 55 begin 54 56 if Mask ='0' then --cellule inactive … … 57 59 East <= '1'; 58 60 else 59 Grant <= R equest And North And West;60 South <= (North) And (Not (R equest And North And West));61 East <= (West) And (Not (R equest And North And West));61 Grant <= RNW; 62 South <= (North) And (Not (RNW)); 63 East <= (West) And (Not (RNW)); 62 64 end if; 63 65 end process; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd
r45 r65 24 24 CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566; 25 25 CONSTANT CORE_Rank2port_BASE :NATURAL:=32; 26 CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base; 26 27 CONSTANT WIN0_ADR :natural :=4; 27 28 CONSTANT WIN1_ADR :natural :=14; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd
r22 r65 1 1 ---------------------------------------------------------------------------------- 2 2 -- Company: 3 -- Engineer: KIEGAING EMMANUEL 3 -- Engineer: KIEGAING EMMANUEL / GAMOM NGOUNOU 4 4 -- 5 5 -- Create Date: 11:48:18 06/19/2011 … … 16 16 -- a été retiré les signaux inutilisées comme fp, port_source, etc... 17 17 -- Revision 0.01 - File Created 18 -- Additional Comments: 18 -- Revision 0.02 Ajout des signaux clk et reset 19 -- Additional Comments: pour la gestion du pipeline 19 20 -- 20 21 ---------------------------------------------------------------------------------- … … 33 34 generic 34 35 ( 35 number_of_crossbar_ports: positive := 436 number_of_crossbar_ports: positive := 8 36 37 ); 37 Port ( Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 38 Port ( clk : in STD_LOGIC; 39 reset : in STD_LOGIC; --pour gérer le pipeline 40 Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 38 41 Port2_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 39 42 Port3_in : in STD_LOGIC_VECTOR (Word-1 downto 0); … … 115 118 number_of_ports : positive := 4 116 119 ); 117 Port ( Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 120 Port ( clk,reset : in std_logic; 121 Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 118 122 Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1); 119 123 Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1)); 120 124 END COMPONENT; 121 125 signal ctrl_buf: STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1):=(others=>'0'); 126 --signal ctrl_chg:std_logic:='0'; 122 127 begin 123 128 -- La matrice interconnectee 124 129 -- le circuit genere depend du parametre generique nombre de ports 125 130 --ctrl_chg<=all_zeros(ctrl_buf xor ctrl); --sur chaque changement du mot de contrôle, mettre à jour ce registre 131 --ctrl_proc:process(ctrl) 132 -- begin 133 ctrl_buf<=ctrl; 134 -- end process; 126 135 --======================crossbar 2 ports======================= 127 136 … … 133 142 GENERIC MAP(number_of_ports => 2) 134 143 PORT MAP( 135 136 Control => Ctrl, 144 reset => reset, 145 clk =>clk, 146 147 Control => Ctrl_buf, 137 148 Data_In(1) => Port1_in(0), 138 149 Data_In(2) => Port2_in(0), … … 146 157 GENERIC MAP(number_of_ports => 2) 147 158 PORT MAP( 148 149 Control => Ctrl, 159 reset => reset, 160 clk =>clk, 161 162 Control => Ctrl_buf, 150 163 Data_In(1) => Port1_in(1), 151 164 Data_In(2) => Port2_in(1), … … 159 172 GENERIC MAP(number_of_ports => 2) 160 173 PORT MAP( 161 162 Control => Ctrl, 174 reset => reset, 175 clk =>clk, 176 177 Control => Ctrl_buf, 163 178 Data_In(1) => Port1_in(2), 164 179 Data_In(2) => Port2_in(2), … … 172 187 GENERIC MAP(number_of_ports => 2) 173 188 PORT MAP( 174 175 Control => Ctrl, 189 reset => reset, 190 clk =>clk, 191 192 Control => Ctrl_buf, 176 193 Data_In(1) => Port1_in(3), 177 194 Data_In(2) => Port2_in(3), … … 186 203 PORT MAP( 187 204 188 Control => Ctrl, 205 reset => reset, 206 clk =>clk, 207 208 Control => Ctrl_buf, 189 209 Data_In(1) => Port1_in(4), 190 210 Data_In(2) => Port2_in(4), … … 199 219 PORT MAP( 200 220 201 Control => Ctrl, 221 reset => reset, 222 clk=>clk, 223 Control => Ctrl_buf, 202 224 Data_In(1) => Port1_in(5), 203 225 Data_In(2) => Port2_in(5), … … 212 234 PORT MAP( 213 235 214 Control => Ctrl, 236 reset => reset, 237 clk=>clk, 238 Control => Ctrl_buf, 215 239 Data_In(1) => Port1_in(6), 216 240 Data_In(2) => Port2_in(6), … … 225 249 PORT MAP( 226 250 227 Control => Ctrl, 251 reset => reset, 252 clk=>clk, 253 Control => Ctrl_buf, 228 254 Data_In(1) => Port1_in(7), 229 255 Data_In(2) => Port2_in(7), … … 237 263 GENERIC MAP(number_of_ports => 2) 238 264 PORT MAP( 239 240 Control => Ctrl, 265 reset => reset, 266 clk =>clk, 267 268 Control => Ctrl_buf, 241 269 Data_In(1) => Port1_pulse_in, 242 270 Data_In(2) => Port2_pulse_in, … … 258 286 PORT MAP( 259 287 260 Control => Ctrl, 288 reset => reset, 289 clk =>clk, 290 291 Control => Ctrl_buf, 261 292 Data_In(1) => Port1_in(0), 262 293 Data_In(2) => Port2_in(0), … … 272 303 GENERIC MAP(number_of_ports => 3) 273 304 PORT MAP( 274 275 Control => Ctrl, 305 reset => reset, 306 clk =>clk, 307 308 Control => Ctrl_buf, 276 309 Data_In(1) => Port1_in(1), 277 310 Data_In(2) => Port2_in(1), … … 288 321 PORT MAP( 289 322 290 Control => Ctrl, 323 reset => reset, 324 clk=>clk, 325 Control => Ctrl_buf, 291 326 Data_In(1) => Port1_in(2), 292 327 Data_In(2) => Port2_in(2), … … 302 337 GENERIC MAP(number_of_ports => 3) 303 338 PORT MAP( 304 305 Control => Ctrl, 339 reset => reset, 340 clk =>clk, 341 342 Control => Ctrl_buf, 306 343 Data_In(1) => Port1_in(3), 307 344 Data_In(2) => Port2_in(3), … … 318 355 PORT MAP( 319 356 320 Control => Ctrl, 357 reset => reset, 358 clk=>clk, 359 Control => Ctrl_buf, 321 360 Data_In(1) => Port1_in(4), 322 361 Data_In(2) => Port2_in(4), … … 333 372 PORT MAP( 334 373 335 Control => Ctrl, 374 reset => reset, 375 clk=>clk, 376 Control => Ctrl_buf, 336 377 Data_In(1) => Port1_in(5), 337 378 Data_In(2) => Port2_in(5), … … 348 389 PORT MAP( 349 390 350 Control => Ctrl, 391 reset => reset, 392 clk =>clk, 393 394 Control => Ctrl_buf, 351 395 Data_In(1) => Port1_in(6), 352 396 Data_In(2) => Port2_in(6), … … 362 406 GENERIC MAP(number_of_ports => 3) 363 407 PORT MAP( 364 365 Control => Ctrl, 408 reset => reset, 409 clk =>clk, 410 411 Control => Ctrl_buf, 366 412 Data_In(1) => Port1_in(7), 367 413 Data_In(2) => Port2_in(7), … … 377 423 GENERIC MAP(number_of_ports => 3) 378 424 PORT MAP( 379 380 Control => Ctrl, 425 reset => reset, 426 clk =>clk, 427 428 Control => Ctrl_buf, 381 429 Data_In(1) => Port1_pulse_in, 382 430 Data_In(2) => Port2_pulse_in, … … 400 448 PORT MAP( 401 449 402 Control => Ctrl, 450 reset => reset, 451 clk=>clk, 452 Control => Ctrl_buf, 403 453 Data_In(1) => Port1_in(0), 404 454 Data_In(2) => Port2_in(0), … … 417 467 PORT MAP( 418 468 419 Control => Ctrl, 469 reset => reset, 470 clk=>clk, 471 Control => Ctrl_buf, 420 472 Data_In(1) => Port1_in(1), 421 473 Data_In(2) => Port2_in(1), … … 434 486 PORT MAP( 435 487 436 Control => Ctrl, 488 reset => reset, 489 clk=>clk, 490 Control => Ctrl_buf, 437 491 Data_In(1) => Port1_in(2), 438 492 Data_In(2) => Port2_in(2), … … 451 505 PORT MAP( 452 506 453 Control => Ctrl, 507 reset => reset, 508 clk=>clk, 509 Control => Ctrl_buf, 454 510 Data_In(1) => Port1_in(3), 455 511 Data_In(2) => Port2_in(3), … … 468 524 PORT MAP( 469 525 470 Control => Ctrl, 526 reset => reset, 527 clk=>clk, 528 Control => Ctrl_buf, 471 529 Data_In(1) => Port1_in(4), 472 530 Data_In(2) => Port2_in(4), … … 485 543 PORT MAP( 486 544 487 Control => Ctrl, 545 reset => reset, 546 clk=>clk, 547 Control => Ctrl_buf, 488 548 Data_In(1) => Port1_in(5), 489 549 Data_In(2) => Port2_in(5), … … 502 562 PORT MAP( 503 563 504 Control => Ctrl, 564 reset => reset, 565 clk=>clk, 566 Control => Ctrl_buf, 505 567 Data_In(1) => Port1_in(6), 506 568 Data_In(2) => Port2_in(6), … … 519 581 PORT MAP( 520 582 521 Control => Ctrl, 583 reset => reset, 584 clk=>clk, 585 Control => Ctrl_buf, 522 586 Data_In(1) => Port1_in(7), 523 587 Data_In(2) => Port2_in(7), … … 536 600 PORT MAP( 537 601 538 Control => Ctrl, 602 reset => reset, 603 clk=>clk, 604 Control => Ctrl_buf, 539 605 Data_In(1) => Port1_pulse_in, 540 606 Data_In(2) => Port2_pulse_in, … … 560 626 PORT MAP( 561 627 562 Control => Ctrl, 628 reset => reset, 629 clk=>clk, 630 Control => Ctrl_buf, 563 631 Data_In(1) => Port1_in(0), 564 632 Data_In(2) => Port2_in(0), … … 579 647 PORT MAP( 580 648 581 Control => Ctrl, 649 reset => reset, 650 clk=>clk, 651 Control => Ctrl_buf, 582 652 Data_In(1) => Port1_in(1), 583 653 Data_In(2) => Port2_in(1), … … 598 668 PORT MAP( 599 669 600 Control => Ctrl, 670 reset => reset, 671 clk=>clk, 672 Control => Ctrl_buf, 601 673 Data_In(1) => Port1_in(2), 602 674 Data_In(2) => Port2_in(2), … … 617 689 PORT MAP( 618 690 619 Control => Ctrl, 691 reset => reset, 692 clk=>clk, 693 Control => Ctrl_buf, 620 694 Data_In(1) => Port1_in(3), 621 695 Data_In(2) => Port2_in(3), … … 636 710 PORT MAP( 637 711 638 Control => Ctrl, 712 reset => reset, 713 clk=>clk, 714 Control => Ctrl_buf, 639 715 Data_In(1) => Port1_in(4), 640 716 Data_In(2) => Port2_in(4), … … 655 731 PORT MAP( 656 732 657 Control => Ctrl, 733 reset => reset, 734 clk=>clk, 735 Control => Ctrl_buf, 658 736 Data_In(1) => Port1_in(5), 659 737 Data_In(2) => Port2_in(5), … … 674 752 PORT MAP( 675 753 676 Control => Ctrl, 754 reset => reset, 755 clk=>clk, 756 Control => Ctrl_buf, 677 757 Data_In(1) => Port1_in(6), 678 758 Data_In(2) => Port2_in(6), … … 693 773 PORT MAP( 694 774 695 Control => Ctrl, 775 reset => reset, 776 clk=>clk, 777 Control => Ctrl_buf, 696 778 Data_In(1) => Port1_in(7), 697 779 Data_In(2) => Port2_in(7), … … 712 794 PORT MAP( 713 795 714 Control => Ctrl, 796 reset => reset, 797 clk=>clk, 798 Control => Ctrl_buf, 715 799 Data_In(1) => Port1_pulse_in, 716 800 Data_In(2) => Port2_pulse_in, … … 738 822 PORT MAP( 739 823 740 Control => Ctrl, 824 reset => reset, 825 clk=>clk, 826 Control => Ctrl_buf, 741 827 Data_In(1) => Port1_in(0), 742 828 Data_In(2) => Port2_in(0), … … 759 845 PORT MAP( 760 846 761 Control => Ctrl, 847 reset => reset, 848 clk=>clk, 849 Control => Ctrl_buf, 762 850 Data_In(1) => Port1_in(1), 763 851 Data_In(2) => Port2_in(1), … … 780 868 PORT MAP( 781 869 782 Control => Ctrl, 870 reset => reset, 871 clk=>clk, 872 Control => Ctrl_buf, 783 873 Data_In(1) => Port1_in(2), 784 874 Data_In(2) => Port2_in(2), … … 801 891 PORT MAP( 802 892 803 Control => Ctrl, 893 reset => reset, 894 clk=>clk, 895 Control => Ctrl_buf, 804 896 Data_In(1) => Port1_in(3), 805 897 Data_In(2) => Port2_in(3), … … 822 914 PORT MAP( 823 915 824 Control => Ctrl, 916 reset => reset, 917 clk=>clk, 918 Control => Ctrl_buf, 825 919 Data_In(1) => Port1_in(4), 826 920 Data_In(2) => Port2_in(4), … … 843 937 PORT MAP( 844 938 845 Control => Ctrl, 939 reset => reset, 940 clk=>clk, 941 Control => Ctrl_buf, 846 942 Data_In(1) => Port1_in(5), 847 943 Data_In(2) => Port2_in(5), … … 864 960 PORT MAP( 865 961 866 Control => Ctrl, 962 reset => reset, 963 clk=>clk, 964 Control => Ctrl_buf, 867 965 Data_In(1) => Port1_in(6), 868 966 Data_In(2) => Port2_in(6), … … 885 983 PORT MAP( 886 984 887 Control => Ctrl, 985 reset => reset, 986 clk=>clk, 987 Control => Ctrl_buf, 888 988 Data_In(1) => Port1_in(7), 889 989 Data_In(2) => Port2_in(7), … … 906 1006 PORT MAP( 907 1007 908 Control => Ctrl, 1008 reset => reset, 1009 clk=>clk, 1010 Control => Ctrl_buf, 909 1011 Data_In(1) => Port1_pulse_in, 910 1012 Data_In(2) => Port2_pulse_in, … … 934 1036 PORT MAP( 935 1037 936 Control => Ctrl, 1038 reset => reset, 1039 clk=>clk, 1040 Control => Ctrl_buf, 937 1041 Data_In(1) => Port1_in(0), 938 1042 Data_In(2) => Port2_in(0), … … 957 1061 PORT MAP( 958 1062 959 Control => Ctrl, 1063 reset => reset, 1064 clk=>clk, 1065 Control => Ctrl_buf, 960 1066 Data_In(1) => Port1_in(1), 961 1067 Data_In(2) => Port2_in(1), … … 980 1086 PORT MAP( 981 1087 982 Control => Ctrl, 1088 reset => reset, 1089 clk=>clk, 1090 Control => Ctrl_buf, 983 1091 Data_In(1) => Port1_in(2), 984 1092 Data_In(2) => Port2_in(2), … … 1003 1111 PORT MAP( 1004 1112 1005 Control => Ctrl, 1113 reset => reset, 1114 clk=>clk, 1115 Control => Ctrl_buf, 1006 1116 Data_In(1) => Port1_in(3), 1007 1117 Data_In(2) => Port2_in(3), … … 1026 1136 PORT MAP( 1027 1137 1028 Control => Ctrl, 1138 reset => reset, 1139 clk=>clk, 1140 Control => Ctrl_buf, 1029 1141 Data_In(1) => Port1_in(4), 1030 1142 Data_In(2) => Port2_in(4), … … 1049 1161 PORT MAP( 1050 1162 1051 Control => Ctrl, 1163 reset => reset, 1164 clk=>clk, 1165 Control => Ctrl_buf, 1052 1166 Data_In(1) => Port1_in(5), 1053 1167 Data_In(2) => Port2_in(5), … … 1072 1186 PORT MAP( 1073 1187 1074 Control => Ctrl, 1188 reset => reset, 1189 clk=>clk, 1190 Control => Ctrl_buf, 1075 1191 Data_In(1) => Port1_in(6), 1076 1192 Data_In(2) => Port2_in(6), … … 1095 1211 PORT MAP( 1096 1212 1097 Control => Ctrl, 1213 reset => reset, 1214 clk=>clk, 1215 Control => Ctrl_buf, 1098 1216 Data_In(1) => Port1_in(7), 1099 1217 Data_In(2) => Port2_in(7), … … 1118 1236 PORT MAP( 1119 1237 1120 Control => Ctrl, 1238 reset => reset, 1239 clk=>clk, 1240 Control => Ctrl_buf, 1121 1241 Data_In(1) => Port1_pulse_in, 1122 1242 Data_In(2) => Port2_pulse_in, … … 1147 1267 GENERIC MAP(number_of_ports => 8) 1148 1268 PORT MAP( 1149 1150 Control => Ctrl, 1269 clk =>clk, 1270 reset =>reset, 1271 1272 Control => Ctrl_buf, 1151 1273 Data_In(1) => Port1_in(0), 1152 1274 Data_In(2) => Port2_in(0), … … 1172 1294 GENERIC MAP(number_of_ports => 8) 1173 1295 PORT MAP( 1174 1175 Control => Ctrl, 1296 clk =>clk, 1297 reset =>reset, 1298 1299 Control => Ctrl_buf, 1176 1300 Data_In(1) => Port1_in(1), 1177 1301 Data_In(2) => Port2_in(1), … … 1197 1321 GENERIC MAP(number_of_ports => 8) 1198 1322 PORT MAP( 1199 1200 Control => Ctrl, 1323 clk =>clk, 1324 reset =>reset, 1325 1326 Control => Ctrl_buf, 1201 1327 Data_In(1) => Port1_in(2), 1202 1328 Data_In(2) => Port2_in(2), … … 1222 1348 GENERIC MAP(number_of_ports => 8) 1223 1349 PORT MAP( 1224 1225 Control => Ctrl, 1350 clk =>clk, 1351 reset =>reset, 1352 1353 Control => Ctrl_buf, 1226 1354 Data_In(1) => Port1_in(3), 1227 1355 Data_In(2) => Port2_in(3), … … 1247 1375 GENERIC MAP(number_of_ports => 8) 1248 1376 PORT MAP( 1249 1250 Control => Ctrl, 1377 clk =>clk, 1378 reset =>reset, 1379 1380 Control => Ctrl_buf, 1251 1381 Data_In(1) => Port1_in(4), 1252 1382 Data_In(2) => Port2_in(4), … … 1272 1402 GENERIC MAP(number_of_ports => 8) 1273 1403 PORT MAP( 1274 1275 Control => Ctrl, 1404 clk =>clk, 1405 reset =>reset, 1406 1407 Control => Ctrl_buf, 1276 1408 Data_In(1) => Port1_in(5), 1277 1409 Data_In(2) => Port2_in(5), … … 1297 1429 GENERIC MAP(number_of_ports => 8) 1298 1430 PORT MAP( 1299 1300 Control => Ctrl, 1431 clk =>clk, 1432 reset =>reset, 1433 1434 Control => Ctrl_buf, 1301 1435 Data_In(1) => Port1_in(6), 1302 1436 Data_In(2) => Port2_in(6), … … 1322 1456 GENERIC MAP(number_of_ports => 8) 1323 1457 PORT MAP( 1324 1325 Control => Ctrl, 1458 clk =>clk, 1459 reset =>reset, 1460 1461 Control => Ctrl_buf, 1326 1462 Data_In(1) => Port1_in(7), 1327 1463 Data_In(2) => Port2_in(7), … … 1347 1483 GENERIC MAP(number_of_ports => 8) 1348 1484 PORT MAP( 1349 1350 Control => Ctrl, 1485 clk =>clk, 1486 reset =>reset, 1487 1488 Control => Ctrl_buf, 1351 1489 Data_In(1) => Port1_pulse_in, 1352 1490 Data_In(2) => Port2_pulse_in, … … 1379 1517 GENERIC MAP(number_of_ports => 9) 1380 1518 PORT MAP( 1381 1382 Control => Ctrl, 1519 clk =>clk, 1520 reset =>reset, 1521 1522 Control => Ctrl_buf, 1383 1523 Data_In(1) => Port1_in(0), 1384 1524 Data_In(2) => Port2_in(0), … … 1406 1546 GENERIC MAP(number_of_ports => 9) 1407 1547 PORT MAP( 1408 1409 Control => Ctrl, 1548 clk =>clk, 1549 reset =>reset, 1550 1551 Control => Ctrl_buf, 1410 1552 Data_In(1) => Port1_in(1), 1411 1553 Data_In(2) => Port2_in(1), … … 1433 1575 GENERIC MAP(number_of_ports => 9) 1434 1576 PORT MAP( 1435 1436 Control => Ctrl, 1577 clk =>clk, 1578 reset =>reset, 1579 1580 Control => Ctrl_buf, 1437 1581 Data_In(1) => Port1_in(2), 1438 1582 Data_In(2) => Port2_in(2), … … 1460 1604 GENERIC MAP(number_of_ports => 9) 1461 1605 PORT MAP( 1462 1463 Control => Ctrl, 1606 clk =>clk, 1607 reset =>reset, 1608 1609 Control => Ctrl_buf, 1464 1610 Data_In(1) => Port1_in(3), 1465 1611 Data_In(2) => Port2_in(3), … … 1487 1633 GENERIC MAP(number_of_ports => 9) 1488 1634 PORT MAP( 1489 1490 Control => Ctrl, 1635 clk =>clk, 1636 reset =>reset, 1637 1638 Control => Ctrl_buf, 1491 1639 Data_In(1) => Port1_in(4), 1492 1640 Data_In(2) => Port2_in(4), … … 1514 1662 GENERIC MAP(number_of_ports => 9) 1515 1663 PORT MAP( 1516 1517 Control => Ctrl, 1664 clk =>clk, 1665 reset =>reset, 1666 1667 Control => Ctrl_buf, 1518 1668 Data_In(1) => Port1_in(5), 1519 1669 Data_In(2) => Port2_in(5), … … 1541 1691 GENERIC MAP(number_of_ports => 9) 1542 1692 PORT MAP( 1543 1544 Control => Ctrl, 1693 clk =>clk, 1694 reset =>reset, 1695 1696 Control => Ctrl_buf, 1545 1697 Data_In(1) => Port1_in(6), 1546 1698 Data_In(2) => Port2_in(6), … … 1568 1720 GENERIC MAP(number_of_ports => 9) 1569 1721 PORT MAP( 1570 1571 Control => Ctrl, 1722 clk =>clk, 1723 reset =>reset, 1724 1725 Control => Ctrl_buf, 1572 1726 Data_In(1) => Port1_in(7), 1573 1727 Data_In(2) => Port2_in(7), … … 1595 1749 GENERIC MAP(number_of_ports => 9) 1596 1750 PORT MAP( 1597 1598 Control => Ctrl, 1751 clk =>clk, 1752 reset =>reset, 1753 1754 Control => Ctrl_buf, 1599 1755 Data_In(1) => Port1_pulse_in, 1600 1756 Data_In(2) => Port2_pulse_in, … … 1630 1786 PORT MAP( 1631 1787 1632 Control => Ctrl, 1788 reset => reset, 1789 clk=>clk, 1790 Control => Ctrl_buf, 1633 1791 Data_In(1) => Port1_in(0), 1634 1792 Data_In(2) => Port2_in(0), … … 1659 1817 PORT MAP( 1660 1818 1661 Control => Ctrl, 1819 reset => reset, 1820 clk=>clk, 1821 Control => Ctrl_buf, 1662 1822 Data_In(1) => Port1_in(1), 1663 1823 Data_In(2) => Port2_in(1), … … 1688 1848 PORT MAP( 1689 1849 1690 Control => Ctrl, 1850 reset => reset, 1851 clk=>clk, 1852 Control => Ctrl_buf, 1691 1853 Data_In(1) => Port1_in(2), 1692 1854 Data_In(2) => Port2_in(2), … … 1717 1879 PORT MAP( 1718 1880 1719 Control => Ctrl, 1881 reset => reset, 1882 clk=>clk, 1883 Control => Ctrl_buf, 1720 1884 Data_In(1) => Port1_in(3), 1721 1885 Data_In(2) => Port2_in(3), … … 1746 1910 PORT MAP( 1747 1911 1748 Control => Ctrl, 1912 reset => reset, 1913 clk=>clk, 1914 Control => Ctrl_buf, 1749 1915 Data_In(1) => Port1_in(4), 1750 1916 Data_In(2) => Port2_in(4), … … 1775 1941 PORT MAP( 1776 1942 1777 Control => Ctrl, 1943 reset => reset, 1944 clk=>clk, 1945 Control => Ctrl_buf, 1778 1946 Data_In(1) => Port1_in(5), 1779 1947 Data_In(2) => Port2_in(5), … … 1804 1972 PORT MAP( 1805 1973 1806 Control => Ctrl, 1974 reset => reset, 1975 clk=>clk, 1976 Control => Ctrl_buf, 1807 1977 Data_In(1) => Port1_in(6), 1808 1978 Data_In(2) => Port2_in(6), … … 1833 2003 PORT MAP( 1834 2004 1835 Control => Ctrl, 2005 reset => reset, 2006 clk=>clk, 2007 Control => Ctrl_buf, 1836 2008 Data_In(1) => Port1_in(7), 1837 2009 Data_In(2) => Port2_in(7), … … 1862 2034 PORT MAP( 1863 2035 1864 Control => Ctrl, 2036 reset => reset, 2037 clk=>clk, 2038 Control => Ctrl_buf, 1865 2039 Data_In(1) => Port1_pulse_in, 1866 2040 Data_In(2) => Port2_pulse_in, … … 1898 2072 PORT MAP( 1899 2073 1900 Control => Ctrl, 2074 reset => reset, 2075 clk=>clk, 2076 Control => Ctrl_buf, 1901 2077 Data_In(1) => Port1_in(0), 1902 2078 Data_In(2) => Port2_in(0), … … 1929 2105 PORT MAP( 1930 2106 1931 Control => Ctrl, 2107 reset => reset, 2108 clk=>clk, 2109 Control => Ctrl_buf, 1932 2110 Data_In(1) => Port1_in(1), 1933 2111 Data_In(2) => Port2_in(1), … … 1960 2138 PORT MAP( 1961 2139 1962 Control => Ctrl, 2140 reset => reset, 2141 clk=>clk, 2142 Control => Ctrl_buf, 1963 2143 Data_In(1) => Port1_in(2), 1964 2144 Data_In(2) => Port2_in(2), … … 1991 2171 PORT MAP( 1992 2172 1993 Control => Ctrl, 2173 reset => reset, 2174 clk=>clk, 2175 2176 Control => Ctrl_buf, 1994 2177 Data_In(1) => Port1_in(3), 1995 2178 Data_In(2) => Port2_in(3), … … 2022 2205 PORT MAP( 2023 2206 2024 Control => Ctrl, 2207 reset => reset, 2208 clk=>clk, 2209 Control => Ctrl_buf, 2025 2210 Data_In(1) => Port1_in(4), 2026 2211 Data_In(2) => Port2_in(4), … … 2053 2238 PORT MAP( 2054 2239 2055 Control => Ctrl, 2240 reset => reset, 2241 clk=>clk, 2242 2243 Control => Ctrl_buf, 2056 2244 Data_In(1) => Port1_in(5), 2057 2245 Data_In(2) => Port2_in(5), … … 2084 2272 PORT MAP( 2085 2273 2086 Control => Ctrl, 2274 reset => reset, 2275 clk=>clk, 2276 2277 Control => Ctrl_buf, 2087 2278 Data_In(1) => Port1_in(6), 2088 2279 Data_In(2) => Port2_in(6), … … 2115 2306 PORT MAP( 2116 2307 2117 Control => Ctrl, 2308 reset => reset, 2309 clk=>clk, 2310 2311 Control => Ctrl_buf, 2118 2312 Data_In(1) => Port1_in(7), 2119 2313 Data_In(2) => Port2_in(7), … … 2146 2340 PORT MAP( 2147 2341 2148 Control => Ctrl, 2342 reset => reset, 2343 clk=>clk, 2344 2345 Control => Ctrl_buf, 2149 2346 Data_In(1) => Port1_pulse_in, 2150 2347 Data_In(2) => Port2_pulse_in, … … 2184 2381 PORT MAP( 2185 2382 2186 Control => Ctrl, 2383 reset => reset, 2384 clk=>clk, 2385 2386 Control => Ctrl_buf, 2187 2387 Data_In(1) => Port1_in(0), 2188 2388 Data_In(2) => Port2_in(0), … … 2217 2417 PORT MAP( 2218 2418 2219 Control => Ctrl, 2419 reset => reset, 2420 clk=>clk, 2421 2422 Control => Ctrl_buf, 2220 2423 Data_In(1) => Port1_in(1), 2221 2424 Data_In(2) => Port2_in(1), … … 2250 2453 PORT MAP( 2251 2454 2252 Control => Ctrl, 2455 reset => reset, 2456 clk=>clk, 2457 2458 Control => Ctrl_buf, 2253 2459 Data_In(1) => Port1_in(2), 2254 2460 Data_In(2) => Port2_in(2), … … 2283 2489 PORT MAP( 2284 2490 2285 Control => Ctrl, 2491 reset => reset, 2492 clk=>clk, 2493 2494 Control => Ctrl_buf, 2286 2495 Data_In(1) => Port1_in(3), 2287 2496 Data_In(2) => Port2_in(3), … … 2316 2525 PORT MAP( 2317 2526 2318 Control => Ctrl, 2527 reset => reset, 2528 clk=>clk, 2529 2530 Control => Ctrl_buf, 2319 2531 Data_In(1) => Port1_in(4), 2320 2532 Data_In(2) => Port2_in(4), … … 2349 2561 PORT MAP( 2350 2562 2351 Control => Ctrl, 2563 reset => reset, 2564 clk=>clk, 2565 2566 Control => Ctrl_buf, 2352 2567 Data_In(1) => Port1_in(5), 2353 2568 Data_In(2) => Port2_in(5), … … 2382 2597 PORT MAP( 2383 2598 2384 Control => Ctrl, 2599 reset => reset, 2600 clk=>clk, 2601 2602 Control => Ctrl_buf, 2385 2603 Data_In(1) => Port1_in(6), 2386 2604 Data_In(2) => Port2_in(6), … … 2415 2633 PORT MAP( 2416 2634 2417 Control => Ctrl, 2635 reset => reset, 2636 clk=>clk, 2637 2638 Control => Ctrl_buf, 2418 2639 Data_In(1) => Port1_in(7), 2419 2640 Data_In(2) => Port2_in(7), … … 2448 2669 PORT MAP( 2449 2670 2450 Control => Ctrl, 2671 reset => reset, 2672 clk=>clk, 2673 2674 Control => Ctrl_buf, 2451 2675 Data_In(1) => Port1_pulse_in, 2452 2676 Data_In(2) => Port2_pulse_in, … … 2488 2712 PORT MAP( 2489 2713 2490 Control => Ctrl, 2714 reset => reset, 2715 clk=>clk, 2716 Control => Ctrl_buf, 2491 2717 Data_In(1) => Port1_in(0), 2492 2718 Data_In(2) => Port2_in(0), … … 2523 2749 PORT MAP( 2524 2750 2525 Control => Ctrl, 2751 reset => reset, 2752 clk=>clk, 2753 2754 Control => Ctrl_buf, 2526 2755 Data_In(1) => Port1_in(1), 2527 2756 Data_In(2) => Port2_in(1), … … 2558 2787 PORT MAP( 2559 2788 2560 Control => Ctrl, 2789 reset => reset, 2790 clk=>clk, 2791 2792 Control => Ctrl_buf, 2561 2793 Data_In(1) => Port1_in(2), 2562 2794 Data_In(2) => Port2_in(2), … … 2593 2825 PORT MAP( 2594 2826 2595 Control => Ctrl, 2827 reset => reset, 2828 clk=>clk, 2829 Control => Ctrl_buf, 2596 2830 Data_In(1) => Port1_in(3), 2597 2831 Data_In(2) => Port2_in(3), … … 2628 2862 PORT MAP( 2629 2863 2630 Control => Ctrl, 2864 reset => reset, 2865 clk=>clk, 2866 Control => Ctrl_buf, 2631 2867 Data_In(1) => Port1_in(4), 2632 2868 Data_In(2) => Port2_in(4), … … 2663 2899 PORT MAP( 2664 2900 2665 Control => Ctrl, 2901 reset => reset, 2902 clk=>clk, 2903 Control => Ctrl_buf, 2666 2904 Data_In(1) => Port1_in(5), 2667 2905 Data_In(2) => Port2_in(5), … … 2698 2936 PORT MAP( 2699 2937 2700 Control => Ctrl, 2938 reset => reset, 2939 clk=>clk, 2940 Control => Ctrl_buf, 2701 2941 Data_In(1) => Port1_in(6), 2702 2942 Data_In(2) => Port2_in(6), … … 2733 2973 PORT MAP( 2734 2974 2735 Control => Ctrl, 2975 reset => reset, 2976 clk=>clk, 2977 Control => Ctrl_buf, 2736 2978 Data_In(1) => Port1_in(7), 2737 2979 Data_In(2) => Port2_in(7), … … 2768 3010 PORT MAP( 2769 3011 2770 Control => Ctrl, 3012 reset => reset, 3013 clk=>clk, 3014 Control => Ctrl_buf, 2771 3015 Data_In(1) => Port1_pulse_in, 2772 3016 Data_In(2) => Port2_pulse_in, … … 2810 3054 PORT MAP( 2811 3055 2812 Control => Ctrl, 3056 reset => reset, 3057 clk=>clk, 3058 Control => Ctrl_buf, 2813 3059 Data_In(1) => Port1_in(0), 2814 3060 Data_In(2) => Port2_in(0), … … 2847 3093 PORT MAP( 2848 3094 2849 Control => Ctrl, 3095 reset => reset, 3096 clk=>clk, 3097 Control => Ctrl_buf, 2850 3098 Data_In(1) => Port1_in(1), 2851 3099 Data_In(2) => Port2_in(1), … … 2884 3132 PORT MAP( 2885 3133 2886 Control => Ctrl, 3134 reset => reset, 3135 clk=>clk, 3136 Control => Ctrl_buf, 2887 3137 Data_In(1) => Port1_in(2), 2888 3138 Data_In(2) => Port2_in(2), … … 2921 3171 PORT MAP( 2922 3172 2923 Control => Ctrl, 3173 reset => reset, 3174 clk=>clk, 3175 Control => Ctrl_buf, 2924 3176 Data_In(1) => Port1_in(3), 2925 3177 Data_In(2) => Port2_in(3), … … 2958 3210 PORT MAP( 2959 3211 2960 Control => Ctrl, 3212 reset => reset, 3213 clk=>clk, 3214 Control => Ctrl_buf, 2961 3215 Data_In(1) => Port1_in(4), 2962 3216 Data_In(2) => Port2_in(4), … … 2995 3249 PORT MAP( 2996 3250 2997 Control => Ctrl, 3251 reset => reset, 3252 clk=>clk, 3253 Control => Ctrl_buf, 2998 3254 Data_In(1) => Port1_in(5), 2999 3255 Data_In(2) => Port2_in(5), … … 3032 3288 PORT MAP( 3033 3289 3034 Control => Ctrl, 3290 reset => reset, 3291 clk=>clk, 3292 Control => Ctrl_buf, 3035 3293 Data_In(1) => Port1_in(6), 3036 3294 Data_In(2) => Port2_in(6), … … 3069 3327 PORT MAP( 3070 3328 3071 Control => Ctrl, 3329 reset => reset, 3330 clk=>clk, 3331 Control => Ctrl_buf, 3072 3332 Data_In(1) => Port1_in(7), 3073 3333 Data_In(2) => Port2_in(7), … … 3106 3366 PORT MAP( 3107 3367 3108 Control => Ctrl, 3368 reset => reset, 3369 clk=>clk, 3370 Control => Ctrl_buf, 3109 3371 Data_In(1) => Port1_pulse_in, 3110 3372 Data_In(2) => Port2_pulse_in, … … 3150 3412 PORT MAP( 3151 3413 3152 Control => Ctrl, 3414 reset => reset, 3415 clk=>clk, 3416 Control => Ctrl_buf, 3153 3417 Data_In(1) => Port1_in(0), 3154 3418 Data_In(2) => Port2_in(0), … … 3189 3453 PORT MAP( 3190 3454 3191 Control => Ctrl, 3455 reset => reset, 3456 clk=>clk, 3457 Control => Ctrl_buf, 3192 3458 Data_In(1) => Port1_in(1), 3193 3459 Data_In(2) => Port2_in(1), … … 3228 3494 PORT MAP( 3229 3495 3230 Control => Ctrl, 3496 reset => reset, 3497 clk=>clk, 3498 Control => Ctrl_buf, 3231 3499 Data_In(1) => Port1_in(2), 3232 3500 Data_In(2) => Port2_in(2), … … 3267 3535 PORT MAP( 3268 3536 3269 Control => Ctrl, 3537 reset => reset, 3538 clk=>clk, 3539 Control => Ctrl_buf, 3270 3540 Data_In(1) => Port1_in(3), 3271 3541 Data_In(2) => Port2_in(3), … … 3306 3576 PORT MAP( 3307 3577 3308 Control => Ctrl, 3578 reset => reset, 3579 clk=>clk, 3580 Control => Ctrl_buf, 3309 3581 Data_In(1) => Port1_in(4), 3310 3582 Data_In(2) => Port2_in(4), … … 3345 3617 PORT MAP( 3346 3618 3347 Control => Ctrl, 3619 reset => reset, 3620 clk=>clk, 3621 Control => Ctrl_buf, 3348 3622 Data_In(1) => Port1_in(5), 3349 3623 Data_In(2) => Port2_in(5), … … 3384 3658 PORT MAP( 3385 3659 3386 Control => Ctrl, 3660 reset => reset, 3661 clk=>clk, 3662 Control => Ctrl_buf, 3387 3663 Data_In(1) => Port1_in(6), 3388 3664 Data_In(2) => Port2_in(6), … … 3423 3699 PORT MAP( 3424 3700 3425 Control => Ctrl, 3701 reset => reset, 3702 clk=>clk, 3703 Control => Ctrl_buf, 3426 3704 Data_In(1) => Port1_in(7), 3427 3705 Data_In(2) => Port2_in(7), … … 3462 3740 PORT MAP( 3463 3741 3464 Control => Ctrl, 3742 reset => reset, 3743 clk=>clk, 3744 Control => Ctrl_buf, 3465 3745 Data_In(1) => Port1_pulse_in, 3466 3746 Data_In(2) => Port2_pulse_in, … … 3508 3788 PORT MAP( 3509 3789 3510 Control => Ctrl, 3790 reset => reset, 3791 clk=>clk, 3792 Control => Ctrl_buf, 3511 3793 Data_In(1) => Port1_in(0), 3512 3794 Data_In(2) => Port2_in(0), … … 3549 3831 PORT MAP( 3550 3832 3551 Control => Ctrl, 3833 reset => reset, 3834 clk=>clk, 3835 Control => Ctrl_buf, 3552 3836 Data_In(1) => Port1_in(1), 3553 3837 Data_In(2) => Port2_in(1), … … 3590 3874 PORT MAP( 3591 3875 3592 Control => Ctrl, 3876 reset => reset, 3877 clk=>clk, 3878 Control => Ctrl_buf, 3593 3879 Data_In(1) => Port1_in(2), 3594 3880 Data_In(2) => Port2_in(2), … … 3631 3917 PORT MAP( 3632 3918 3633 Control => Ctrl, 3919 reset => reset, 3920 clk=>clk, 3921 Control => Ctrl_buf, 3634 3922 Data_In(1) => Port1_in(3), 3635 3923 Data_In(2) => Port2_in(3), … … 3672 3960 PORT MAP( 3673 3961 3674 Control => Ctrl, 3962 reset => reset, 3963 clk=>clk, 3964 Control => Ctrl_buf, 3675 3965 Data_In(1) => Port1_in(4), 3676 3966 Data_In(2) => Port2_in(4), … … 3713 4003 PORT MAP( 3714 4004 3715 Control => Ctrl, 4005 reset => reset, 4006 clk=>clk, 4007 Control => Ctrl_buf, 3716 4008 Data_In(1) => Port1_in(5), 3717 4009 Data_In(2) => Port2_in(5), … … 3754 4046 PORT MAP( 3755 4047 3756 Control => Ctrl, 4048 reset => reset, 4049 clk=>clk, 4050 Control => Ctrl_buf, 3757 4051 Data_In(1) => Port1_in(6), 3758 4052 Data_In(2) => Port2_in(6), … … 3795 4089 PORT MAP( 3796 4090 3797 Control => Ctrl, 4091 reset => reset, 4092 clk=>clk, 4093 Control => Ctrl_buf, 3798 4094 Data_In(1) => Port1_in(7), 3799 4095 Data_In(2) => Port2_in(7), … … 3836 4132 PORT MAP( 3837 4133 3838 Control => Ctrl, 4134 reset => reset, 4135 clk=>clk, 4136 Control => Ctrl_buf, 3839 4137 Data_In(1) => Port1_pulse_in, 3840 4138 Data_In(2) => Port2_pulse_in, -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbit.vhd
r22 r65 1 1 ---------------------------------------------------------------------------------- 2 2 -- Company: 3 -- Engineer: Kiegaing Emmanuel GEL EN 53 -- Engineer: Kiegaing Emmanuel /GAMOM Roland Christian 4 4 -- 5 5 -- Create Date: 01:47 05/06/2011 … … 14 14 -- Dependencies: 15 15 -- 16 -- Revision: 16 -- Revision: 11-01-2013 17 -- AJOUT DU CLK pour créer un pipeline dans l'architecture. 17 18 -- Revision 0.01 - File Created 18 19 -- Additional Comments: … … 34 35 number_of_ports: positive := 4 35 36 ); 36 Port ( Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 37 Port ( clk,reset : in std_logic; 38 Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); 37 39 Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1); 38 40 Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1) 41 39 42 ); 40 43 end Crossbit; 41 44 42 45 architecture Behavioral of Crossbit is 43 46 signal dout :STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); 44 47 begin 45 48 -- element de commutation utilisee dans la matrice interconnecte … … 49 52 crossbit2x2 : if number_of_ports = 2 generate 50 53 51 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3)));52 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4)));54 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3))); 55 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4))); 53 56 end generate crossbit2x2; 54 57 … … 59 62 60 63 61 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7)));62 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8)));63 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9)));64 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7))); 65 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8))); 66 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9))); 64 67 end generate crossbit3x3; 65 68 … … 69 72 crossbit4x4 : if number_of_ports = 4 generate 70 73 71 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13)));72 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14)));73 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15)));74 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16)));74 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13))); 75 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14))); 76 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15))); 77 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16))); 75 78 end generate crossbit4x4; 76 79 … … 80 83 crossbit5x5 : if number_of_ports = 5 generate 81 84 82 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21)));83 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22)));84 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23)));85 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24)));86 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25)));85 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21))); 86 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22))); 87 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23))); 88 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24))); 89 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25))); 87 90 end generate crossbit5x5; 88 91 … … 92 95 crossbit6x6 : if number_of_ports = 6 generate 93 96 94 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31)));95 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32)));96 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33)));97 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34)));98 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35)));99 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36)));97 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31))); 98 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32))); 99 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33))); 100 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34))); 101 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35))); 102 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36))); 100 103 end generate crossbit6x6; 101 104 … … 105 108 crossbit7x7 : if number_of_ports = 7 generate 106 109 107 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43)));108 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44)));109 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45)));110 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46)));111 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47)));112 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48)));113 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49)));110 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43))); 111 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44))); 112 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45))); 113 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46))); 114 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47))); 115 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48))); 116 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49))); 114 117 end generate crossbit7x7; 115 118 … … 119 122 crossbit8x8 : if number_of_ports = 8 generate 120 123 121 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57)));122 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58)));123 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59)));124 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60)));125 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61)));126 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62)));127 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63)));128 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64)));124 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57))); 125 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58))); 126 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59))); 127 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60))); 128 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61))); 129 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62))); 130 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63))); 131 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64))); 129 132 end generate crossbit8x8; 130 133 … … 134 137 crossbit9x9 : if number_of_ports = 9 generate 135 138 136 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73)));137 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74)));138 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75)));139 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76)));140 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77)));141 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78)));142 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79)));143 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80)));144 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81)));139 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73))); 140 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74))); 141 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75))); 142 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76))); 143 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77))); 144 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78))); 145 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79))); 146 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80))); 147 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81))); 145 148 end generate crossbit9x9; 146 149 … … 150 153 crossbit10x10 : if number_of_ports = 10 generate 151 154 152 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91)));153 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92)));154 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93)));155 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94)));156 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95)));157 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96)));158 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97)));159 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98)));160 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99)));161 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100)));155 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91))); 156 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92))); 157 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93))); 158 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94))); 159 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95))); 160 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96))); 161 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97))); 162 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98))); 163 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99))); 164 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100))); 162 165 end generate crossbit10x10; 163 166 … … 167 170 crossbit11x11 : if number_of_ports = 11 generate 168 171 169 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111)));170 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112)));171 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113)));172 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114)));173 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115)));174 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116)));175 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117)));176 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118)));177 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119)));178 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120)));179 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121)));172 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111))); 173 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112))); 174 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113))); 175 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114))); 176 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115))); 177 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116))); 178 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117))); 179 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118))); 180 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119))); 181 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120))); 182 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121))); 180 183 end generate crossbit11x11; 181 184 … … 185 188 crossbit12x12 : if number_of_ports = 12 generate 186 189 187 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133)));188 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134)));189 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135)));190 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136)));191 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137)));192 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138)));193 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139)));194 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140)));195 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141)));196 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142)));197 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143)));198 D ata_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144)));190 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133))); 191 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134))); 192 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135))); 193 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136))); 194 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137))); 195 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138))); 196 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139))); 197 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140))); 198 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141))); 199 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142))); 200 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143))); 201 Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144))); 199 202 end generate crossbit12x12; 200 203 … … 204 207 crossbit13x13 : if number_of_ports = 13 generate 205 208 206 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157)));207 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158)));208 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159)));209 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160)));210 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161)));211 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162)));212 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163)));213 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164)));214 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165)));215 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166)));216 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167)));217 D ata_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168)));218 D ata_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169)));209 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157))); 210 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158))); 211 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159))); 212 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160))); 213 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161))); 214 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162))); 215 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163))); 216 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164))); 217 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165))); 218 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166))); 219 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167))); 220 Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168))); 221 Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169))); 219 222 end generate crossbit13x13; 220 223 … … 224 227 crossbit14x14 : if number_of_ports = 14 generate 225 228 226 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183)));227 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184)));228 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185)));229 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186)));230 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187)));231 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188)));232 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189)));233 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190)));234 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191)));235 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192)));236 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193)));237 D ata_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194)));238 D ata_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195)));239 D ata_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196)));229 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183))); 230 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184))); 231 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185))); 232 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186))); 233 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187))); 234 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188))); 235 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189))); 236 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190))); 237 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191))); 238 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192))); 239 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193))); 240 Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194))); 241 Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195))); 242 Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196))); 240 243 end generate crossbit14x14; 241 244 … … 245 248 crossbit15x15 : if number_of_ports = 15 generate 246 249 247 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211)));248 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212)));249 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213)));250 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214)));251 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215)));252 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216)));253 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217)));254 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218)));255 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219)));256 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220)));257 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221)));258 D ata_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222)));259 D ata_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223)));260 D ata_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224)));261 D ata_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225)));250 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211))); 251 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212))); 252 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213))); 253 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214))); 254 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215))); 255 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216))); 256 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217))); 257 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218))); 258 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219))); 259 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220))); 260 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221))); 261 Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222))); 262 Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223))); 263 Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224))); 264 Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225))); 262 265 end generate crossbit15x15; 263 266 … … 267 270 crossbit16x16 : if number_of_ports = 16 generate 268 271 269 D ata_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241)));270 D ata_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242)));271 D ata_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243)));272 D ata_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244)));273 D ata_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245)));274 D ata_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246)));275 D ata_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247)));276 D ata_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248)));277 D ata_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249)));278 D ata_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250)));279 D ata_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251)));280 D ata_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252)));281 D ata_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253)));282 D ata_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254)));283 D ata_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255)));284 D ata_out(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256)));272 Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241))); 273 Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242))); 274 Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243))); 275 Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244))); 276 Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245))); 277 Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246))); 278 Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247))); 279 Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248))); 280 Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249))); 281 Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250))); 282 Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251))); 283 Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252))); 284 Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253))); 285 Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254))); 286 Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255))); 287 Dout(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256))); 285 288 end generate crossbit16x16; 286 289 --pcrossbit:process (clk,reset) 290 --begin 291 --if rising_edge(clk) then 292 -- if reset='1' then 293 -- data_out<= (others=>'0'); 294 -- else 295 data_out<=dout; 296 -- end if; 297 --end if; 298 --end process pcrossbit; 287 299 end Behavioral; 288 300 -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_256_FWFT.vhd
r22 r65 83 83 84 84 -- ram instantiation de la bloc ram 256 octets du FIFO 85 fifo_RAM_256: RAM_256 PORT MAP( 86 clka => clk_signal, 87 clkb => clk_signal, 88 wea => wr_en_signal, 89 ena => '1', 90 enb => '1', 91 addra => push_address_counter, 92 addrb => pop_address_counter, 93 dia => din, 94 dob => doa_signal 95 ); 85 --fifo_RAM_256: RAM_256 PORT MAP( 86 -- clka => clk_signal, 87 -- clkb => clk_signal, 88 -- wea => wr_en_signal, 89 -- ena => '1', 90 -- enb => '1', 91 -- addra => push_address_counter, 92 -- addrb => pop_address_counter, 93 -- dia => din, 94 -- dob => dob_signal 95 -- --dob => doa_signal 96 -- ); 96 97 97 98 -- circuiterie des signaux de validation et d'etat du fifo … … 102 103 --empty_signal <= '1' when fifo_counter = "000000" else 103 104 -- '0'; 104 empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0else105 empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0') else 105 106 '0'; 106 107 clk_signal <= clk; … … 143 144 end if; 144 145 145 when others => fwft_fsm_state <= state0;146 -- when others => fwft_fsm_state <= state0; 146 147 147 148 -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/INPUT_PORT_MODULE.vhd
r22 r65 44 44 Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); 45 45 data_in_en : in STD_LOGIC; -- signaler la présence des données en entrée 46 cmd_in_en : STD_LOGIC; --permet d'identifier les données qui sont dans le tampon46 cmd_in_en :in STD_LOGIC; --permet d'identifier les données qui sont dans le tampon 47 47 reset : in STD_LOGIC; 48 48 clk : in STD_LOGIC; … … 73 73 74 74 --definition du type etat pour les fsm 75 type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse, state3);-- definition du type etat pour le codage des etats des fsm75 type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm 76 76 type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd); 77 77 signal pop_state : fsm_states; … … 79 79 signal cmd_exec : std_logic:='0'; --indique que le port est en train d'exécuter une commande 80 80 signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données 81 signal readOk : std_logic:='0'; --indique s'il est possible de lire les données 81 signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution 82 signal readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données 82 83 -- signaux utilisés dans les fsm 83 signal request_decoder : STD_LOGIC_VECTOR(number_of_ports downto 1);84 signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports downto 1); 84 85 signal request_decoder_en : std_logic; 85 signal request_latch : STD_LOGIC_VECTOR(4 downto 1) ; -- pourquoi pas 3 downto 0 ?86 signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0'); -- pourquoi pas 3 downto 0 ? 86 87 signal request_latch_en : std_logic; 87 88 signal pipeline_latch : std_logic_vector(Word-1 downto 0); … … 131 132 132 133 data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal; 133 fifo_empty <= fifo_empty_signal;134 fifo_empty <= empty_latch; 134 135 reset_signal <= reset; 135 136 grant_proc:process(clk) 136 137 begin 137 138 if rising_edge(clk) then 138 if unsigned(grant)> 0 then 139 -- if unsigned(grant)> 0 then 140 if unsigned(req_grant) > 0 then 139 141 port_granted <= '1'; --il faut veiller à ce que ce port soit vraiment autorisé 140 142 else … … 145 147 rd_en_signal <= not(empty_latch) ; 146 148 request <= request_decoder; 149 reg_grant:process (request_decoder,grant) 150 begin 151 req_grant<=request_decoder and grant; 152 end process reg_grant; 147 153 request_word <= request_latch & request_decoder_en; 148 154 clk_signal <= clk; … … 499 505 case pop_state is 500 506 when state0 => if cmd_in_en='0' then --il ne faut pas exécuter les deux MAE ... 501 if fifo_empty_signal='0' then -- pile pas vide on doit dépiler507 if empty_latch ='0' then -- pile pas vide on doit dépiler 502 508 pop_state <= WaitGrant; 503 509 end if; … … 505 511 pop_state <= CmdOn; 506 512 end if; 507 when CmdOn => if fifo_empty_signal='1' then513 when CmdOn => if empty_latch='1' and cmd_in_en='0' then 508 514 pop_state <= state0; 515 elsif empty_latch='0' and cmd_in_en='1' then 516 pop_state <= CmdOn; 517 elsif empty_latch='1' and cmd_in_en='1' then 518 pop_state <= state0; 519 else -- empty_latch='0' and cmd_in_en='0' 520 pop_state <= WaitGrant; 509 521 end if; 522 510 523 when WaitGrant => if port_granted = '1' then 511 524 -- … … 536 549 pop_state <= state2; 537 550 ReadOk<='1'; 551 else --rd_en_signal='0' fin prématurée de la lecture 552 ReadOk<='0'; 553 pop_state<=stateErr; 554 data_counter<=(others => '0'); 538 555 end if; 539 556 else … … 549 566 data_counter <= data_counter - 1; 550 567 pop_state <= state0; 551 568 when stateErr => 569 data_counter <= data_counter; 570 pop_state <= stateErr; 552 571 when others => pop_state <= state0; 553 572 end case; … … 557 576 558 577 -- actions associées à chaque etat de la fsm de mealy 559 pop_fsm_action : process(pop_state, fifo_out_signal, fifo_empty_signal, rd_en_signal,readok, port_granted )578 pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted ) 560 579 begin 561 580 -- code fonctionnel … … 568 587 dat_priority_rotation <= '1'; 569 588 dat_exec<='0'; 589 dat_Err<='0'; 570 590 push_dout<=fifo_out_signal; 591 571 592 when CmdOn => dat_request_latch_en <= '0'; 572 dat_pipeline_latch_en <= rd_en_signal;593 dat_pipeline_latch_en <= '0'; 573 594 dat_fifo_read_signal <='0'; 574 595 dat_request_decoder_en <= '0'; … … 576 597 dat_priority_rotation <= '1'; 577 598 dat_exec<='0'; 599 dat_Err<='0'; 578 600 push_dout<=fifo_out_signal; 579 601 when WaitGrant => … … 585 607 dat_priority_rotation <= '0'; 586 608 dat_exec<='1'; 609 dat_Err<='0'; 587 610 push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); 588 611 when ReqPort => 589 612 dat_request_latch_en <='1'; --autoriser l'identification du port de destination 590 dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau591 dat_fifo_read_signal <= Port_granted;613 dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau 614 dat_fifo_read_signal <= '1'; 592 615 dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request 593 616 dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot 594 617 dat_priority_rotation <= '0'; 595 618 dat_exec<='1'; 619 dat_Err<='0'; 596 620 push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); 597 621 … … 600 624 dat_fifo_read_signal <= rd_en_signal and port_granted; 601 625 dat_request_decoder_en <= '1'; 602 dat_data_out_pulse <= '1';626 dat_data_out_pulse <= port_granted; 603 627 dat_priority_rotation <= '0'; 604 628 dat_exec<='1'; 629 dat_Err<='0'; 605 630 push_dout<=fifo_out_signal; 606 631 … … 612 637 dat_priority_rotation <= '0'; 613 638 dat_exec<='1'; 639 dat_Err<='0'; 614 640 push_dout<=fifo_out_signal; 615 641 … … 621 647 dat_priority_rotation <= '0'; 622 648 dat_exec<='1'; 649 dat_Err<='0'; 623 650 push_dout<=fifo_out_signal; 624 651 … … 630 657 dat_data_out_pulse <= '0'; 631 658 dat_exec<='0'; 659 dat_Err<='0'; 632 660 push_dout<=fifo_out_signal; 633 661 when stateErr => dat_request_latch_en <= '0'; 662 dat_pipeline_latch_en <= '0'; 663 dat_priority_rotation <= '1'; -- libérer la priorité 664 dat_fifo_read_signal <= '0'; 665 dat_request_decoder_en <= '0'; --libérer le décodeur 666 dat_data_out_pulse <= '0'; 667 dat_exec<='1'; 668 dat_Err<='1'; 669 push_dout<=fifo_out_signal; 634 670 when others => dat_request_latch_en <= '0'; 635 671 dat_pipeline_latch_en <= '0'; … … 639 675 dat_data_out_pulse <= '0'; 640 676 dat_exec<='0'; 677 dat_Err<='0'; 641 678 push_dout<=fifo_out_signal; 642 679 … … 655 692 656 693 when cmdstart => 657 if cmd_in_en='1' and dat_exec='0' and fifo_empty_signal='0' then658 cmdstate<=cmd wait;694 if cmd_in_en='1' and dat_exec='0' and empty_latch='0' then 695 cmdstate<=cmdread; 659 696 end if; 660 when cmdwait => if fifo_empty_signal='0' and port_granted ='1' then 697 cmdReadOk<='0'; 698 when cmdwait => if port_granted='1' then -- demande du port de sortie 661 699 662 cmdstate<=cmdread; 700 cmdstate<=cmdsetdest; 701 elsif cmd_in_en='1' then 702 cmdstate<=cmdwait; 663 703 else 664 704 cmdstate<=cmdstart; 665 705 end if; 706 cmdReadOk<='0'; 666 707 when cmdread => 667 if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas708 -- if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas 668 709 cmdcode:= to_integer(unsigned(fifo_out_signal)); 669 710 if cmdcode=1 then --code de getportid 670 cmdstate<=cmdsetdest; 711 cmdstate<=cmdwait; 712 cmdReadOk<='1'; 671 713 else 672 if port_granted='1' then 673 cmdstate<=cmdend; 674 end if; 714 --ne pas prendre le code inconnu en compte 715 cmdstate<=cmdend; -- la commande n'a pas été reconnu 716 717 cmdReadOk<='0'; 675 718 end if; 676 end if;719 -- end if; 677 720 when cmdsetdest => 678 721 if port_granted='1' then 679 722 cmdstate<=cmdsetcount; 680 723 end if; 724 cmdReadOk<='0'; 681 725 when cmdsetcount => 682 726 if port_granted='1' then 683 727 cmdstate<=cmdsetID; 728 else 729 cmdstate<=cmdsetdest; 684 730 end if; 731 cmdReadOk<='0'; 685 732 when cmdsetID=> 686 733 if port_granted='1' then 687 734 cmdstate <=cmdpulse; 688 735 end if; 736 cmdReadOk<='0'; 689 737 when cmdpulse => 690 738 if port_granted='1' then 691 739 cmdstate <=cmdEnd; 692 740 end if; 741 cmdReadOk<='0'; 693 742 when cmdend => 694 743 if cmd_in_en='0' then --éviter l'exécution en boucle 695 744 cmdstate<=cmdstart; 696 697 745 end if; 746 cmdReadOk<='0'; 698 747 699 748 end case; … … 715 764 cmd_data_signal<=(others=>'0'); 716 765 cmd_data_out_pulse <= '0'; 717 when cmdwait => 766 767 when cmdread => 768 cmd_exec<='1'; 769 cmd_pipeline_latch_en <= '0'; 770 cmd_fifo_read_signal <= '1'; -- vider le tampon d'entrée 771 cmd_request_latch_en<='1'; --mémoriser l'adresse de destination 772 cmd_request_decoder_en <= '1'; --demande d'émission 773 cmd_data_out_pulse <= '0'; 774 cmd_priority_rotation <= '1'; --sans priorité 775 cmd_data_signal<=Port_ID; 776 when cmdwait => 718 777 cmd_exec<='1'; 719 778 cmd_pipeline_latch_en <='0'; 720 779 cmd_fifo_read_signal <= '0'; 721 cmd_priority_rotation <= '1'; --sans priorité 722 cmd_request_latch_en<='0'; 723 cmd_request_decoder_en <= not(fifo_empty_signal); --demande d'émission 724 cmd_data_signal<=(others=>'0'); 725 cmd_data_out_pulse <= '0'; 726 when cmdread => 727 cmd_exec<='1'; 728 cmd_pipeline_latch_en <= '1'; 729 cmd_fifo_read_signal <= '0'; 730 cmd_request_latch_en<='1'; --mémoriser l'adresse de destination 731 cmd_request_decoder_en <= '1'; --demande d'émission 732 cmd_data_out_pulse <= '0'; 733 cmd_priority_rotation <= '0'; --avec priorité 734 --cmd_data_signal<=(others=>'0'); 735 cmd_data_signal<=Port_ID; 780 cmd_request_latch_en<='1'; 781 cmd_priority_rotation <= '0'; --avec priorité 782 cmd_request_decoder_en <= '1'; --demande d'émission 783 cmd_data_signal<=Port_ID; 784 cmd_data_out_pulse <= '0'; 736 785 when cmdsetdest => 737 786 --cmd_request_decoder_en <= '1'; 738 787 cmd_exec<='1'; 739 cmd_pipeline_latch_en <='1'; 788 cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée 740 789 cmd_fifo_read_signal <='0'; 741 790 cmd_request_latch_en<='0'; … … 744 793 cmd_priority_rotation <= '0'; 745 794 cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé 746 795 when cmdsetcount => 796 797 cmd_exec<='1'; 798 cmd_pipeline_latch_en <='1'; -- empiler dans le tampon de sortie les données 799 cmd_fifo_read_signal <='0'; 800 cmd_request_latch_en<='0'; --enregistrer l'adresse de destination 801 cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request 802 cmd_data_out_pulse <= port_granted; 803 cmd_priority_rotation <= '0'; 804 cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8)); 747 805 when cmdSetId => 748 806 --cmd_request_decoder_en <= '1'; … … 750 808 cmd_pipeline_latch_en <='1'; 751 809 cmd_fifo_read_signal <='0'; 752 cmd_request_latch_en<='0'; 810 cmd_request_latch_en<='0'; --enregistrer l'adresse de destination 753 811 cmd_request_decoder_en <= '1'; --autoriser le decodeur à activer le dernier bit de request 754 cmd_data_out_pulse <= '1';812 cmd_data_out_pulse <= port_granted; 755 813 cmd_priority_rotation <= '0'; 756 814 cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé 757 815 758 when cmdsetcount =>759 760 cmd_exec<='1';761 cmd_pipeline_latch_en <='1';762 cmd_fifo_read_signal <='1';763 cmd_request_latch_en<='0';764 cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request765 cmd_data_out_pulse <= port_granted;766 cmd_priority_rotation <= '0';767 cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));768 769 816 when cmdpulse => cmd_exec<='1'; 770 817 cmd_pipeline_latch_en <='0'; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Proto_receiv.vhd
r22 r65 81 81 dlen:=to_integer(unsigned(fifo_out)); 82 82 mem(1)<=fifo_out; -- la longueur 83 etrec<=r_data;84 83 84 if dlen>2 then 85 etrec<=r_data; 86 else 87 etrec<=r_end; 88 end if; 85 89 i:=1; 86 90 87 91 when r_data => 88 92 if fifo_empty='0' then 89 if i<dlen- 3then93 if i<dlen-2 then 90 94 i:=i+1; 91 95 mem(i)<=fifo_out; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER12_12.VHD
r22 r65 55 55 signal grant_latch : std_logic_vector(144 downto 1); 56 56 signal priority_rotation_en : std_logic; 57 signal Grant : std_logic_vector(144 downto 1);57 signal Grant,req_grant : std_logic_vector(144 downto 1); 58 58 begin 59 59 60 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 priority_rotation_en <= '1' when unsigned(priority_rotation) = 4095 else '0'; 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 4095 else '0'; 62 63 --latch servant qui memorise le signal grant pendant a transmission 63 64 grant_latch_process : process(clk) … … 66 67 if reset = '1' then 67 68 grant_latch <= (others => '0'); 68 elsif priority_rotation_en = '1'then69 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 69 70 grant_latch <= Grant; 70 71 end if; 71 72 end if; 72 73 end process; 73 port_grant <= Grant andgrant_latch;74 port_grant <= grant_latch; 74 75 Grant(1) <= Signal_grant(1)(1) or Signal_grant(13)(1); -- Grant(1,1) 75 76 Grant(2) <= Signal_grant(2)(2) or Signal_grant(14)(2); -- Grant(1,2) -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER13_13.VHD
r22 r65 55 55 signal grant_latch : std_logic_vector(169 downto 1); 56 56 signal priority_rotation_en : std_logic; 57 signal Grant : std_logic_vector(169 downto 1);57 signal Grant,req_grant : std_logic_vector(169 downto 1); 58 58 begin 59 59 60 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 priority_rotation_en <= '1' when unsigned(priority_rotation) = 8191 else '0'; 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 8191 else '0'; 62 63 --latch servant qui memorise le signal grant pendant a transmission 63 64 grant_latch_process : process(clk) … … 66 67 if reset = '1' then 67 68 grant_latch <= (others => '0'); 68 elsif priority_rotation_en = '1' then69 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 69 70 grant_latch <= Grant; 70 71 end if; 71 72 end if; 72 73 end process; 73 port_grant <= Grant andgrant_latch;74 port_grant <= grant_latch; 74 75 Grant(1) <= Signal_grant(1)(1) or Signal_grant(14)(1); -- Grant(1,1) 75 76 Grant(2) <= Signal_grant(2)(2) or Signal_grant(15)(2); -- Grant(1,2) -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER14_14.VHD
r22 r65 55 55 signal grant_latch : std_logic_vector(196 downto 1); 56 56 signal priority_rotation_en : std_logic; 57 signal Grant : std_logic_vector(196 downto 1);57 signal Grant,req_grant : std_logic_vector(196 downto 1); 58 58 begin 59 59 60 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 priority_rotation_en <= '1' when unsigned(priority_rotation) = 16383 else '0'; 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 16383 else '0'; 62 63 --latch servant qui memorise le signal grant pendant a transmission 63 64 grant_latch_process : process(clk) … … 66 67 if reset = '1' then 67 68 grant_latch <= (others => '0'); 68 elsif priority_rotation_en = '1' then69 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 69 70 grant_latch <= Grant; 70 71 end if; 71 72 end if; 72 73 end process; 73 port_grant <= Grant andgrant_latch;74 port_grant <= grant_latch; 74 75 Grant(1) <= Signal_grant(1)(1) or Signal_grant(15)(1); -- Grant(1,1) 75 76 Grant(2) <= Signal_grant(2)(2) or Signal_grant(16)(2); -- Grant(1,2) -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER15_15.VHD
r22 r65 55 55 signal grant_latch : std_logic_vector(225 downto 1); 56 56 signal priority_rotation_en : std_logic; 57 signal Grant : std_logic_vector(225 downto 1);57 signal Grant ,req_grant: std_logic_vector(225 downto 1); 58 58 begin 59 59 60 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 priority_rotation_en <= '1' when unsigned(priority_rotation) = 32767 else '0'; 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(req_grant)=0 or unsigned(priority_rotation) = 32767 else '0'; 62 63 --latch servant qui memorise le signal grant pendant a transmission 63 64 grant_latch_process : process(clk) … … 66 67 if reset = '1' then 67 68 grant_latch <= (others => '0'); 68 elsif priority_rotation_en = '1' then69 elsif priority_rotation_en = '1'or unsigned(Grant_latch)=0 then 69 70 grant_latch <= Grant; 70 71 end if; 71 72 end if; 72 73 end process; 73 port_grant <= Grant andgrant_latch;74 port_grant <= grant_latch; 74 75 Grant(1) <= Signal_grant(1)(1) or Signal_grant(16)(1); -- Grant(1,1) 75 76 Grant(2) <= Signal_grant(2)(2) or Signal_grant(17)(2); -- Grant(1,2) -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER16_16.VHD
r22 r65 55 55 signal grant_latch : std_logic_vector(256 downto 1); 56 56 signal priority_rotation_en : std_logic; 57 signal Grant : std_logic_vector(256 downto 1);57 signal Grant,req_grant : std_logic_vector(256 downto 1); 58 58 begin 59 59 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 priority_rotation_en <= '1' when unsigned(priority_rotation) = 65535 else '0'; 60 --validation de la rotation de priorité lorsque aucun port n'emet 61 req_grant<=(request and grant_latch); 62 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 65535 else '0'; 62 63 --latch servant qui memorise le signal grant pendant a transmission 63 64 grant_latch_process : process(clk) … … 66 67 if reset = '1' then 67 68 grant_latch <= (others => '0'); 68 elsif priority_rotation_en = '1' then69 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 69 70 grant_latch <= Grant; 70 71 end if; 71 72 end if; 72 73 end process; 73 port_grant <= Grant andgrant_latch;74 port_grant <= grant_latch; 74 75 Grant(1) <= Signal_grant(1)(1) or Signal_grant(17)(1); -- Grant(1,1) 75 76 Grant(2) <= Signal_grant(2)(2) or Signal_grant(18)(2); -- Grant(1,2) -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd
r45 r65 32 32 entity SWITCH_GEN is 33 33 --type portio is array(positive range) of std_logic_vector (7 downto 0); 34 generic(number_of_ports : positive := 4);34 generic(number_of_ports : positive := 8); 35 35 port( 36 36 -- ports d'entree 37 37 Port_in : in typ_portIO(1 to number_of_ports) ; 38 -- Port1_in : in STD_LOGIC_VECTOR (7 downto 0); 39 -- Port2_in : in STD_LOGIC_VECTOR (7 downto 0); 40 -- Port3_in : in STD_LOGIC_VECTOR (7 downto 0); 41 -- Port4_in : in STD_LOGIC_VECTOR (7 downto 0); 42 -- Port5_in : in STD_LOGIC_VECTOR (7 downto 0); 43 -- Port6_in : in STD_LOGIC_VECTOR (7 downto 0); 44 -- Port7_in : in STD_LOGIC_VECTOR (7 downto 0); 45 -- Port8_in : in STD_LOGIC_VECTOR (7 downto 0); 46 -- Port9_in : in STD_LOGIC_VECTOR (7 downto 0); 47 -- Port10_in : in STD_LOGIC_VECTOR (7 downto 0); 48 -- Port11_in : in STD_LOGIC_VECTOR (7 downto 0); 49 -- Port12_in : in STD_LOGIC_VECTOR (7 downto 0); 50 -- Port13_in : in STD_LOGIC_VECTOR (7 downto 0); 51 -- Port14_in : in STD_LOGIC_VECTOR (7 downto 0); 52 -- Port15_in : in STD_LOGIC_VECTOR (7 downto 0); 53 -- Port16_in : in STD_LOGIC_VECTOR (7 downto 0); 38 54 39 55 40 -- port de sortie 56 41 Port_out : out typ_portIO(1 to number_of_ports); 57 -- Port1_out : out STD_LOGIC_VECTOR (7 downto 0); 58 -- Port2_out : out STD_LOGIC_VECTOR (7 downto 0); 59 -- Port3_out : out STD_LOGIC_VECTOR (7 downto 0); 60 -- Port4_out : out STD_LOGIC_VECTOR (7 downto 0); 61 -- Port5_out : out STD_LOGIC_VECTOR (7 downto 0); 62 -- Port6_out : out STD_LOGIC_VECTOR (7 downto 0); 63 -- Port7_out : out STD_LOGIC_VECTOR (7 downto 0); 64 -- Port8_out : out STD_LOGIC_VECTOR (7 downto 0); 65 -- Port9_out : out STD_LOGIC_VECTOR (7 downto 0); 66 -- Port10_out : out STD_LOGIC_VECTOR (7 downto 0); 67 -- Port11_out : out STD_LOGIC_VECTOR (7 downto 0); 68 -- Port12_out : out STD_LOGIC_VECTOR (7 downto 0); 69 -- Port13_out : out STD_LOGIC_VECTOR (7 downto 0); 70 -- Port14_out : out STD_LOGIC_VECTOR (7 downto 0); 71 -- Port15_out : out STD_LOGIC_VECTOR (7 downto 0); 72 -- Port16_out : out STD_LOGIC_VECTOR (7 downto 0); 42 73 43 -- signaux de controle 74 44 data_in_en : in std_logic_vector(number_of_ports downto 1); … … 87 57 88 58 COMPONENT INPUT_PORT_MODULE 89 generic(number_of_ports : positive := 4;59 generic(number_of_ports : positive := 8; 90 60 Port_num: natural); 91 61 Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0); … … 125 95 ); 126 96 Port ( 127 --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports); 128 Port1_in : in STD_LOGIC_VECTOR (7 downto 0); 97 clk : in STD_LOGIC; 98 reset : in STD_LOGIC; 99 Port1_in : in STD_LOGIC_VECTOR (7 downto 0); 129 100 Port2_in : in STD_LOGIC_VECTOR (7 downto 0); 130 101 Port3_in : in STD_LOGIC_VECTOR (7 downto 0); … … 213 184 214 185 --declaration des signaux de connection entre les modules du switch 215 --type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);216 --signal crossbar_port_in_connetion : port_connection_type;217 --signal crossbar_port_out_connetion :port_connection_type;218 --signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);219 --signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);220 --signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);221 --signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);222 --signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);223 --signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);224 --variable i,j : integer;225 186 226 187 Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1); … … 231 192 signal crossbar_in_port : Typ_PortIO(1 to number_of_ports); 232 193 233 --signal crossbar_in_port1 : std_logic_vector(7 downto 0); 234 --signal crossbar_in_port2 : std_logic_vector(7 downto 0); 235 --signal crossbar_in_port3 : std_logic_vector(7 downto 0); 236 --signal crossbar_in_port4 : std_logic_vector(7 downto 0); 237 --signal crossbar_in_port5 : std_logic_vector(7 downto 0); 238 --signal crossbar_in_port6 : std_logic_vector(7 downto 0); 239 --signal crossbar_in_port7 : std_logic_vector(7 downto 0); 240 --signal crossbar_in_port8 : std_logic_vector(7 downto 0); 241 --signal crossbar_in_port9 : std_logic_vector(7 downto 0); 242 --signal crossbar_in_port10 : std_logic_vector(7 downto 0); 243 --signal crossbar_in_port11 : std_logic_vector(7 downto 0); 244 --signal crossbar_in_port12 : std_logic_vector(7 downto 0); 245 --signal crossbar_in_port13 : std_logic_vector(7 downto 0); 246 --signal crossbar_in_port14 : std_logic_vector(7 downto 0); 247 --signal crossbar_in_port15 : std_logic_vector(7 downto 0); 248 --signal crossbar_in_port16 : std_logic_vector(7 downto 0); 194 249 195 250 196 signal crossbar_out_port : Typ_PortIO(1 to number_of_ports); 251 --signal crossbar_out_port1 : std_logic_vector(7 downto 0); 252 --signal crossbar_out_port2 : std_logic_vector(7 downto 0); 253 --signal crossbar_out_port3 : std_logic_vector(7 downto 0); 254 --signal crossbar_out_port4 : std_logic_vector(7 downto 0); 255 --signal crossbar_out_port5 : std_logic_vector(7 downto 0); 256 --signal crossbar_out_port6 : std_logic_vector(7 downto 0); 257 --signal crossbar_out_port7 : std_logic_vector(7 downto 0); 258 --signal crossbar_out_port8 : std_logic_vector(7 downto 0); 259 --signal crossbar_out_port9 : std_logic_vector(7 downto 0); 260 --signal crossbar_out_port10 : std_logic_vector(7 downto 0); 261 --signal crossbar_out_port11 : std_logic_vector(7 downto 0); 262 --signal crossbar_out_port12 : std_logic_vector(7 downto 0); 263 --signal crossbar_out_port13 : std_logic_vector(7 downto 0); 264 --signal crossbar_out_port14 : std_logic_vector(7 downto 0); 265 --signal crossbar_out_port15 : std_logic_vector(7 downto 0); 266 --signal crossbar_out_port16 : std_logic_vector(7 downto 0); 197 267 198 268 199 signal crossbar_in_pulse : std_logic_vector(number_of_ports downto 1); 269 --signal crossbar_in_pulse1 : std_logic; 270 --signal crossbar_in_pulse2 : std_logic; 271 --signal crossbar_in_pulse3 : std_logic; 272 --signal crossbar_in_pulse4 : std_logic; 273 --signal crossbar_in_pulse5 : std_logic; 274 --signal crossbar_in_pulse6 : std_logic; 275 --signal crossbar_in_pulse7 : std_logic; 276 --signal crossbar_in_pulse8 : std_logic; 277 --signal crossbar_in_pulse9 : std_logic; 278 --signal crossbar_in_pulse10 : std_logic; 279 --signal crossbar_in_pulse11 : std_logic; 280 --signal crossbar_in_pulse12 : std_logic; 281 --signal crossbar_in_pulse13 : std_logic; 282 --signal crossbar_in_pulse14 : std_logic; 283 --signal crossbar_in_pulse15 : std_logic; 284 --signal crossbar_in_pulse16 : std_logic; 200 285 201 286 202 signal crossbar_out_pulse : std_logic_vector(number_of_ports downto 1); 287 --signal crossbar_out_pulse1 : std_logic; 288 --signal crossbar_out_pulse2 : std_logic; 289 --signal crossbar_out_pulse3 : std_logic; 290 --signal crossbar_out_pulse4 : std_logic; 291 --signal crossbar_out_pulse5 : std_logic; 292 --signal crossbar_out_pulse6 : std_logic; 293 --signal crossbar_out_pulse7 : std_logic; 294 --signal crossbar_out_pulse8 : std_logic; 295 --signal crossbar_out_pulse9 : std_logic; 296 --signal crossbar_out_pulse10 : std_logic; 297 --signal crossbar_out_pulse11 : std_logic; 298 --signal crossbar_out_pulse12 : std_logic; 299 --signal crossbar_out_pulse13 : std_logic; 300 --signal crossbar_out_pulse14 : std_logic; 301 --signal crossbar_out_pulse15 : std_logic; 302 --signal crossbar_out_pulse16 : std_logic; 203 303 204 304 205 … … 428 329 --j=number_of_ports*(i-1); 429 330 PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 430 GENERIC MAP(number_of_ports => 4,Port_num=>i)331 GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i) 431 332 PORT MAP( 432 333 data_in => Port_in(i), … … 6281 6182 GENERIC MAP(number_of_crossbar_ports =>2) 6282 6183 PORT MAP( 6184 reset => reset, 6185 clk => clk, 6283 6186 Port1_in => crossbar_in_port(1), 6284 6187 Port2_in => crossbar_in_port(2), … … 6327 6230 GENERIC MAP(number_of_crossbar_ports =>3) 6328 6231 PORT MAP( 6329 Port1_in => crossbar_in_port(1), 6232 reset => reset, 6233 clk => clk, 6234 Port1_in => crossbar_in_port(1), 6330 6235 Port2_in => crossbar_in_port(2), 6331 6236 Port3_in => crossbar_in_port(3), … … 6375 6280 GENERIC MAP(number_of_crossbar_ports =>4) 6376 6281 PORT MAP( 6282 reset => reset, 6283 clk => clk, 6377 6284 Port1_in => crossbar_in_port(1), 6378 6285 Port2_in => crossbar_in_port(2), … … 6425 6332 GENERIC MAP(number_of_crossbar_ports =>5) 6426 6333 PORT MAP( 6334 reset => reset, 6335 clk => clk, 6427 6336 Port1_in => crossbar_in_port(1), 6428 6337 Port2_in => crossbar_in_port(2), … … 6477 6386 GENERIC MAP(number_of_crossbar_ports =>6) 6478 6387 PORT MAP( 6388 6389 reset => reset, 6390 clk => clk, 6479 6391 Port1_in => crossbar_in_port(1), 6480 6392 Port2_in => crossbar_in_port(2), … … 6531 6443 GENERIC MAP(number_of_crossbar_ports =>7) 6532 6444 PORT MAP( 6445 reset => reset, 6446 clk => clk, 6533 6447 Port1_in => crossbar_in_port(1), 6534 6448 Port2_in => crossbar_in_port(2), … … 6587 6501 GENERIC MAP(number_of_crossbar_ports =>8) 6588 6502 PORT MAP( 6503 reset => reset, 6504 clk =>clk, 6589 6505 Port1_in => crossbar_in_port(1), 6590 6506 Port2_in => crossbar_in_port(2), … … 6645 6561 GENERIC MAP(number_of_crossbar_ports =>9) 6646 6562 PORT MAP( 6563 reset => reset, 6564 clk => clk, 6647 6565 Port1_in => crossbar_in_port(1), 6648 6566 Port2_in => crossbar_in_port(2), … … 6705 6623 GENERIC MAP(number_of_crossbar_ports =>10) 6706 6624 PORT MAP( 6625 reset => reset, 6626 clk => clk, 6707 6627 Port1_in => crossbar_in_port(1), 6708 6628 Port2_in => crossbar_in_port(2), … … 6767 6687 GENERIC MAP(number_of_crossbar_ports =>11) 6768 6688 PORT MAP( 6689 reset => reset, 6690 clk => clk, 6769 6691 Port1_in => crossbar_in_port(1), 6770 6692 Port2_in => crossbar_in_port(2), … … 6831 6753 GENERIC MAP(number_of_crossbar_ports =>12) 6832 6754 PORT MAP( 6755 reset => reset, 6756 clk => clk, 6833 6757 Port1_in => crossbar_in_port(1), 6834 6758 Port2_in => crossbar_in_port(2), … … 6897 6821 GENERIC MAP(number_of_crossbar_ports =>13) 6898 6822 PORT MAP( 6823 reset => reset, 6824 clk => clk, 6899 6825 Port1_in => crossbar_in_port(1), 6900 6826 Port2_in => crossbar_in_port(2), … … 6965 6891 GENERIC MAP(number_of_crossbar_ports =>14) 6966 6892 PORT MAP( 6893 reset => reset, 6894 clk => clk, 6967 6895 Port1_in => crossbar_in_port(1), 6968 6896 Port2_in => crossbar_in_port(2), … … 7035 6963 GENERIC MAP(number_of_crossbar_ports =>15) 7036 6964 PORT MAP( 6965 reset => reset, 6966 clk => clk, 7037 6967 Port1_in => crossbar_in_port(1), 7038 6968 Port2_in => crossbar_in_port(2), … … 7107 7037 GENERIC MAP(number_of_crossbar_ports =>16) 7108 7038 PORT MAP( 7039 reset => reset, 7040 clk => clk, 7109 7041 Port1_in => crossbar_in_port(1), 7110 7042 Port2_in => crossbar_in_port(2), -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd
r22 r65 42 42 43 43 architecture Behavioral of Scheduler is 44 -- signaux pour le pipeline; 45 signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0'); 46 signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); 47 signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1'); 48 44 49 -- composants du scheduler 45 46 -- composants du scheduler47 48 49 50 COMPONENT Scheduler2_2 50 51 PORT( … … 225 226 Inst_Scheduler2_2 : Scheduler2_2 226 227 PORT MAP( 228 Request => Request_latch, 229 Fifo_full => Fifo_full_latch, 230 clk => clk , 231 reset =>reset, 232 priority_rotation =>priority_rotation_latch, 233 port_grant =>port_grant); 234 end generate scheduler2x2; 235 236 --======================scheduler 3 ports======================= 237 238 scheduler3x3 : if number_of_ports = 3 generate 239 240 Inst_Scheduler3_3 : Scheduler3_3 241 PORT MAP( 242 Request => Request_latch, 243 Fifo_full => Fifo_full_latch, 244 clk => clk , 245 reset =>reset, 246 priority_rotation =>priority_rotation_latch, 247 port_grant =>port_grant); 248 end generate scheduler3x3; 249 250 --======================scheduler 4 ports======================= 251 252 scheduler4x4 : if number_of_ports = 4 generate 253 254 Inst_Scheduler4_4 : Scheduler4_4 255 PORT MAP( 256 Request => Request_latch, 257 Fifo_full => Fifo_full_latch, 258 clk => clk , 259 reset =>reset, 260 priority_rotation =>priority_rotation_latch, 261 port_grant =>port_grant); 262 end generate scheduler4x4; 263 264 --======================scheduler 5 ports======================= 265 266 scheduler5x5 : if number_of_ports = 5 generate 267 268 Inst_Scheduler5_5 : Scheduler5_5 269 PORT MAP( 227 270 Request => Request, 228 271 Fifo_full => Fifo_full, … … 231 274 priority_rotation =>priority_rotation, 232 275 port_grant =>port_grant); 233 end generate scheduler2x2; 234 235 --======================scheduler 3 ports======================= 236 237 scheduler3x3 : if number_of_ports = 3 generate 238 239 Inst_Scheduler3_3 : Scheduler3_3 276 end generate scheduler5x5; 277 278 --======================scheduler 6 ports======================= 279 280 scheduler6x6 : if number_of_ports = 6 generate 281 282 Inst_Scheduler6_6 : Scheduler6_6 283 PORT MAP( 284 Request => Request_latch, 285 Fifo_full => Fifo_full_latch, 286 clk => clk , 287 reset =>reset, 288 priority_rotation =>priority_rotation_latch, 289 port_grant =>port_grant); 290 end generate scheduler6x6; 291 292 --======================scheduler 7 ports======================= 293 294 scheduler7x7 : if number_of_ports = 7 generate 295 296 Inst_Scheduler7_7 : Scheduler7_7 297 PORT MAP( 298 Request => Request_latch, 299 Fifo_full => Fifo_full_latch, 300 clk => clk , 301 reset =>reset, 302 priority_rotation =>priority_rotation_latch, 303 port_grant =>port_grant); 304 end generate scheduler7x7; 305 306 --======================scheduler 8 ports======================= 307 308 scheduler8x8 : if number_of_ports = 8 generate 309 310 Inst_Scheduler8_8 : Scheduler8_8 311 PORT MAP( 312 Request => Request_latch, 313 Fifo_full => Fifo_full_latch, 314 clk => clk , 315 reset =>reset, 316 priority_rotation =>priority_rotation_latch, 317 port_grant =>port_grant); 318 end generate scheduler8x8; 319 320 --======================scheduler 9 ports======================= 321 322 scheduler9x9 : if number_of_ports = 9 generate 323 324 Inst_Scheduler9_9 : Scheduler9_9 325 PORT MAP( 326 Request => Request_latch, 327 Fifo_full => Fifo_full_latch, 328 clk => clk , 329 reset =>reset, 330 priority_rotation =>priority_rotation_latch, 331 port_grant =>port_grant); 332 end generate scheduler9x9; 333 334 --======================scheduler 10 ports======================= 335 336 scheduler10x10 : if number_of_ports = 10 generate 337 338 Inst_Scheduler10_10 : Scheduler10_10 240 339 PORT MAP( 241 340 Request => Request, … … 245 344 priority_rotation =>priority_rotation, 246 345 port_grant =>port_grant); 247 end generate scheduler 3x3;248 249 --======================scheduler 4ports=======================250 251 scheduler 4x4 : if number_of_ports = 4generate252 253 Inst_Scheduler 4_4 : Scheduler4_4346 end generate scheduler10x10; 347 348 --======================scheduler 11 ports======================= 349 350 scheduler11x11 : if number_of_ports = 11 generate 351 352 Inst_Scheduler11_11 : Scheduler11_11 254 353 PORT MAP( 255 354 Request => Request, … … 259 358 priority_rotation =>priority_rotation, 260 359 port_grant =>port_grant); 261 end generate scheduler4x4;262 263 --======================scheduler 5 ports=======================264 265 scheduler5x5 : if number_of_ports = 5 generate266 267 Inst_Scheduler5_5 : Scheduler5_5268 PORT MAP(269 Request => Request,270 Fifo_full => Fifo_full,271 clk => clk ,272 reset =>reset,273 priority_rotation =>priority_rotation,274 port_grant =>port_grant);275 end generate scheduler5x5;276 277 --======================scheduler 6 ports=======================278 279 scheduler6x6 : if number_of_ports = 6 generate280 281 Inst_Scheduler6_6 : Scheduler6_6282 PORT MAP(283 Request => Request,284 Fifo_full => Fifo_full,285 clk => clk ,286 reset =>reset,287 priority_rotation =>priority_rotation,288 port_grant =>port_grant);289 end generate scheduler6x6;290 291 --======================scheduler 7 ports=======================292 293 scheduler7x7 : if number_of_ports = 7 generate294 295 Inst_Scheduler7_7 : Scheduler7_7296 PORT MAP(297 Request => Request,298 Fifo_full => Fifo_full,299 clk => clk ,300 reset =>reset,301 priority_rotation =>priority_rotation,302 port_grant =>port_grant);303 end generate scheduler7x7;304 305 --======================scheduler 8 ports=======================306 307 scheduler8x8 : if number_of_ports = 8 generate308 309 Inst_Scheduler8_8 : Scheduler8_8310 PORT MAP(311 Request => Request,312 Fifo_full => Fifo_full,313 clk => clk ,314 reset =>reset,315 priority_rotation =>priority_rotation,316 port_grant =>port_grant);317 end generate scheduler8x8;318 319 --======================scheduler 9 ports=======================320 321 scheduler9x9 : if number_of_ports = 9 generate322 323 Inst_Scheduler9_9 : Scheduler9_9324 PORT MAP(325 Request => Request,326 Fifo_full => Fifo_full,327 clk => clk ,328 reset =>reset,329 priority_rotation =>priority_rotation,330 port_grant =>port_grant);331 end generate scheduler9x9;332 333 --======================scheduler 10 ports=======================334 335 scheduler10x10 : if number_of_ports = 10 generate336 337 Inst_Scheduler10_10 : Scheduler10_10338 PORT MAP(339 Request => Request,340 Fifo_full => Fifo_full,341 clk => clk ,342 reset =>reset,343 priority_rotation =>priority_rotation,344 port_grant =>port_grant);345 end generate scheduler10x10;346 347 --======================scheduler 11 ports=======================348 349 scheduler11x11 : if number_of_ports = 11 generate350 351 Inst_Scheduler11_11 : Scheduler11_11352 PORT MAP(353 Request => Request,354 Fifo_full => Fifo_full,355 clk => clk ,356 reset =>reset,357 priority_rotation =>priority_rotation,358 port_grant =>port_grant);359 360 end generate scheduler11x11; 360 361 … … 365 366 Inst_Scheduler12_12 : Scheduler12_12 366 367 PORT MAP( 367 Request => Request ,368 Fifo_full => Fifo_full ,369 clk => clk , 370 reset =>reset, 371 priority_rotation =>priority_rotation ,368 Request => Request_latch, 369 Fifo_full => Fifo_full_latch, 370 clk => clk , 371 reset =>reset, 372 priority_rotation =>priority_rotation_latch, 372 373 port_grant =>port_grant); 373 374 end generate scheduler12x12; … … 379 380 Inst_Scheduler13_13 : Scheduler13_13 380 381 PORT MAP( 381 Request => Request ,382 Fifo_full => Fifo_full ,383 clk => clk , 384 reset =>reset, 385 priority_rotation =>priority_rotation ,382 Request => Request_latch, 383 Fifo_full => Fifo_full_latch, 384 clk => clk , 385 reset =>reset, 386 priority_rotation =>priority_rotation_latch, 386 387 port_grant =>port_grant); 387 388 end generate scheduler13x13; … … 393 394 Inst_Scheduler14_14 : Scheduler14_14 394 395 PORT MAP( 395 Request => Request ,396 Fifo_full => Fifo_full ,397 clk => clk , 398 reset =>reset, 399 priority_rotation =>priority_rotation ,396 Request => Request_latch, 397 Fifo_full => Fifo_full_latch, 398 clk => clk , 399 reset =>reset, 400 priority_rotation =>priority_rotation_latch, 400 401 port_grant =>port_grant); 401 402 end generate scheduler14x14; … … 407 408 Inst_Scheduler15_15 : Scheduler15_15 408 409 PORT MAP( 409 Request => Request ,410 Fifo_full => Fifo_full ,411 clk => clk , 412 reset =>reset, 413 priority_rotation =>priority_rotation ,410 Request => Request_latch, 411 Fifo_full => Fifo_full_latch, 412 clk => clk , 413 reset =>reset, 414 priority_rotation =>priority_rotation_latch, 414 415 port_grant =>port_grant); 415 416 end generate scheduler15x15; … … 421 422 Inst_Scheduler16_16 : Scheduler16_16 422 423 PORT MAP( 423 Request => Request ,424 Fifo_full => Fifo_full ,425 clk => clk , 426 reset =>reset, 427 priority_rotation =>priority_rotation ,424 Request => Request_latch, 425 Fifo_full => Fifo_full_latch, 426 clk => clk , 427 reset =>reset, 428 priority_rotation =>priority_rotation_latch, 428 429 port_grant =>port_grant); 429 430 end generate scheduler16x16; 430 431 Sched:process (clk,reset) 432 begin 433 if rising_edge(clk) then 434 if reset='1' then 435 request_latch<=(others=>'0'); 436 Fifo_full_latch<=(others=>'0'); 437 priority_rotation_latch<=(others=>'1'); 438 else 439 request_latch<=request; 440 Fifo_full_latch<=fifo_full; 441 priority_rotation_latch<=priority_rotation; 442 end if; 443 end if; 444 end process sched; 431 445 end Behavioral; 432 446 -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
r22 r65 50 50 signal sfifo_in : std_logic_vector(Word-1 downto 0); 51 51 signal spush : std_logic:='0'; 52 signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); 52 53 begin 53 54 … … 57 58 if reset='1' then 58 59 etsnd<=s_head; 59 60 err<=(others =>'0'); 60 61 else 61 62 if rising_edge(clk) then -- le process s'exécute sur chaque front … … 79 80 i:=i+1; 80 81 dlen:=to_integer(unsigned(mem(i))); 81 spush<='1'; 82 snd_comp<='0'; 83 etsnd<=s_data; 82 if dlen > 2 then 83 spush<='1'; 84 snd_comp<='0'; 85 etsnd<=s_data; 86 else 87 spush<='1'; 88 snd_comp<='1'; 89 etsnd<=s_end; 90 91 end if; 84 92 when s_len2 => 85 93 snd_comp<='0'; … … 87 95 88 96 when s_data => 89 if fifo_full='0' then97 if (fifo_full='0') and (dlen >2) then 90 98 i:=i+1; 91 99 sfifo_in<=mem(i); 92 if i=dlen-2 then 100 if i>=dlen-1 then --les indices 0 et 1 étant réservés 101 --les données sont comptés à partir de 2 93 102 etsnd<=s_end; 94 103 snd_comp<='1';
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