[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[707] | 2 | // File: top.cpp (for tsar_generic_iob platform) |
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[718] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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[966] | 5 | // Date : august 2013 / updated march 2015 |
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[450] | 6 | // This program is released under the GNU public license |
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| 7 | /////////////////////////////////////////////////////////////////////////////// |
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[938] | 8 | // This file define a generic TSAR architecture with an external IO network |
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| 9 | // emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: |
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[450] | 10 | // |
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[472] | 11 | // - BROM : boot ROM |
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| 12 | // - FBUF : Frame Buffer |
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[1053] | 13 | // - MTTY : multi TTY (up to 8 channels) |
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[1050] | 14 | // - MNIC : Network controller (up to 4 channels) |
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[965] | 15 | // - DISK : Block device controler (BDV / HBA / SDC) |
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[707] | 16 | // - IOPI : HWI to SWI translator. |
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[450] | 17 | // |
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[938] | 18 | // This I/0 bus is connected to internal address space through two IOB bridges |
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[966] | 19 | // located in cluster[0][0] and cluster[X_SIZE-1][Y_SIZE-1]. |
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[938] | 20 | // |
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[707] | 21 | // The internal physical address space is 40 bits, and the cluster index |
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| 22 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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[938] | 23 | // Y is encoded on 4 bits, whatever the actual mesh size. |
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[707] | 24 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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[450] | 25 | // |
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[607] | 26 | // It contains 3 networks: |
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| 27 | // |
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[707] | 28 | // 1) the "INT" network supports Read/Write transactions |
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[718] | 29 | // between processors and L2 caches or peripherals. |
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[450] | 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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[718] | 32 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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[472] | 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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[707] | 37 | // 7 external peripheral controllers. |
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[450] | 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[718] | 39 | // |
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| 40 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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[707] | 41 | // external IOPIC component, that must be configured by the OS to route |
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[874] | 42 | // these WTI IRQS to one or several internal XICU components. |
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[1050] | 43 | // - IOPIC HWI[3:0] connected to IRQ_NIC_RX[3:0] |
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| 44 | // - IOPIC HWI[7:4] connected to IRQ_NIC_TX[3:0] |
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| 45 | // - IOPIC HWI[12] connected to IRQ_IOC |
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[1053] | 46 | // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0] |
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| 47 | // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0] |
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[450] | 48 | // |
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[972] | 49 | // Each cluster contains the following component: |
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| 50 | // - From 1 to 8 MIP32 processors |
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| 51 | // - One L2 cache controller |
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| 52 | // - One XICU component, |
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[1051] | 53 | // - One multi channels DMA controler (number of channels is defined by nprocs) |
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[972] | 54 | // The XICU component is mainly used to handle WTI IRQs, as at most |
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[1051] | 55 | // (nprocs + 1) HWI IRQs are connected to XICU in each cluster: |
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[959] | 56 | // - IRQ_IN[0] : MMC |
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[1051] | 57 | // - IRQ_IN[1 to nprocs] : DMA |
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[718] | 58 | // |
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[450] | 59 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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[1050] | 60 | // contain an extra IO bridge component and two DSPIN local-xbar to multiplex |
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| 61 | // the MEMC and IOB access to RAM network. These IOB0 & IOB1 components are |
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[450] | 62 | // connected to the three networks (INT, RAM, IOX). |
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[718] | 63 | // |
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[450] | 64 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[718] | 65 | // local interconnect correponding to the INT network. |
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| 66 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 67 | // local interconnect correponding to the coherence INT network. |
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[450] | 68 | // - It uses two virtual_dspin_router per cluster to implement |
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| 69 | // the INT network (routing both the direct and coherence trafic). |
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| 70 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 71 | // - It uses the vci_cc_vcache_wrapper. |
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| 72 | // - It uses the vci_mem_cache. |
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| 73 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 74 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 75 | // |
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| 76 | // The TsarIobCluster component is defined in files |
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| 77 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 78 | // |
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| 79 | // The main hardware parameters must be defined in the hard_config.h file : |
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[966] | 80 | // - X_WIDTH : number of bits for x cluster coordinate |
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| 81 | // - Y_WIDTH : number of bits for y cluster coordinate |
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| 82 | // - P_WIDTH : number of bits for local processor coordinate |
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[718] | 83 | // - X_SIZE : number of clusters in a row |
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[707] | 84 | // - Y_SIZE : number of clusters in a column |
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[959] | 85 | // - NB_PROCS_MAX : number of processors per cluster (up to 8) |
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| 86 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) |
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[1050] | 87 | // - NB_TXT_CHANNELS : number of TTY channels in I/O network (up to 16) |
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| 88 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 4) |
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[714] | 89 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 90 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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[1050] | 91 | // - ICU_NB_HWI : number of ICU HWIs (>= NB_PROCS_MAX + 1) |
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| 92 | // - ICU_NB_PTI : number of ICU PTIs (>= NB_PROCS_MAX) |
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| 93 | // - ICU_NB_WTI : number of ICU WTIs (>= 4*NB_PROCS_MAX) |
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| 94 | // - ICU_NB_OUT : number of ICU output IRQs (>= 4*NB_PROCS_MAX) |
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[966] | 95 | // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) |
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[718] | 96 | // |
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[966] | 97 | // Some other hardware parameters must be defined in this top.cpp file: |
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[718] | 98 | // - XRAM_LATENCY : external ram latency |
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[450] | 99 | // - MEMC_WAYS : L2 cache number of ways |
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| 100 | // - MEMC_SETS : L2 cache number of sets |
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[718] | 101 | // - L1_IWAYS |
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| 102 | // - L1_ISETS |
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| 103 | // - L1_DWAYS |
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| 104 | // - L1_DSETS |
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[965] | 105 | // - DISK_IMAGE_NAME : file pathname for block device |
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[450] | 106 | // |
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| 107 | // General policy for 40 bits physical address decoding: |
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| 108 | // All physical segments base addresses are multiple of 1 Mbytes |
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[718] | 109 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[450] | 110 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 111 | // the cluster index, and the LADR bits define the local index: |
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[707] | 112 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 113 | // | 4 | 4 | 8 | 24 | |
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[450] | 114 | // |
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| 115 | // General policy for 14 bits SRCID decoding: |
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| 116 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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[707] | 117 | // |X_ID|Y_ID| L_ID | |
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| 118 | // | 4 | 4 | 6 | |
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[1050] | 119 | // |
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| 120 | // The NIC controler has one VCI target port, and one VCI initiator port, |
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| 121 | // but it uses two different LOCAL_SRCID values to distinguish TX and TX |
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| 122 | // transactions, because there is not enough bits in 4 bits TRDID field. |
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[450] | 123 | ///////////////////////////////////////////////////////////////////////// |
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| 124 | |
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| 125 | #include <systemc> |
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| 126 | #include <sys/time.h> |
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| 127 | #include <iostream> |
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| 128 | #include <sstream> |
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| 129 | #include <cstdlib> |
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| 130 | #include <cstdarg> |
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| 131 | #include <stdint.h> |
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| 132 | |
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| 133 | #include "gdbserver.h" |
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| 134 | #include "mapping_table.h" |
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| 135 | |
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| 136 | #include "tsar_iob_cluster.h" |
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| 137 | #include "vci_chbuf_dma.h" |
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[1053] | 138 | #include "vci_tty_tsar.h" |
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[1050] | 139 | #include "vci_master_nic.h" |
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[450] | 140 | #include "vci_simple_rom.h" |
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[965] | 141 | #include "vci_multi_ahci.h" |
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[450] | 142 | #include "vci_block_device_tsar.h" |
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[1002] | 143 | #include "vci_ahci_sdc.h" |
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| 144 | #include "sd_card.h" |
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[450] | 145 | #include "vci_framebuffer.h" |
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| 146 | #include "vci_iox_network.h" |
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[707] | 147 | #include "vci_iopic.h" |
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[450] | 148 | |
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| 149 | #include "alloc_elems.h" |
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| 150 | |
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[972] | 151 | |
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| 152 | ////////////////////////////////////////////////////////////////// |
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[1046] | 153 | // Virtual disk selection => OS selection |
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[972] | 154 | ////////////////////////////////////////////////////////////////// |
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| 155 | |
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[1046] | 156 | #define USE_ALMOS 1 |
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| 157 | #define USE_GIET 0 |
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[450] | 158 | |
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[1046] | 159 | #if ( USE_ALMOS + USE_GIET != 1 ) |
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| 160 | #error "OS UNDEFINED" |
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| 161 | #endif |
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[450] | 162 | |
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[1046] | 163 | #if USE_ALMOS |
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| 164 | #define DISK_IMAGE_NAME "almos_virt_hdd.dmg" |
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| 165 | #endif |
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| 166 | |
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| 167 | #if USE_GIET |
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| 168 | #define DISK_IMAGE_NAME "giet_virt_hdd.dmg" |
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| 169 | #endif |
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[972] | 170 | ////////////////////////////////////////////////////////////////// |
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| 171 | // Parallelisation |
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| 172 | ////////////////////////////////////////////////////////////////// |
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[450] | 173 | |
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[981] | 174 | #if USE_OPENMP |
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[450] | 175 | #include <omp.h> |
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| 176 | #endif |
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| 177 | |
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[972] | 178 | ////////////////////////////////////////////////////////////////// |
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[718] | 179 | // DSPIN parameters |
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[972] | 180 | ////////////////////////////////////////////////////////////////// |
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[450] | 181 | |
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| 182 | #define dspin_int_cmd_width 39 |
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| 183 | #define dspin_int_rsp_width 32 |
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| 184 | |
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| 185 | #define dspin_ram_cmd_width 64 |
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| 186 | #define dspin_ram_rsp_width 64 |
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| 187 | |
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[972] | 188 | ////////////////////////////////////////////////////////////////// |
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[718] | 189 | // VCI fields width for the 3 VCI networks |
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[972] | 190 | ////////////////////////////////////////////////////////////////// |
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[450] | 191 | |
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| 192 | #define vci_cell_width_int 4 |
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| 193 | #define vci_cell_width_ext 8 |
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| 194 | |
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| 195 | #define vci_plen_width 8 |
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| 196 | #define vci_address_width 40 |
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| 197 | #define vci_rerror_width 1 |
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| 198 | #define vci_clen_width 1 |
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| 199 | #define vci_rflag_width 1 |
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| 200 | #define vci_srcid_width 14 |
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| 201 | #define vci_pktid_width 4 |
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| 202 | #define vci_trdid_width 4 |
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| 203 | #define vci_wrplen_width 1 |
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| 204 | |
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| 205 | //////////////////////////////////////////////////////////// |
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[718] | 206 | // Main Hardware Parameters values |
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[450] | 207 | //////////////////////i///////////////////////////////////// |
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| 208 | |
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[802] | 209 | #include "hard_config.h" |
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[450] | 210 | |
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| 211 | //////////////////////////////////////////////////////////// |
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[718] | 212 | // Secondary Hardware Parameters values |
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[450] | 213 | //////////////////////i///////////////////////////////////// |
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| 214 | |
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[607] | 215 | #define XMAX X_SIZE |
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| 216 | #define YMAX Y_SIZE |
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[450] | 217 | |
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| 218 | #define XRAM_LATENCY 0 |
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| 219 | |
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| 220 | #define MEMC_WAYS 16 |
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| 221 | #define MEMC_SETS 256 |
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| 222 | |
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[1050] | 223 | #define MNIC_MAC_4 0x33445566 // 32 LSB bits |
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| 224 | #define MNIC_MAC_2 0X1122 // 16 MSB bits |
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| 225 | |
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[450] | 226 | #define L1_IWAYS 4 |
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| 227 | #define L1_ISETS 64 |
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| 228 | |
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| 229 | #define L1_DWAYS 4 |
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| 230 | #define L1_DSETS 64 |
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| 231 | |
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[938] | 232 | #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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[450] | 233 | |
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| 234 | #define NORTH 0 |
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| 235 | #define SOUTH 1 |
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| 236 | #define EAST 2 |
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| 237 | #define WEST 3 |
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| 238 | |
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[693] | 239 | #define cluster(x,y) ((y) + ((x) << 4)) |
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[450] | 240 | |
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| 241 | //////////////////////////////////////////////////////////// |
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[718] | 242 | // DEBUG Parameters default values |
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[450] | 243 | //////////////////////i///////////////////////////////////// |
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| 244 | |
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[914] | 245 | #define MAX_FROZEN_CYCLES 1000000 |
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[450] | 246 | |
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| 247 | ///////////////////////////////////////////////////////// |
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| 248 | // Physical segments definition |
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| 249 | ///////////////////////////////////////////////////////// |
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| 250 | |
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[734] | 251 | // All physical segments base addresses and sizes are defined |
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| 252 | // in the hard_config.h file. For replicated segments, the |
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| 253 | // base address is incremented by a cluster offset: |
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| 254 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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[450] | 255 | |
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| 256 | //////////////////////////////////////////////////////////////////////// |
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| 257 | // SRCID definition |
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| 258 | //////////////////////////////////////////////////////////////////////// |
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| 259 | // All initiators are in the same indexing space (14 bits). |
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| 260 | // The SRCID is structured in two fields: |
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[1050] | 261 | // - The 8 MSB bits define the cluster index. |
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[764] | 262 | // - The 6 LSB bits define the local index. |
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[718] | 263 | // Two different initiators cannot have the same SRCID, but a given |
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| 264 | // initiator can have two alias SRCIDs: |
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[1051] | 265 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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[450] | 266 | // and each initiator has one single SRCID. |
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[965] | 267 | // - External initiators (disk, cdma) are not replicated, but can be |
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[718] | 268 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 269 | // They have the same local index, but two different cluster indexes. |
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[707] | 270 | // |
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[450] | 271 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[718] | 272 | // and external initiators, they must have different local indexes. |
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[450] | 273 | // Consequence: For a local interconnect, the INI_ID port index |
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| 274 | // is NOT equal to the SRCID local index, and the local interconnect |
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[718] | 275 | // must make a translation: SRCID => INI_ID |
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[450] | 276 | //////////////////////////////////////////////////////////////////////// |
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| 277 | |
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[550] | 278 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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[1051] | 279 | #define MDMA_LOCAL_SRCID 0x8 |
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[550] | 280 | #define IOBX_LOCAL_SRCID 0x9 |
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| 281 | #define MEMC_LOCAL_SRCID 0xA |
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[965] | 282 | #define DISK_LOCAL_SRCID 0xC |
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[707] | 283 | #define IOPI_LOCAL_SRCID 0xD |
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[1050] | 284 | #define MNRX_LOCAL_SRCID 0xE // NIC_RX transactions |
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| 285 | #define MNTX_LOCAL_SRCID 0xF // NIC_TX transactions |
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[450] | 286 | |
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[550] | 287 | /////////////////////////////////////////////////////////////////////// |
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[450] | 288 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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[550] | 289 | /////////////////////////////////////////////////////////////////////// |
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[450] | 290 | |
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| 291 | #define INT_MEMC_TGT_ID 0 |
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| 292 | #define INT_XICU_TGT_ID 1 |
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[1051] | 293 | #define INT_MDMA_TGT_ID 2 |
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[450] | 294 | #define INT_IOBX_TGT_ID 3 |
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| 295 | |
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| 296 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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[1051] | 297 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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[450] | 298 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 299 | |
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[550] | 300 | /////////////////////////////////////////////////////////////////////// |
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[450] | 301 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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[550] | 302 | /////////////////////////////////////////////////////////////////////// |
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[450] | 303 | |
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| 304 | #define RAM_XRAM_TGT_ID 0 |
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| 305 | |
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| 306 | #define RAM_MEMC_INI_ID 0 |
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| 307 | #define RAM_IOBX_INI_ID 1 |
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| 308 | |
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[550] | 309 | /////////////////////////////////////////////////////////////////////// |
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[450] | 310 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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[550] | 311 | /////////////////////////////////////////////////////////////////////// |
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[450] | 312 | |
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[718] | 313 | #define IOX_FBUF_TGT_ID 0 |
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[965] | 314 | #define IOX_DISK_TGT_ID 1 |
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[718] | 315 | #define IOX_MNIC_TGT_ID 2 |
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[1050] | 316 | #define IOX_BROM_TGT_ID 3 |
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| 317 | #define IOX_MTTY_TGT_ID 4 |
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| 318 | #define IOX_IOPI_TGT_ID 5 |
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| 319 | #define IOX_IOB0_TGT_ID 6 |
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| 320 | #define IOX_IOB1_TGT_ID 7 |
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[450] | 321 | |
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[965] | 322 | #define IOX_DISK_INI_ID 0 |
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[1050] | 323 | #define IOX_IOPI_INI_ID 1 |
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| 324 | #define IOX_MNIC_INI_ID 2 |
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[718] | 325 | #define IOX_IOB0_INI_ID 3 |
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| 326 | #define IOX_IOB1_INI_ID 4 |
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[450] | 327 | |
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[550] | 328 | //////////////////////////////////////////////////////////////////////// |
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[450] | 329 | int _main(int argc, char *argv[]) |
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[550] | 330 | //////////////////////////////////////////////////////////////////////// |
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[450] | 331 | { |
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| 332 | using namespace sc_core; |
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| 333 | using namespace soclib::caba; |
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| 334 | using namespace soclib::common; |
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| 335 | |
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[938] | 336 | char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code |
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| 337 | size_t ncycles = 4000000000; // simulated cycles |
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[965] | 338 | char disk_name[256] = DISK_IMAGE_NAME; // pathname: disk image |
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[966] | 339 | ssize_t threads = 1; // simulator's threads number |
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[938] | 340 | bool debug_ok = false; // trace activated |
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[1030] | 341 | uint32_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 342 | uint32_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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[938] | 343 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 344 | uint32_t debug_from = 0; // trace start cycle |
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| 345 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 346 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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| 347 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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| 348 | size_t x_width = X_WIDTH; // # of bits for x |
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| 349 | size_t y_width = Y_WIDTH; // # of bits for y |
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| 350 | size_t p_width = P_WIDTH; // # of bits for lpid |
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[450] | 351 | |
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[981] | 352 | #if USE_OPENMP |
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[762] | 353 | size_t simul_period = 1000000; |
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| 354 | #else |
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| 355 | size_t simul_period = 1; |
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| 356 | #endif |
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| 357 | |
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[607] | 358 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 359 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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[718] | 360 | |
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[818] | 361 | assert( P_WIDTH <= 4 and |
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| 362 | "ERROR: we must have P_WIDTH <= 4"); |
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[802] | 363 | |
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[450] | 364 | ////////////// command line arguments ////////////////////// |
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| 365 | if (argc > 1) |
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| 366 | { |
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| 367 | for (int n = 1; n < argc; n = n + 2) |
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| 368 | { |
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| 369 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 370 | { |
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| 371 | ncycles = atoi(argv[n+1]); |
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| 372 | } |
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| 373 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 374 | { |
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| 375 | debug_ok = true; |
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| 376 | debug_from = atoi(argv[n+1]); |
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| 377 | } |
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| 378 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 379 | { |
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| 380 | strcpy(disk_name, argv[n+1]); |
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| 381 | } |
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| 382 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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| 383 | { |
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| 384 | debug_memc_id = atoi(argv[n+1]); |
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[607] | 385 | size_t x = debug_memc_id >> 4; |
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| 386 | size_t y = debug_memc_id & 0xF; |
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| 387 | if( (x>=XMAX) || (y>=YMAX) ) |
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| 388 | { |
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[966] | 389 | std::cout << "MEMCID parameter doesn't fit XMAX/YMAX" << std::endl; |
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[914] | 390 | std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; |
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| 391 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
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| 392 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
---|
[607] | 393 | exit(0); |
---|
| 394 | } |
---|
[450] | 395 | } |
---|
| 396 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
---|
| 397 | { |
---|
| 398 | debug_iob = atoi(argv[n+1]); |
---|
| 399 | } |
---|
| 400 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
---|
| 401 | { |
---|
[607] | 402 | debug_proc_id = atoi(argv[n+1]); |
---|
[802] | 403 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
[607] | 404 | size_t x = cluster_xy >> 4; |
---|
| 405 | size_t y = cluster_xy & 0xF; |
---|
| 406 | if( (x>=XMAX) || (y>=YMAX) ) |
---|
| 407 | { |
---|
| 408 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
---|
[914] | 409 | std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; |
---|
| 410 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
---|
| 411 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
---|
[607] | 412 | exit(0); |
---|
| 413 | } |
---|
[450] | 414 | } |
---|
| 415 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
---|
| 416 | { |
---|
[966] | 417 | threads = atoi(argv[n+1]); |
---|
| 418 | threads = (threads < 1) ? 1 : threads; |
---|
[450] | 419 | } |
---|
| 420 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
| 421 | { |
---|
| 422 | frozen_cycles = atoi(argv[n+1]); |
---|
| 423 | } |
---|
| 424 | else |
---|
| 425 | { |
---|
| 426 | std::cout << " Arguments are (key,value) couples." << std::endl; |
---|
| 427 | std::cout << " The order is not important." << std::endl; |
---|
| 428 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
[938] | 429 | std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 430 | std::cout << " - DEBUG debug_start_cycle" << std::endl; |
---|
| 431 | std::cout << " - THREADS simulator's threads number" << std::endl; |
---|
[1030] | 432 | std::cout << " - FROZEN max_number_of_cycles" << std::endl; |
---|
[938] | 433 | std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 434 | std::cout << " - PROCID index_proc_to_be_traced" << std::endl; |
---|
| 435 | std::cout << " - IOB non_zero_value" << std::endl; |
---|
[450] | 436 | exit(0); |
---|
| 437 | } |
---|
| 438 | } |
---|
| 439 | } |
---|
| 440 | |
---|
| 441 | // checking hardware parameters |
---|
[607] | 442 | assert( (XMAX <= 16) and |
---|
[972] | 443 | "Error in tsar_generic_iob : XMAX parameter cannot be larger than 16" ); |
---|
[450] | 444 | |
---|
[607] | 445 | assert( (YMAX <= 16) and |
---|
[972] | 446 | "Error in tsar_generic_iob : YMAX parameter cannot be larger than 16" ); |
---|
[450] | 447 | |
---|
[959] | 448 | assert( (NB_PROCS_MAX <= 8) and |
---|
[972] | 449 | "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
[450] | 450 | |
---|
[1050] | 451 | assert( (ICU_NB_HWI > NB_PROCS_MAX) and |
---|
| 452 | "Error in tsar_generic_iob : ICU_NB_HWI cannot be smaller than NB_PROCS_MAX" ); |
---|
[959] | 453 | |
---|
[1050] | 454 | assert( (ICU_NB_PTI >= NB_PROCS_MAX) and |
---|
| 455 | "Error in tsar_generic_iob : ICU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); |
---|
[959] | 456 | |
---|
[1050] | 457 | assert( (ICU_NB_WTI >= 4*NB_PROCS_MAX) and |
---|
| 458 | "Error in tsar_generic_iob : ICU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
[959] | 459 | |
---|
[1050] | 460 | assert( (ICU_NB_OUT >= 4*NB_PROCS_MAX) and |
---|
| 461 | "Error in tsar_generic_iob : ICU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
[959] | 462 | |
---|
[1053] | 463 | assert( (NB_TXT_CHANNELS >= 1) and (NB_TXT_CHANNELS <= 8) and |
---|
[1050] | 464 | "Error in tsar_generic_iob : NB_TXT_CHANNELS parameter cannot be larger than 16" ); |
---|
[450] | 465 | |
---|
[1050] | 466 | assert( (NB_NIC_CHANNELS <= 4) and |
---|
| 467 | "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 4" ); |
---|
[450] | 468 | |
---|
[966] | 469 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
---|
[972] | 470 | "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); |
---|
[966] | 471 | |
---|
[972] | 472 | assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and |
---|
| 473 | "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); |
---|
| 474 | |
---|
[707] | 475 | std::cout << std::endl << std::dec |
---|
| 476 | << " - XMAX = " << XMAX << std::endl |
---|
| 477 | << " - YMAX = " << YMAX << std::endl |
---|
[802] | 478 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
[1050] | 479 | << " - NB_TXT_CHANNELS = " << NB_TXT_CHANNELS << std::endl |
---|
[707] | 480 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
| 481 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 482 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 483 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 484 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[914] | 485 | << " - NCYCLES = " << ncycles << std::endl |
---|
[966] | 486 | << " - SOFT_FILENAME = " << soft_name << std::endl |
---|
| 487 | << " - DISK_IMAGENAME = " << disk_name << std::endl |
---|
| 488 | << " - OPENMP THREADS = " << threads << std::endl |
---|
[707] | 489 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
[1030] | 490 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl; |
---|
[450] | 491 | |
---|
| 492 | std::cout << std::endl; |
---|
| 493 | |
---|
[981] | 494 | #if USE_OPENMP |
---|
[450] | 495 | omp_set_dynamic(false); |
---|
[966] | 496 | omp_set_num_threads(threads); |
---|
[450] | 497 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 498 | #endif |
---|
| 499 | |
---|
| 500 | // Define VciParams objects |
---|
| 501 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 502 | vci_plen_width, |
---|
| 503 | vci_address_width, |
---|
| 504 | vci_rerror_width, |
---|
| 505 | vci_clen_width, |
---|
| 506 | vci_rflag_width, |
---|
| 507 | vci_srcid_width, |
---|
| 508 | vci_pktid_width, |
---|
| 509 | vci_trdid_width, |
---|
| 510 | vci_wrplen_width> vci_param_int; |
---|
| 511 | |
---|
| 512 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 513 | vci_plen_width, |
---|
| 514 | vci_address_width, |
---|
[718] | 515 | vci_rerror_width, |
---|
[450] | 516 | vci_clen_width, |
---|
| 517 | vci_rflag_width, |
---|
| 518 | vci_srcid_width, |
---|
| 519 | vci_pktid_width, |
---|
| 520 | vci_trdid_width, |
---|
| 521 | vci_wrplen_width> vci_param_ext; |
---|
| 522 | |
---|
| 523 | ///////////////////////////////////////////////////////////////////// |
---|
| 524 | // INT network mapping table |
---|
| 525 | // - two levels address decoding for commands |
---|
| 526 | // - two levels srcid decoding for responses |
---|
[1051] | 527 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 528 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
[450] | 529 | ///////////////////////////////////////////////////////////////////// |
---|
[718] | 530 | MappingTable maptab_int( vci_address_width, |
---|
| 531 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
| 532 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 533 | 0x00FF000000); |
---|
| 534 | |
---|
| 535 | for (size_t x = 0; x < XMAX; x++) |
---|
| 536 | { |
---|
| 537 | for (size_t y = 0; y < YMAX; y++) |
---|
| 538 | { |
---|
[718] | 539 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 540 | << (vci_address_width-x_width-y_width); |
---|
[550] | 541 | bool config = true; |
---|
| 542 | bool cacheable = true; |
---|
[450] | 543 | |
---|
| 544 | // the four following segments are defined in all clusters |
---|
| 545 | |
---|
| 546 | std::ostringstream smemc_conf; |
---|
| 547 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
[718] | 548 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
| 549 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[450] | 550 | |
---|
| 551 | std::ostringstream smemc_xram; |
---|
| 552 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
[718] | 553 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
| 554 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
---|
[450] | 555 | |
---|
| 556 | std::ostringstream sxicu; |
---|
| 557 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
[1050] | 558 | maptab_int.add(Segment(sxicu.str(), SEG_ICU_BASE+offset, SEG_ICU_SIZE, |
---|
[718] | 559 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
---|
[450] | 560 | |
---|
[1051] | 561 | std::ostringstream smdma; |
---|
| 562 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
| 563 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
| 564 | IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); |
---|
[450] | 565 | |
---|
| 566 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 567 | |
---|
[718] | 568 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
[450] | 569 | { |
---|
| 570 | std::ostringstream siobx; |
---|
| 571 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
[718] | 572 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[550] | 573 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[450] | 574 | |
---|
| 575 | std::ostringstream stty; |
---|
| 576 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
[1050] | 577 | maptab_int.add(Segment(stty.str(), SEG_TXT_BASE+offset, SEG_TXT_SIZE, |
---|
[550] | 578 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 579 | |
---|
| 580 | std::ostringstream sfbf; |
---|
| 581 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
[718] | 582 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[550] | 583 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 584 | |
---|
[965] | 585 | std::ostringstream sdsk; |
---|
| 586 | sdsk << "int_seg_disk_" << x << "_" << y; |
---|
| 587 | maptab_int.add(Segment(sdsk.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[550] | 588 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 589 | |
---|
| 590 | std::ostringstream snic; |
---|
| 591 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
[718] | 592 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[550] | 593 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 594 | |
---|
| 595 | std::ostringstream srom; |
---|
| 596 | srom << "int_seg_brom_" << x << "_" << y; |
---|
[718] | 597 | maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[550] | 598 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); |
---|
[450] | 599 | |
---|
[707] | 600 | std::ostringstream spic; |
---|
| 601 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
[718] | 602 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[707] | 603 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 604 | } |
---|
| 605 | |
---|
| 606 | // This define the mapping between the SRCIDs |
---|
| 607 | // and the port index on the local interconnect. |
---|
| 608 | |
---|
[1051] | 609 | maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), |
---|
| 610 | IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); |
---|
[450] | 611 | |
---|
[550] | 612 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
---|
| 613 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
[450] | 614 | |
---|
[707] | 615 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
---|
| 616 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
| 617 | |
---|
[802] | 618 | for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) |
---|
[718] | 619 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
---|
[550] | 620 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
---|
[450] | 621 | } |
---|
| 622 | } |
---|
| 623 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 624 | |
---|
| 625 | ///////////////////////////////////////////////////////////////////////// |
---|
[718] | 626 | // RAM network mapping table |
---|
[450] | 627 | // - two levels address decoding for commands |
---|
| 628 | // - two levels srcid decoding for responses |
---|
[718] | 629 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
[450] | 630 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 631 | // - 1 local target (XRAM) per cluster |
---|
| 632 | //////////////////////////////////////////////////////////////////////// |
---|
| 633 | MappingTable maptab_ram( vci_address_width, |
---|
[718] | 634 | IntTab(x_width+y_width, 0), |
---|
| 635 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 636 | 0x00FF000000); |
---|
| 637 | |
---|
| 638 | for (size_t x = 0; x < XMAX; x++) |
---|
| 639 | { |
---|
| 640 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 641 | { |
---|
| 642 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 643 | << (vci_address_width-x_width-y_width); |
---|
| 644 | |
---|
| 645 | std::ostringstream sxram; |
---|
| 646 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
[718] | 647 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
| 648 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
[450] | 649 | } |
---|
| 650 | } |
---|
| 651 | |
---|
[550] | 652 | // This define the mapping between the initiators SRCID |
---|
| 653 | // and the port index on the RAM local interconnect. |
---|
[1050] | 654 | // This routing table is used to route the response to the |
---|
| 655 | // relevant initiator: external peripherals transactions |
---|
| 656 | // use IOBX port, while MEMC transactions use MEMC port. |
---|
[450] | 657 | |
---|
[965] | 658 | maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), |
---|
[550] | 659 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
[450] | 660 | |
---|
[965] | 661 | maptab_ram.srcid_map( IntTab( cluster_iob1, DISK_LOCAL_SRCID ), |
---|
[550] | 662 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 663 | |
---|
[718] | 664 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 665 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 666 | |
---|
| 667 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 668 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 669 | |
---|
[1050] | 670 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNRX_LOCAL_SRCID ), |
---|
| 671 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 672 | |
---|
| 673 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNRX_LOCAL_SRCID ), |
---|
| 674 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 675 | |
---|
| 676 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNTX_LOCAL_SRCID ), |
---|
| 677 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 678 | |
---|
| 679 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNTX_LOCAL_SRCID ), |
---|
| 680 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 681 | |
---|
[718] | 682 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 683 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 684 | |
---|
| 685 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
[550] | 686 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 687 | |
---|
[450] | 688 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 689 | |
---|
| 690 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 691 | // IOX network mapping table |
---|
[1050] | 692 | // - two levels address decoding for commands |
---|
[450] | 693 | // - two levels srcid decoding for responses |
---|
[1050] | 694 | // - 5 initiators (IOB0, IOB1, DISK, MNIC, IOPI) |
---|
| 695 | // - 8 targets (IOB0, IOB1, DISK, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
[718] | 696 | // |
---|
| 697 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 698 | // IOB0 or IOB1. |
---|
[450] | 699 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 700 | MappingTable maptab_iox( |
---|
| 701 | vci_address_width, |
---|
| 702 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
---|
| 703 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
---|
| 704 | 0x00FF000000); |
---|
[450] | 705 | |
---|
[707] | 706 | // External peripherals segments |
---|
[718] | 707 | // When there is more than one cluster, external peripherals can be accessed |
---|
[707] | 708 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
[718] | 709 | |
---|
| 710 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 711 | << (vci_address_width - x_width - y_width); |
---|
| 712 | |
---|
[1050] | 713 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TXT_BASE + iob0_base, SEG_TXT_SIZE, |
---|
[718] | 714 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 715 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 716 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 717 | maptab_iox.add(Segment("iox_seg_disk_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 718 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 719 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 720 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 721 | maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, |
---|
| 722 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 723 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 724 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
| 725 | |
---|
[707] | 726 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 727 | { |
---|
[718] | 728 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 729 | << (vci_address_width - x_width - y_width); |
---|
| 730 | |
---|
[1050] | 731 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TXT_BASE + iob1_base, SEG_TXT_SIZE, |
---|
[718] | 732 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 733 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 734 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 735 | maptab_iox.add(Segment("iox_seg_disk_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 736 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 737 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 738 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 739 | maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, |
---|
| 740 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 741 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 742 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[707] | 743 | } |
---|
[450] | 744 | |
---|
[718] | 745 | // If there is more than one cluster, external peripherals |
---|
[707] | 746 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 747 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
[718] | 748 | // and the choice depends on address bit A[32]. |
---|
[450] | 749 | for (size_t x = 0; x < XMAX; x++) |
---|
| 750 | { |
---|
| 751 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 752 | { |
---|
| 753 | const bool wti = true; |
---|
| 754 | const bool cacheable = true; |
---|
[450] | 755 | |
---|
[718] | 756 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 757 | << (vci_address_width-x_width-y_width); |
---|
| 758 | |
---|
[1050] | 759 | const uint64_t xicu_base = SEG_ICU_BASE + offset; |
---|
[718] | 760 | |
---|
| 761 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
[450] | 762 | { |
---|
[718] | 763 | std::ostringstream sxcu0; |
---|
| 764 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
[1050] | 765 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_ICU_SIZE, |
---|
[718] | 766 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 767 | |
---|
| 768 | std::ostringstream siob0; |
---|
| 769 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
[1050] | 770 | maptab_iox.add(Segment(siob0.str(), offset, SEG_ICU_BASE, |
---|
[718] | 771 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
[707] | 772 | } |
---|
[718] | 773 | else // USE IOB1 |
---|
[707] | 774 | { |
---|
[718] | 775 | std::ostringstream sxcu1; |
---|
| 776 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
[1050] | 777 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_ICU_SIZE, |
---|
[718] | 778 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 779 | |
---|
| 780 | std::ostringstream siob1; |
---|
| 781 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
[1050] | 782 | maptab_iox.add(Segment(siob1.str(), offset, SEG_ICU_BASE, |
---|
[718] | 783 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
[450] | 784 | } |
---|
| 785 | } |
---|
| 786 | } |
---|
| 787 | |
---|
[707] | 788 | // This define the mapping between the external initiators (SRCID) |
---|
[1050] | 789 | // and the initiator port index on the IOX local interconnect. |
---|
[550] | 790 | |
---|
[965] | 791 | maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , |
---|
| 792 | IntTab( 0, IOX_DISK_INI_ID ) ); |
---|
[1050] | 793 | |
---|
[718] | 794 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 795 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
[1050] | 796 | |
---|
[718] | 797 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 798 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 799 | |
---|
[1050] | 800 | maptab_iox.srcid_map( IntTab( 0, MNRX_LOCAL_SRCID ) , |
---|
| 801 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
---|
| 802 | |
---|
| 803 | maptab_iox.srcid_map( IntTab( 0, MNTX_LOCAL_SRCID ) , |
---|
| 804 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
---|
| 805 | |
---|
[707] | 806 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 807 | { |
---|
[718] | 808 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 809 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
[707] | 810 | } |
---|
[550] | 811 | |
---|
[450] | 812 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 813 | |
---|
| 814 | //////////////////// |
---|
| 815 | // Signals |
---|
| 816 | /////////////////// |
---|
| 817 | |
---|
[550] | 818 | sc_clock signal_clk("clk"); |
---|
| 819 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 820 | |
---|
[584] | 821 | sc_signal<bool> signal_irq_false; |
---|
[965] | 822 | sc_signal<bool> signal_irq_disk; |
---|
[1050] | 823 | sc_signal<bool> signal_irq_mtty_rx[NB_TXT_CHANNELS]; |
---|
[1053] | 824 | sc_signal<bool> signal_irq_mtty_tx[NB_TXT_CHANNELS]; |
---|
[550] | 825 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 826 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
[450] | 827 | |
---|
| 828 | // VCI signals for IOX network |
---|
[550] | 829 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 830 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
[965] | 831 | VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); |
---|
[707] | 832 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
[1050] | 833 | VciSignals<vci_param_ext> signal_vci_ini_mnic("signal_vci_ini_mnic"); |
---|
[450] | 834 | |
---|
[550] | 835 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 836 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 837 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 838 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 839 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 840 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
---|
[965] | 841 | VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); |
---|
[953] | 842 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
---|
[450] | 843 | |
---|
[1002] | 844 | // Horizontal inter-clusters INT_CMD DSPIN |
---|
| 845 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_inc = |
---|
| 846 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX); |
---|
| 847 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_dec = |
---|
| 848 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX); |
---|
[450] | 849 | |
---|
[1002] | 850 | // Horizontal inter-clusters INT_RSP DSPIN |
---|
| 851 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_inc = |
---|
| 852 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX); |
---|
| 853 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_dec = |
---|
| 854 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX); |
---|
[450] | 855 | |
---|
[1002] | 856 | // Horizontal inter-clusters INT_M2P DSPIN |
---|
| 857 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_inc = |
---|
| 858 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_inc", XMAX-1, YMAX); |
---|
| 859 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_dec = |
---|
| 860 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_dec", XMAX-1, YMAX); |
---|
[450] | 861 | |
---|
[1002] | 862 | // Horizontal inter-clusters INT_P2M DSPIN |
---|
| 863 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_inc = |
---|
| 864 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_inc", XMAX-1, YMAX); |
---|
| 865 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_dec = |
---|
| 866 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_dec", XMAX-1, YMAX); |
---|
[450] | 867 | |
---|
[1002] | 868 | // Horizontal inter-clusters INT_CLA DSPIN |
---|
| 869 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_inc = |
---|
| 870 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_inc", XMAX-1, YMAX); |
---|
| 871 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_dec = |
---|
| 872 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_dec", XMAX-1, YMAX); |
---|
| 873 | |
---|
| 874 | |
---|
| 875 | // Vertical inter-clusters INT_CMD DSPIN |
---|
| 876 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_inc = |
---|
| 877 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1); |
---|
| 878 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_dec = |
---|
| 879 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1); |
---|
| 880 | |
---|
| 881 | // Vertical inter-clusters INT_RSP DSPIN |
---|
| 882 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_inc = |
---|
| 883 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1); |
---|
| 884 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_dec = |
---|
| 885 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1); |
---|
| 886 | |
---|
| 887 | // Vertical inter-clusters INT_M2P DSPIN |
---|
| 888 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_inc = |
---|
| 889 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_inc", XMAX, YMAX-1); |
---|
| 890 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_dec = |
---|
| 891 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_dec", XMAX, YMAX-1); |
---|
| 892 | |
---|
| 893 | // Vertical inter-clusters INT_P2M DSPIN |
---|
| 894 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_inc = |
---|
| 895 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_inc", XMAX, YMAX-1); |
---|
| 896 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_dec = |
---|
| 897 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_dec", XMAX, YMAX-1); |
---|
| 898 | |
---|
| 899 | // Vertical inter-clusters INT_CLA DSPIN |
---|
| 900 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_inc = |
---|
| 901 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_inc", XMAX, YMAX-1); |
---|
| 902 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_dec = |
---|
| 903 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_dec", XMAX, YMAX-1); |
---|
| 904 | |
---|
| 905 | |
---|
| 906 | // Mesh boundaries INT_CMD DSPIN |
---|
| 907 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_in = |
---|
| 908 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4); |
---|
| 909 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_out = |
---|
| 910 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4); |
---|
| 911 | |
---|
| 912 | // Mesh boundaries INT_RSP DSPIN |
---|
| 913 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_in = |
---|
| 914 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4); |
---|
| 915 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_out = |
---|
| 916 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4); |
---|
| 917 | |
---|
| 918 | // Mesh boundaries INT_M2P DSPIN |
---|
| 919 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_in = |
---|
| 920 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2p_in", XMAX, YMAX, 4); |
---|
| 921 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_out = |
---|
| 922 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2P_out", XMAX, YMAX, 4); |
---|
| 923 | |
---|
| 924 | // Mesh boundaries INT_P2M DSPIN |
---|
| 925 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_in = |
---|
| 926 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_in", XMAX, YMAX, 4); |
---|
| 927 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_out = |
---|
| 928 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_out", XMAX, YMAX, 4); |
---|
| 929 | |
---|
| 930 | // Mesh boundaries INT_CLA DSPIN |
---|
| 931 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_in = |
---|
| 932 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_in", XMAX, YMAX, 4); |
---|
| 933 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_out = |
---|
| 934 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_out", XMAX, YMAX, 4); |
---|
| 935 | |
---|
| 936 | |
---|
| 937 | // Horizontal inter-clusters RAM_CMD DSPIN |
---|
[450] | 938 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
| 939 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
| 940 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
| 941 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
[1002] | 942 | |
---|
| 943 | // Horizontal inter-clusters RAM_RSP DSPIN |
---|
[450] | 944 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
| 945 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
| 946 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
| 947 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
| 948 | |
---|
[1002] | 949 | // Vertical inter-clusters RAM_CMD DSPIN |
---|
[450] | 950 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
| 951 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
| 952 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
| 953 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
[1002] | 954 | |
---|
| 955 | // Vertical inter-clusters RAM_RSP DSPIN |
---|
[450] | 956 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
| 957 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
| 958 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
| 959 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
| 960 | |
---|
[1002] | 961 | // Mesh boundaries RAM_CMD DSPIN |
---|
[450] | 962 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
| 963 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
| 964 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
| 965 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
[1002] | 966 | |
---|
| 967 | // Mesh boundaries RAM_RSP DSPIN |
---|
[450] | 968 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
| 969 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
| 970 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
| 971 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
| 972 | |
---|
[1002] | 973 | // SD card signals |
---|
| 974 | sc_signal<bool> signal_sdc_clk; |
---|
| 975 | sc_signal<bool> signal_sdc_cmd_enable_to_card; |
---|
| 976 | sc_signal<bool> signal_sdc_cmd_value_to_card; |
---|
| 977 | sc_signal<bool> signal_sdc_dat_enable_to_card; |
---|
| 978 | sc_signal<bool> signal_sdc_dat_value_to_card[4]; |
---|
| 979 | sc_signal<bool> signal_sdc_cmd_enable_from_card; |
---|
| 980 | sc_signal<bool> signal_sdc_cmd_value_from_card; |
---|
| 981 | sc_signal<bool> signal_sdc_dat_enable_from_card; |
---|
| 982 | sc_signal<bool> signal_sdc_dat_value_from_card[4]; |
---|
| 983 | |
---|
[1046] | 984 | //////////////////////////////////////////////// |
---|
| 985 | // Load the preloader code in the ROM |
---|
| 986 | //////////////////////////////////////////////// |
---|
[450] | 987 | |
---|
[965] | 988 | soclib::common::Loader loader(soft_name); |
---|
[450] | 989 | |
---|
[965] | 990 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 991 | proc_iss::set_loader(loader); |
---|
[450] | 992 | |
---|
[965] | 993 | //////////////////////////////////////// |
---|
| 994 | // Instanciated Hardware Components |
---|
| 995 | //////////////////////////////////////// |
---|
[450] | 996 | |
---|
[965] | 997 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
[450] | 998 | |
---|
[965] | 999 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
[1050] | 1000 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; |
---|
[718] | 1001 | |
---|
[965] | 1002 | // IOX network |
---|
| 1003 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 1004 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 1005 | maptab_iox, |
---|
| 1006 | nb_iox_targets, |
---|
| 1007 | nb_iox_initiators ); |
---|
| 1008 | // boot ROM |
---|
| 1009 | VciSimpleRom<vci_param_ext>* brom; |
---|
| 1010 | brom = new VciSimpleRom<vci_param_ext>( "brom", |
---|
| 1011 | IntTab(0, IOX_BROM_TGT_ID), |
---|
| 1012 | maptab_iox, |
---|
| 1013 | loader ); |
---|
[1050] | 1014 | // Ethernet Controller |
---|
| 1015 | VciMasterNic<vci_param_ext>* mnic; |
---|
| 1016 | mnic = new VciMasterNic<vci_param_ext>( "mnic", |
---|
| 1017 | maptab_iox, |
---|
| 1018 | IntTab(0, MNRX_LOCAL_SRCID), |
---|
| 1019 | IntTab(0, MNTX_LOCAL_SRCID), |
---|
| 1020 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 1021 | NB_NIC_CHANNELS, |
---|
| 1022 | 64, // burst length |
---|
| 1023 | MNIC_MAC_4, // default MAC address (LSB) |
---|
| 1024 | MNIC_MAC_2, // default MAC address (MSB) |
---|
| 1025 | 1, // NIC_MODE_SYNTHESIS |
---|
| 1026 | 12); // INTER_FRAME_GAP |
---|
[450] | 1027 | |
---|
[965] | 1028 | // Frame Buffer |
---|
| 1029 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 1030 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 1031 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 1032 | maptab_iox, |
---|
| 1033 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 1034 | |
---|
[965] | 1035 | // Disk |
---|
| 1036 | std::vector<std::string> filenames; |
---|
| 1037 | filenames.push_back(disk_name); // one single disk |
---|
| 1038 | |
---|
| 1039 | #if ( USE_IOC_HBA ) |
---|
[966] | 1040 | |
---|
[965] | 1041 | VciMultiAhci<vci_param_ext>* disk; |
---|
| 1042 | disk = new VciMultiAhci<vci_param_ext>( "disk", |
---|
| 1043 | maptab_iox, |
---|
| 1044 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1045 | IntTab(0, IOX_DISK_TGT_ID), |
---|
| 1046 | filenames, |
---|
| 1047 | 512, // block size |
---|
| 1048 | 64, // burst size (bytes) |
---|
| 1049 | 0 ); // disk latency |
---|
[1002] | 1050 | #elif ( USE_IOC_BDV ) |
---|
[966] | 1051 | |
---|
[965] | 1052 | VciBlockDeviceTsar<vci_param_ext>* disk; |
---|
| 1053 | disk = new VciBlockDeviceTsar<vci_param_ext>( "disk", |
---|
[550] | 1054 | maptab_iox, |
---|
[965] | 1055 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1056 | IntTab(0, IOX_DISK_TGT_ID), |
---|
[550] | 1057 | disk_name, |
---|
[714] | 1058 | 512, // block size |
---|
[718] | 1059 | 64, // burst size (bytes) |
---|
| 1060 | 0 ); // disk latency |
---|
[1002] | 1061 | #elif ( USE_IOC_SDC ) |
---|
| 1062 | |
---|
| 1063 | VciAhciSdc<vci_param_ext>* disk; |
---|
| 1064 | disk = new VciAhciSdc<vci_param_ext>( "disk", |
---|
| 1065 | maptab_iox, |
---|
| 1066 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1067 | IntTab(0, IOX_DISK_TGT_ID), |
---|
| 1068 | 64 ); // burst size (bytes) |
---|
| 1069 | SdCard* card; |
---|
| 1070 | card = new SdCard( "card", |
---|
| 1071 | disk_name, |
---|
| 1072 | 10, // RX one block latency |
---|
| 1073 | 10 ); // TX one block latency |
---|
[965] | 1074 | #endif |
---|
[450] | 1075 | |
---|
[1053] | 1076 | // TTY controller |
---|
[965] | 1077 | std::vector<std::string> vect_names; |
---|
[1050] | 1078 | for( size_t tid = 0 ; tid < NB_TXT_CHANNELS ; tid++ ) |
---|
[965] | 1079 | { |
---|
| 1080 | std::ostringstream term_name; |
---|
| 1081 | term_name << "term" << tid; |
---|
| 1082 | |
---|
[707] | 1083 | vect_names.push_back(term_name.str().c_str()); |
---|
[1053] | 1084 | } |
---|
| 1085 | VciTtyTsar<vci_param_ext>* mtty; |
---|
| 1086 | mtty = new VciTtyTsar<vci_param_ext>( "mtty", |
---|
| 1087 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 1088 | maptab_iox, |
---|
| 1089 | vect_names); |
---|
[707] | 1090 | |
---|
[965] | 1091 | // IOPIC |
---|
| 1092 | VciIopic<vci_param_ext>* iopi; |
---|
| 1093 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 1094 | maptab_iox, |
---|
| 1095 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 1096 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 1097 | 32 ); // number of input HWI |
---|
| 1098 | // Clusters |
---|
| 1099 | TsarIobCluster<vci_param_int, |
---|
| 1100 | vci_param_ext, |
---|
| 1101 | dspin_int_cmd_width, |
---|
| 1102 | dspin_int_rsp_width, |
---|
| 1103 | dspin_ram_cmd_width, |
---|
| 1104 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
[450] | 1105 | |
---|
[1051] | 1106 | unsigned int coproc_type = 0; |
---|
[972] | 1107 | |
---|
[981] | 1108 | #if USE_OPENMP |
---|
[450] | 1109 | #pragma omp parallel |
---|
| 1110 | { |
---|
| 1111 | #pragma omp for |
---|
| 1112 | #endif |
---|
| 1113 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
| 1114 | { |
---|
| 1115 | size_t x = i / YMAX; |
---|
| 1116 | size_t y = i % YMAX; |
---|
| 1117 | |
---|
[981] | 1118 | #if USE_OPENMP |
---|
[450] | 1119 | #pragma omp critical |
---|
| 1120 | { |
---|
| 1121 | #endif |
---|
| 1122 | std::cout << std::endl; |
---|
| 1123 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1124 | std::cout << std::endl; |
---|
| 1125 | |
---|
[718] | 1126 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
---|
| 1127 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
---|
| 1128 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1129 | |
---|
| 1130 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1131 | IOX_IOB0_INI_ID : |
---|
| 1132 | IOX_IOB1_INI_ID ; |
---|
| 1133 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1134 | IOX_IOB0_TGT_ID : |
---|
| 1135 | IOX_IOB1_TGT_ID ; |
---|
| 1136 | |
---|
[972] | 1137 | |
---|
[450] | 1138 | std::ostringstream sc; |
---|
| 1139 | sc << "cluster_" << x << "_" << y; |
---|
| 1140 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1141 | vci_param_ext, |
---|
| 1142 | dspin_int_cmd_width, |
---|
| 1143 | dspin_int_rsp_width, |
---|
| 1144 | dspin_ram_cmd_width, |
---|
| 1145 | dspin_ram_rsp_width> |
---|
| 1146 | ( |
---|
| 1147 | sc.str().c_str(), |
---|
| 1148 | NB_PROCS_MAX, |
---|
| 1149 | x, |
---|
| 1150 | y, |
---|
| 1151 | XMAX, |
---|
| 1152 | YMAX, |
---|
| 1153 | |
---|
| 1154 | maptab_int, |
---|
| 1155 | maptab_ram, |
---|
| 1156 | maptab_iox, |
---|
| 1157 | |
---|
| 1158 | x_width, |
---|
| 1159 | y_width, |
---|
| 1160 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
[802] | 1161 | p_width, |
---|
[450] | 1162 | |
---|
| 1163 | INT_MEMC_TGT_ID, |
---|
| 1164 | INT_XICU_TGT_ID, |
---|
[1051] | 1165 | INT_MDMA_TGT_ID, |
---|
[450] | 1166 | INT_IOBX_TGT_ID, |
---|
| 1167 | |
---|
| 1168 | INT_PROC_INI_ID, |
---|
[1051] | 1169 | INT_MDMA_INI_ID, |
---|
[450] | 1170 | INT_IOBX_INI_ID, |
---|
| 1171 | |
---|
| 1172 | RAM_XRAM_TGT_ID, |
---|
| 1173 | |
---|
| 1174 | RAM_MEMC_INI_ID, |
---|
[550] | 1175 | RAM_IOBX_INI_ID, |
---|
[450] | 1176 | |
---|
[718] | 1177 | is_io_cluster, |
---|
| 1178 | iox_iob_tgt_id, |
---|
| 1179 | iox_iob_ini_id, |
---|
| 1180 | |
---|
[450] | 1181 | MEMC_WAYS, |
---|
| 1182 | MEMC_SETS, |
---|
| 1183 | L1_IWAYS, |
---|
| 1184 | L1_ISETS, |
---|
| 1185 | L1_DWAYS, |
---|
| 1186 | L1_DSETS, |
---|
| 1187 | XRAM_LATENCY, |
---|
[1050] | 1188 | ICU_NB_HWI, |
---|
| 1189 | ICU_NB_PTI, |
---|
| 1190 | ICU_NB_WTI, |
---|
| 1191 | ICU_NB_OUT, |
---|
[450] | 1192 | |
---|
[972] | 1193 | coproc_type, |
---|
| 1194 | |
---|
[450] | 1195 | loader, |
---|
| 1196 | |
---|
| 1197 | frozen_cycles, |
---|
[1030] | 1198 | debug_ok, |
---|
[450] | 1199 | debug_from, |
---|
[1030] | 1200 | debug_proc_id, |
---|
| 1201 | debug_memc_id, |
---|
| 1202 | debug_iob |
---|
[450] | 1203 | ); |
---|
| 1204 | |
---|
[981] | 1205 | #if USE_OPENMP |
---|
[450] | 1206 | } // end critical |
---|
| 1207 | #endif |
---|
| 1208 | } // end for |
---|
[981] | 1209 | #if USE_OPENMP |
---|
[450] | 1210 | } |
---|
| 1211 | #endif |
---|
| 1212 | |
---|
| 1213 | std::cout << std::endl; |
---|
| 1214 | |
---|
| 1215 | /////////////////////////////////////////////////////////////////////////////// |
---|
[718] | 1216 | // Net-list |
---|
[450] | 1217 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1218 | |
---|
| 1219 | // IOX network connexion |
---|
[584] | 1220 | iox_network->p_clk (signal_clk); |
---|
| 1221 | iox_network->p_resetn (signal_resetn); |
---|
| 1222 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
[965] | 1223 | iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); |
---|
[707] | 1224 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
[1050] | 1225 | iox_network->p_to_ini[IOX_MNIC_INI_ID] (signal_vci_ini_mnic); |
---|
[707] | 1226 | |
---|
[584] | 1227 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1228 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1229 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1230 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1231 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
---|
[965] | 1232 | iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); |
---|
[707] | 1233 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[450] | 1234 | |
---|
[718] | 1235 | if (cluster_iob0 != cluster_iob1) |
---|
| 1236 | { |
---|
| 1237 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1238 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1239 | } |
---|
| 1240 | |
---|
[965] | 1241 | // DISK connexion |
---|
[1002] | 1242 | |
---|
| 1243 | #if ( USE_IOC_HBA ) |
---|
| 1244 | |
---|
[965] | 1245 | disk->p_clk (signal_clk); |
---|
| 1246 | disk->p_resetn (signal_resetn); |
---|
| 1247 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1248 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
| 1249 | disk->p_channel_irq[0] (signal_irq_disk); |
---|
[1002] | 1250 | |
---|
| 1251 | #elif ( USE_IOC_BDV ) |
---|
| 1252 | |
---|
| 1253 | disk->p_clk (signal_clk); |
---|
| 1254 | disk->p_resetn (signal_resetn); |
---|
| 1255 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1256 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
[965] | 1257 | disk->p_irq (signal_irq_disk); |
---|
[1002] | 1258 | |
---|
| 1259 | #elif ( USE_IOC_SDC ) |
---|
| 1260 | |
---|
| 1261 | disk->p_clk (signal_clk); |
---|
| 1262 | disk->p_resetn (signal_resetn); |
---|
| 1263 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1264 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
| 1265 | disk->p_irq (signal_irq_disk); |
---|
| 1266 | |
---|
| 1267 | disk->p_sdc_clk (signal_sdc_clk); |
---|
| 1268 | disk->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_to_card); |
---|
| 1269 | disk->p_sdc_cmd_value_out (signal_sdc_cmd_value_to_card); |
---|
| 1270 | disk->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_from_card); |
---|
| 1271 | disk->p_sdc_cmd_value_in (signal_sdc_cmd_value_from_card); |
---|
| 1272 | disk->p_sdc_dat_enable_out (signal_sdc_dat_enable_to_card); |
---|
| 1273 | disk->p_sdc_dat_value_out[0] (signal_sdc_dat_value_to_card[0]); |
---|
| 1274 | disk->p_sdc_dat_value_out[1] (signal_sdc_dat_value_to_card[1]); |
---|
| 1275 | disk->p_sdc_dat_value_out[2] (signal_sdc_dat_value_to_card[2]); |
---|
| 1276 | disk->p_sdc_dat_value_out[3] (signal_sdc_dat_value_to_card[3]); |
---|
| 1277 | disk->p_sdc_dat_enable_in (signal_sdc_dat_enable_from_card); |
---|
| 1278 | disk->p_sdc_dat_value_in[0] (signal_sdc_dat_value_from_card[0]); |
---|
| 1279 | disk->p_sdc_dat_value_in[1] (signal_sdc_dat_value_from_card[1]); |
---|
| 1280 | disk->p_sdc_dat_value_in[2] (signal_sdc_dat_value_from_card[2]); |
---|
| 1281 | disk->p_sdc_dat_value_in[3] (signal_sdc_dat_value_from_card[3]); |
---|
| 1282 | |
---|
| 1283 | card->p_clk (signal_clk); |
---|
| 1284 | card->p_resetn (signal_resetn); |
---|
| 1285 | |
---|
| 1286 | card->p_sdc_clk (signal_sdc_clk); |
---|
| 1287 | card->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_from_card); |
---|
| 1288 | card->p_sdc_cmd_value_out (signal_sdc_cmd_value_from_card); |
---|
| 1289 | card->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_to_card); |
---|
| 1290 | card->p_sdc_cmd_value_in (signal_sdc_cmd_value_to_card); |
---|
| 1291 | card->p_sdc_dat_enable_out (signal_sdc_dat_enable_from_card); |
---|
| 1292 | card->p_sdc_dat_value_out[0] (signal_sdc_dat_value_from_card[0]); |
---|
| 1293 | card->p_sdc_dat_value_out[1] (signal_sdc_dat_value_from_card[1]); |
---|
| 1294 | card->p_sdc_dat_value_out[2] (signal_sdc_dat_value_from_card[2]); |
---|
| 1295 | card->p_sdc_dat_value_out[3] (signal_sdc_dat_value_from_card[3]); |
---|
| 1296 | card->p_sdc_dat_enable_in (signal_sdc_dat_enable_to_card); |
---|
| 1297 | card->p_sdc_dat_value_in[0] (signal_sdc_dat_value_to_card[0]); |
---|
| 1298 | card->p_sdc_dat_value_in[1] (signal_sdc_dat_value_to_card[1]); |
---|
| 1299 | card->p_sdc_dat_value_in[2] (signal_sdc_dat_value_to_card[2]); |
---|
| 1300 | card->p_sdc_dat_value_in[3] (signal_sdc_dat_value_to_card[3]); |
---|
| 1301 | |
---|
[965] | 1302 | #endif |
---|
[450] | 1303 | |
---|
[965] | 1304 | std::cout << " - DISK connected" << std::endl; |
---|
[450] | 1305 | |
---|
| 1306 | // FBUF connexion |
---|
[550] | 1307 | fbuf->p_clk (signal_clk); |
---|
| 1308 | fbuf->p_resetn (signal_resetn); |
---|
| 1309 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 1310 | |
---|
| 1311 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1312 | |
---|
| 1313 | // MNIC connexion |
---|
[550] | 1314 | mnic->p_clk (signal_clk); |
---|
| 1315 | mnic->p_resetn (signal_resetn); |
---|
[1050] | 1316 | mnic->p_vci_tgt (signal_vci_tgt_mnic); |
---|
| 1317 | mnic->p_vci_ini (signal_vci_ini_mnic); |
---|
[450] | 1318 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1319 | { |
---|
[550] | 1320 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1321 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
[450] | 1322 | } |
---|
| 1323 | |
---|
| 1324 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1325 | |
---|
| 1326 | // BROM connexion |
---|
[550] | 1327 | brom->p_clk (signal_clk); |
---|
| 1328 | brom->p_resetn (signal_resetn); |
---|
| 1329 | brom->p_vci (signal_vci_tgt_brom); |
---|
[450] | 1330 | |
---|
| 1331 | std::cout << " - BROM connected" << std::endl; |
---|
| 1332 | |
---|
| 1333 | // MTTY connexion |
---|
[550] | 1334 | mtty->p_clk (signal_clk); |
---|
| 1335 | mtty->p_resetn (signal_resetn); |
---|
| 1336 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
[1050] | 1337 | for ( size_t i=0 ; i<NB_TXT_CHANNELS ; i++ ) |
---|
[874] | 1338 | { |
---|
[1053] | 1339 | mtty->p_irq_rx[i] (signal_irq_mtty_rx[i]); |
---|
| 1340 | mtty->p_irq_tx[i] (signal_irq_mtty_tx[i]); |
---|
[874] | 1341 | } |
---|
[450] | 1342 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1343 | |
---|
[707] | 1344 | // IOPI connexion |
---|
[718] | 1345 | iopi->p_clk (signal_clk); |
---|
| 1346 | iopi->p_resetn (signal_resetn); |
---|
| 1347 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1348 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
[707] | 1349 | for ( size_t i=0 ; i<32 ; i++) |
---|
[450] | 1350 | { |
---|
[707] | 1351 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1352 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
[1050] | 1353 | else if(i < 4+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-4]); |
---|
| 1354 | else if(i < 12) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1355 | else if(i < 13) iopi->p_hwi[i] (signal_irq_disk); |
---|
[874] | 1356 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
[1050] | 1357 | else if(i < 16+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
[1053] | 1358 | else if(i < 24) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1359 | else if(i < 24+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_tx[i-24]); |
---|
[707] | 1360 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1361 | } |
---|
[584] | 1362 | |
---|
[707] | 1363 | std::cout << " - IOPIC connected" << std::endl; |
---|
[584] | 1364 | |
---|
[718] | 1365 | |
---|
[707] | 1366 | // IOB0 cluster connexion to IOX network |
---|
[718] | 1367 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1368 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[584] | 1369 | |
---|
[718] | 1370 | // IOB1 cluster connexion to IOX network |
---|
[707] | 1371 | // (only when there is more than 1 cluster) |
---|
| 1372 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1373 | { |
---|
| 1374 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1375 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[450] | 1376 | } |
---|
| 1377 | |
---|
| 1378 | // All clusters Clock & RESET connexions |
---|
| 1379 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
| 1380 | { |
---|
| 1381 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1382 | { |
---|
| 1383 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1384 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1385 | } |
---|
| 1386 | } |
---|
| 1387 | |
---|
| 1388 | // Inter Clusters horizontal connections |
---|
| 1389 | if (XMAX > 1) |
---|
| 1390 | { |
---|
| 1391 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
| 1392 | { |
---|
| 1393 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1394 | { |
---|
[1002] | 1395 | clusters[x][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
| 1396 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
| 1397 | clusters[x][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
| 1398 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
[468] | 1399 | |
---|
[1002] | 1400 | clusters[x][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
| 1401 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
| 1402 | clusters[x][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
| 1403 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
[450] | 1404 | |
---|
[1002] | 1405 | clusters[x][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
| 1406 | clusters[x+1][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
| 1407 | clusters[x][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
| 1408 | clusters[x+1][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
| 1409 | |
---|
| 1410 | clusters[x][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
| 1411 | clusters[x+1][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
| 1412 | clusters[x][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
| 1413 | clusters[x+1][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
| 1414 | |
---|
| 1415 | clusters[x][y]->p_dspin_int_cla_out[EAST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
| 1416 | clusters[x+1][y]->p_dspin_int_cla_in[WEST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
| 1417 | clusters[x][y]->p_dspin_int_cla_in[EAST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
| 1418 | clusters[x+1][y]->p_dspin_int_cla_out[WEST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
| 1419 | |
---|
[450] | 1420 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1421 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1422 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1423 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
[1002] | 1424 | |
---|
[450] | 1425 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1426 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1427 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1428 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1429 | } |
---|
| 1430 | } |
---|
| 1431 | } |
---|
| 1432 | |
---|
[718] | 1433 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
[450] | 1434 | |
---|
| 1435 | // Inter Clusters vertical connections |
---|
[718] | 1436 | if (YMAX > 1) |
---|
[450] | 1437 | { |
---|
| 1438 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
| 1439 | { |
---|
| 1440 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1441 | { |
---|
[1002] | 1442 | clusters[x][y]->p_dspin_int_cmd_out[NORTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
| 1443 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
| 1444 | clusters[x][y]->p_dspin_int_cmd_in[NORTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
| 1445 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
[468] | 1446 | |
---|
[1002] | 1447 | clusters[x][y]->p_dspin_int_rsp_out[NORTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
| 1448 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
| 1449 | clusters[x][y]->p_dspin_int_rsp_in[NORTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
| 1450 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
[450] | 1451 | |
---|
[1002] | 1452 | clusters[x][y]->p_dspin_int_m2p_out[NORTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
| 1453 | clusters[x][y+1]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
| 1454 | clusters[x][y]->p_dspin_int_m2p_in[NORTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
| 1455 | clusters[x][y+1]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
| 1456 | |
---|
| 1457 | clusters[x][y]->p_dspin_int_p2m_out[NORTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
| 1458 | clusters[x][y+1]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
| 1459 | clusters[x][y]->p_dspin_int_p2m_in[NORTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
| 1460 | clusters[x][y+1]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
| 1461 | |
---|
| 1462 | clusters[x][y]->p_dspin_int_cla_out[NORTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
| 1463 | clusters[x][y+1]->p_dspin_int_cla_in[SOUTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
| 1464 | clusters[x][y]->p_dspin_int_cla_in[NORTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
| 1465 | clusters[x][y+1]->p_dspin_int_cla_out[SOUTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
| 1466 | |
---|
[450] | 1467 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1468 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1469 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1470 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
[1002] | 1471 | |
---|
[450] | 1472 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1473 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1474 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1475 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1476 | } |
---|
| 1477 | } |
---|
| 1478 | } |
---|
| 1479 | |
---|
| 1480 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1481 | |
---|
| 1482 | // East & West boundary cluster connections |
---|
| 1483 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1484 | { |
---|
[1002] | 1485 | clusters[0][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_false_int_cmd_in[0][y][WEST]); |
---|
| 1486 | clusters[0][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_false_int_cmd_out[0][y][WEST]); |
---|
| 1487 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST]); |
---|
| 1488 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST]); |
---|
[468] | 1489 | |
---|
[1002] | 1490 | clusters[0][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_false_int_rsp_in[0][y][WEST]); |
---|
| 1491 | clusters[0][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_false_int_rsp_out[0][y][WEST]); |
---|
| 1492 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST]); |
---|
| 1493 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST]); |
---|
[450] | 1494 | |
---|
[1002] | 1495 | clusters[0][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_false_int_m2p_in[0][y][WEST]); |
---|
| 1496 | clusters[0][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_false_int_m2p_out[0][y][WEST]); |
---|
| 1497 | clusters[XMAX-1][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_false_int_m2p_in[XMAX-1][y][EAST]); |
---|
| 1498 | clusters[XMAX-1][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_false_int_m2p_out[XMAX-1][y][EAST]); |
---|
[450] | 1499 | |
---|
[1002] | 1500 | clusters[0][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_false_int_p2m_in[0][y][WEST]); |
---|
| 1501 | clusters[0][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_false_int_p2m_out[0][y][WEST]); |
---|
| 1502 | clusters[XMAX-1][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_false_int_p2m_in[XMAX-1][y][EAST]); |
---|
| 1503 | clusters[XMAX-1][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_false_int_p2m_out[XMAX-1][y][EAST]); |
---|
| 1504 | |
---|
| 1505 | clusters[0][y]->p_dspin_int_cla_in[WEST] (signal_dspin_false_int_cla_in[0][y][WEST]); |
---|
| 1506 | clusters[0][y]->p_dspin_int_cla_out[WEST] (signal_dspin_false_int_cla_out[0][y][WEST]); |
---|
| 1507 | clusters[XMAX-1][y]->p_dspin_int_cla_in[EAST] (signal_dspin_false_int_cla_in[XMAX-1][y][EAST]); |
---|
| 1508 | clusters[XMAX-1][y]->p_dspin_int_cla_out[EAST] (signal_dspin_false_int_cla_out[XMAX-1][y][EAST]); |
---|
| 1509 | |
---|
| 1510 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1511 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1512 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
| 1513 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
| 1514 | |
---|
| 1515 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1516 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
| 1517 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
| 1518 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
[450] | 1519 | } |
---|
| 1520 | |
---|
| 1521 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1522 | |
---|
| 1523 | // North & South boundary clusters connections |
---|
| 1524 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1525 | { |
---|
[1002] | 1526 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_false_int_cmd_in[x][0][SOUTH]); |
---|
| 1527 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_false_int_cmd_out[x][0][SOUTH]); |
---|
| 1528 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH]); |
---|
| 1529 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH]); |
---|
[468] | 1530 | |
---|
[1002] | 1531 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_false_int_rsp_in[x][0][SOUTH]); |
---|
| 1532 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_false_int_rsp_out[x][0][SOUTH]); |
---|
| 1533 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH]); |
---|
| 1534 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH]); |
---|
[450] | 1535 | |
---|
[1002] | 1536 | clusters[x][0]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_false_int_m2p_in[x][0][SOUTH]); |
---|
| 1537 | clusters[x][0]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_false_int_m2p_out[x][0][SOUTH]); |
---|
| 1538 | clusters[x][YMAX-1]->p_dspin_int_m2p_in[NORTH] (signal_dspin_false_int_m2p_in[x][YMAX-1][NORTH]); |
---|
| 1539 | clusters[x][YMAX-1]->p_dspin_int_m2p_out[NORTH] (signal_dspin_false_int_m2p_out[x][YMAX-1][NORTH]); |
---|
[450] | 1540 | |
---|
[1002] | 1541 | clusters[x][0]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_false_int_p2m_in[x][0][SOUTH]); |
---|
| 1542 | clusters[x][0]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_false_int_p2m_out[x][0][SOUTH]); |
---|
| 1543 | clusters[x][YMAX-1]->p_dspin_int_p2m_in[NORTH] (signal_dspin_false_int_p2m_in[x][YMAX-1][NORTH]); |
---|
| 1544 | clusters[x][YMAX-1]->p_dspin_int_p2m_out[NORTH] (signal_dspin_false_int_p2m_out[x][YMAX-1][NORTH]); |
---|
| 1545 | |
---|
| 1546 | clusters[x][0]->p_dspin_int_cla_in[SOUTH] (signal_dspin_false_int_cla_in[x][0][SOUTH]); |
---|
| 1547 | clusters[x][0]->p_dspin_int_cla_out[SOUTH] (signal_dspin_false_int_cla_out[x][0][SOUTH]); |
---|
| 1548 | clusters[x][YMAX-1]->p_dspin_int_cla_in[NORTH] (signal_dspin_false_int_cla_in[x][YMAX-1][NORTH]); |
---|
| 1549 | clusters[x][YMAX-1]->p_dspin_int_cla_out[NORTH] (signal_dspin_false_int_cla_out[x][YMAX-1][NORTH]); |
---|
| 1550 | |
---|
| 1551 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1552 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1553 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
| 1554 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
| 1555 | |
---|
| 1556 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1557 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
| 1558 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
| 1559 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
[450] | 1560 | } |
---|
| 1561 | |
---|
[550] | 1562 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
[450] | 1563 | |
---|
| 1564 | //////////////////////////////////////////////////////// |
---|
| 1565 | // Simulation |
---|
| 1566 | /////////////////////////////////////////////////////// |
---|
| 1567 | |
---|
| 1568 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
[584] | 1569 | |
---|
[450] | 1570 | signal_resetn = false; |
---|
[584] | 1571 | signal_irq_false = false; |
---|
| 1572 | |
---|
[450] | 1573 | // network boundaries signals |
---|
| 1574 | for (size_t x = 0; x < XMAX ; x++) |
---|
| 1575 | { |
---|
| 1576 | for (size_t y = 0; y < YMAX ; y++) |
---|
| 1577 | { |
---|
| 1578 | for (size_t a = 0; a < 4; a++) |
---|
| 1579 | { |
---|
[1002] | 1580 | signal_dspin_false_int_cmd_in[x][y][a].write = false; |
---|
| 1581 | signal_dspin_false_int_cmd_in[x][y][a].read = true; |
---|
| 1582 | signal_dspin_false_int_cmd_out[x][y][a].write = false; |
---|
| 1583 | signal_dspin_false_int_cmd_out[x][y][a].read = true; |
---|
[468] | 1584 | |
---|
[1002] | 1585 | signal_dspin_false_int_rsp_in[x][y][a].write = false; |
---|
| 1586 | signal_dspin_false_int_rsp_in[x][y][a].read = true; |
---|
| 1587 | signal_dspin_false_int_rsp_out[x][y][a].write = false; |
---|
| 1588 | signal_dspin_false_int_rsp_out[x][y][a].read = true; |
---|
[450] | 1589 | |
---|
[1002] | 1590 | signal_dspin_false_int_m2p_in[x][y][a].write = false; |
---|
| 1591 | signal_dspin_false_int_m2p_in[x][y][a].read = true; |
---|
| 1592 | signal_dspin_false_int_m2p_out[x][y][a].write = false; |
---|
| 1593 | signal_dspin_false_int_m2p_out[x][y][a].read = true; |
---|
| 1594 | |
---|
| 1595 | signal_dspin_false_int_p2m_in[x][y][a].write = false; |
---|
| 1596 | signal_dspin_false_int_p2m_in[x][y][a].read = true; |
---|
| 1597 | signal_dspin_false_int_p2m_out[x][y][a].write = false; |
---|
| 1598 | signal_dspin_false_int_p2m_out[x][y][a].read = true; |
---|
| 1599 | |
---|
| 1600 | signal_dspin_false_int_cla_in[x][y][a].write = false; |
---|
| 1601 | signal_dspin_false_int_cla_in[x][y][a].read = true; |
---|
| 1602 | signal_dspin_false_int_cla_out[x][y][a].write = false; |
---|
| 1603 | signal_dspin_false_int_cla_out[x][y][a].read = true; |
---|
| 1604 | |
---|
[450] | 1605 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1606 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
| 1607 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
| 1608 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
| 1609 | |
---|
| 1610 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1611 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
| 1612 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
| 1613 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
| 1614 | } |
---|
| 1615 | } |
---|
| 1616 | } |
---|
| 1617 | |
---|
[550] | 1618 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1619 | signal_resetn = true; |
---|
[450] | 1620 | |
---|
[707] | 1621 | |
---|
| 1622 | // simulation loop |
---|
[693] | 1623 | struct timeval t1,t2; |
---|
| 1624 | gettimeofday(&t1, NULL); |
---|
[707] | 1625 | |
---|
[762] | 1626 | |
---|
| 1627 | for ( size_t n = 0; n < ncycles ; n += simul_period ) |
---|
[550] | 1628 | { |
---|
[693] | 1629 | // stats display |
---|
[714] | 1630 | if( (n % 1000000) == 0) |
---|
[693] | 1631 | { |
---|
| 1632 | gettimeofday(&t2, NULL); |
---|
| 1633 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
| 1634 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1635 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
| 1636 | (uint64_t) t2.tv_usec / 1000; |
---|
[817] | 1637 | std::cerr << "### cycle = " << std::dec << n |
---|
[718] | 1638 | << " / frequency = " |
---|
| 1639 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
---|
[693] | 1640 | << std::endl; |
---|
| 1641 | |
---|
| 1642 | gettimeofday(&t1, NULL); |
---|
[1044] | 1643 | |
---|
| 1644 | // loop on all processors to display FROZEN stats |
---|
| 1645 | for ( size_t x = 0 ; x < XMAX ; x++ ) |
---|
| 1646 | { |
---|
| 1647 | for ( size_t y = 0 ; y < YMAX ; y++ ) |
---|
| 1648 | { |
---|
| 1649 | for ( size_t l = 0 ; l < NB_PROCS_MAX ; l++ ) |
---|
| 1650 | { |
---|
| 1651 | clusters[x][y]->proc[l]->print_frozen_stats(); |
---|
| 1652 | } |
---|
| 1653 | } |
---|
| 1654 | } |
---|
[693] | 1655 | } |
---|
| 1656 | |
---|
[607] | 1657 | // Monitor a specific address for one L1 cache |
---|
[1053] | 1658 | // clusters[0][0]->proc[0]->cache_monitor( 0x00032D74ULL ); |
---|
[450] | 1659 | |
---|
[1055] | 1660 | // Monitor a specific address for L2 cache (single word if second argument true) |
---|
[1056] | 1661 | clusters[0][0]->memc->cache_monitor( 0xdbc7cULL , true ); |
---|
[607] | 1662 | |
---|
| 1663 | // Monitor a specific address for one XRAM |
---|
[1053] | 1664 | // clusters[0][0]->xram->start_monitor( 0x0008A000ULL , 64); |
---|
[607] | 1665 | |
---|
[764] | 1666 | if ( debug_ok and (n > debug_from) ) |
---|
[450] | 1667 | { |
---|
[550] | 1668 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1669 | std::cout << " ************************************************" << std::endl; |
---|
[718] | 1670 | // trace proc[debug_proc_id] |
---|
[607] | 1671 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
[550] | 1672 | { |
---|
[1055] | 1673 | // processor debug modes |
---|
| 1674 | // 0x01 : write buffer trace |
---|
| 1675 | // 0x02 : dump processor registers |
---|
| 1676 | // 0x04 : dcache trace |
---|
| 1677 | // 0x08 : icache trace |
---|
| 1678 | // 0x10 : dtlb trace |
---|
| 1679 | // 0x20 : itlb trace |
---|
| 1680 | // 0x40 : SR |
---|
[802] | 1681 | size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; |
---|
| 1682 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
[607] | 1683 | size_t x = cluster_xy >> 4; |
---|
| 1684 | size_t y = cluster_xy & 0xF; |
---|
[1053] | 1685 | /* |
---|
| 1686 | size_t l = 0; |
---|
| 1687 | size_t x = 0; |
---|
| 1688 | size_t y; |
---|
| 1689 | |
---|
| 1690 | for( y = 0 ; y < 2 ; y++ ) |
---|
| 1691 | { |
---|
| 1692 | */ |
---|
[1055] | 1693 | clusters[x][y]->proc[l]->print_trace(0x42); |
---|
[550] | 1694 | std::ostringstream proc_signame; |
---|
| 1695 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1696 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
[450] | 1697 | |
---|
[1051] | 1698 | // XICU |
---|
[959] | 1699 | clusters[x][y]->xicu->print_trace(1); |
---|
| 1700 | std::ostringstream xicu_signame; |
---|
| 1701 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1702 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
[584] | 1703 | |
---|
[1051] | 1704 | // MDMA |
---|
| 1705 | // clusters[x][y]->mdma->print_trace(); |
---|
| 1706 | // std::ostringstream mdma_tgt_signame; |
---|
| 1707 | // mdma_tgt_signame << "[SIG]MDMA_TGT_" << x << "_" << y; |
---|
| 1708 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_tgt_signame.str()); |
---|
| 1709 | // std::ostringstream mdma_ini_signame; |
---|
| 1710 | // mdma_ini_signame << "[SIG]MDMA_INI_" << x << "_" << y; |
---|
| 1711 | // clusters[x][y]->signal_int_vci_ini_mdma.print_trace(mdma_ini_signame.str()); |
---|
[714] | 1712 | |
---|
[739] | 1713 | // local interrupts in cluster(x,y) |
---|
| 1714 | if( clusters[x][y]->signal_irq_memc.read() ) |
---|
[802] | 1715 | std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y |
---|
[739] | 1716 | << " ACTIVE" << std::endl; |
---|
| 1717 | |
---|
[1051] | 1718 | for( size_t i = 0 ; i < NB_PROCS_MAX ; i++ ) |
---|
[739] | 1719 | { |
---|
[1051] | 1720 | if( clusters[x][y]->signal_irq_mdma[i].read() ) |
---|
| 1721 | std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << i |
---|
[739] | 1722 | << " ACTIVE" << std::endl; |
---|
[1051] | 1723 | |
---|
| 1724 | if( clusters[x][y]->signal_proc_it[i<<2].read() ) |
---|
| 1725 | std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << i |
---|
| 1726 | << " ACTIVE" << std::endl; |
---|
[739] | 1727 | } |
---|
[718] | 1728 | } |
---|
[450] | 1729 | |
---|
[718] | 1730 | // trace memc[debug_memc_id] |
---|
[607] | 1731 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
[550] | 1732 | { |
---|
[607] | 1733 | size_t x = debug_memc_id >> 4; |
---|
| 1734 | size_t y = debug_memc_id & 0xF; |
---|
[718] | 1735 | |
---|
[550] | 1736 | clusters[x][y]->memc->print_trace(0); |
---|
| 1737 | std::ostringstream smemc_tgt; |
---|
| 1738 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1739 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
| 1740 | std::ostringstream smemc_ini; |
---|
| 1741 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1742 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
[707] | 1743 | |
---|
[550] | 1744 | clusters[x][y]->xram->print_trace(); |
---|
| 1745 | std::ostringstream sxram_tgt; |
---|
| 1746 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1747 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
[450] | 1748 | |
---|
[1030] | 1749 | // clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1750 | // clusters[x][y]->ram_router_rsp->print_trace(); |
---|
[1050] | 1751 | |
---|
| 1752 | // clusters[x][y]->ram_xbar_cmd->print_trace(); |
---|
| 1753 | // clusters[x][y]->ram_xbar_rsp->print_trace(); |
---|
[707] | 1754 | } |
---|
[718] | 1755 | |
---|
| 1756 | // trace iob, iox and external peripherals |
---|
[550] | 1757 | if ( debug_iob ) |
---|
| 1758 | { |
---|
[914] | 1759 | // clusters[0][0]->iob->print_trace(); |
---|
[718] | 1760 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
| 1761 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
| 1762 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
[730] | 1763 | // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1764 | // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[450] | 1765 | |
---|
[710] | 1766 | // brom->print_trace(); |
---|
[914] | 1767 | // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); |
---|
[450] | 1768 | |
---|
[1053] | 1769 | mtty->print_trace( 1 ); |
---|
| 1770 | signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); |
---|
[450] | 1771 | |
---|
[1018] | 1772 | // disk->print_trace(); |
---|
| 1773 | // signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); |
---|
| 1774 | // signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); |
---|
[450] | 1775 | |
---|
[1002] | 1776 | #if ( USE_IOC_SDC ) |
---|
[1018] | 1777 | // card->print_trace(); |
---|
[1002] | 1778 | #endif |
---|
[714] | 1779 | |
---|
[1053] | 1780 | // mnic->print_trace( 0 ); |
---|
| 1781 | // signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
| 1782 | // signal_vci_ini_mnic.print_trace("[SIG]MNIC_INI"); |
---|
[1002] | 1783 | |
---|
[1050] | 1784 | // fbuf->print_trace(); |
---|
| 1785 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); |
---|
[498] | 1786 | |
---|
[1053] | 1787 | iopi->print_trace(); |
---|
| 1788 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
| 1789 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
[965] | 1790 | |
---|
[874] | 1791 | // iox_network->print_trace(); |
---|
[450] | 1792 | |
---|
[550] | 1793 | // interrupts |
---|
[1002] | 1794 | if ( signal_irq_disk.read() ) |
---|
| 1795 | std::cout << "### IRQ_DISK ACTIVE" << std::endl; |
---|
| 1796 | |
---|
[1053] | 1797 | for( size_t k = 0 ; k < NB_TXT_CHANNELS ; k++ ) |
---|
| 1798 | { |
---|
| 1799 | if ( signal_irq_mtty_rx[k].read() ) |
---|
| 1800 | std::cout << "### IRQ_MTTY_RX[" << k << "] ACTIVE" << std::endl; |
---|
[1002] | 1801 | |
---|
[1053] | 1802 | if ( signal_irq_mtty_tx[k].read() ) |
---|
| 1803 | std::cout << "### IRQ_MTTY_TX[" << k << "] ACTIVE" << std::endl; |
---|
| 1804 | } |
---|
[1002] | 1805 | |
---|
[1053] | 1806 | for( size_t k = 0 ; k < NB_NIC_CHANNELS ; k++ ) |
---|
| 1807 | { |
---|
| 1808 | if ( signal_irq_mnic_rx[k].read() ) |
---|
| 1809 | std::cout << "### IRQ_MNIC_RX[" << k << "] ACTIVE" << std::endl; |
---|
| 1810 | |
---|
| 1811 | if ( signal_irq_mnic_tx[k].read() ) |
---|
| 1812 | std::cout << "### IRQ_MNIC_TX[" << k << "] ACTIVE" << std::endl; |
---|
| 1813 | } |
---|
[550] | 1814 | } |
---|
| 1815 | } |
---|
[450] | 1816 | |
---|
[762] | 1817 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
[550] | 1818 | } |
---|
| 1819 | return EXIT_SUCCESS; |
---|
[450] | 1820 | } |
---|
| 1821 | |
---|
| 1822 | int sc_main (int argc, char *argv[]) |
---|
| 1823 | { |
---|
| 1824 | try { |
---|
| 1825 | return _main(argc, argv); |
---|
| 1826 | } catch (std::exception &e) { |
---|
| 1827 | std::cout << e.what() << std::endl; |
---|
| 1828 | } catch (...) { |
---|
| 1829 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1830 | throw; |
---|
| 1831 | } |
---|
| 1832 | return 1; |
---|
| 1833 | } |
---|
| 1834 | |
---|
| 1835 | |
---|
| 1836 | // Local Variables: |
---|
| 1837 | // tab-width: 3 |
---|
| 1838 | // c-basic-offset: 3 |
---|
| 1839 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1840 | // indent-tabs-mode: nil |
---|
| 1841 | // End: |
---|
| 1842 | |
---|
| 1843 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1844 | |
---|
| 1845 | |
---|
| 1846 | |
---|