[16] | 1 | % les objectifs globaux, |
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[89] | 2 | The market of digital systems is about 4,600 M\$ today and is estimated to |
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[68] | 3 | 5,600 M\$ in 2012. However the ever growing applications complexity involves |
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[97] | 4 | integration of heterogeneous technologies and requires the design of |
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[49] | 5 | complex Multi-Processors System on Chip (MPSoC). |
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[99] | 6 | \\ |
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[97] | 7 | During the last decade, the design of ASICs (Application Specific |
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[49] | 8 | Integrated Circuits) appeared to be more and more reserved to high volume markets, because |
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| 9 | the design and fabrication costs of such components exploded, due to increasing NRE (Non |
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| 10 | Recurring-Engineering) costs. |
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[97] | 11 | Fortunately, FPGA (Field Programmable Gate Array) components, such as the |
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[49] | 12 | Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays |
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[97] | 13 | implement a complete MPSoC with multiple processors and several dedicated |
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[281] | 14 | coprocessors for a few Keuros per device. |
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| 15 | \\ |
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| 16 | Many applications are initially captured |
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[234] | 17 | algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest |
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[165] | 18 | in tools that can provide an implementation path directly from HLLs to hardware. |
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| 19 | Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, |
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[49] | 20 | Co-design, High-Level Synthesis...) are now mature and allow the automation of |
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[165] | 21 | a system-level design flow. Unfortunately, ESL tool development to date has primarily focused |
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| 22 | on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). |
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| 23 | However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design |
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| 24 | methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting |
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| 25 | designs written in C/C++ language and implementing the function straight into FPGA. |
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[49] | 26 | We believe that coupling FPGA technologies and ESL methodologies |
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[281] | 27 | will allow both SMEs (Small and Medium Enterprise) and major companies to design innovative |
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| 28 | devices and to enter new, low and medium volume markets. |
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| 29 | \begin{ADDEDENV} |
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| 30 | Furthermore, today there is an increasing industrial interest to IC |
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| 31 | that integrates both hardwired CPU cores or MPSoC and a configurable area (FPGA) |
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| 32 | such as ATOM E600C (Intel). |
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| 33 | Probably in few years, one can expect that such chips will become current and even standard |
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| 34 | general purpose CPU cores will contains a configurable area making explode the low and medium volume |
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| 35 | markets of digital systems. |
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| 36 | \end{ADDEDENV} |
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[99] | 37 | \parlf |
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[281] | 38 | \begin{SUPPRESSEDENV} |
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[49] | 39 | The objective of COACH is to provide an integrated design flow, based on the |
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| 40 | SoCLib infrastructure~\cite{soclib}, and optimized for the design of |
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[97] | 41 | multi-processors digital systems targeting FPGA devices. |
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[281] | 42 | The digital systems are generally integrated into one or several chips, and there are two types of applications: |
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[97] | 43 | They can be embedded (autonomous) applications |
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[281] | 44 | such as personal digital assistants (PDA), ambient computing components, |
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[165] | 45 | or wireless sensor networks (WSN). |
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[49] | 46 | They can also be extension boards connected to a PC to accelerate a specific computation, |
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| 47 | as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). |
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[281] | 48 | \end{SUPPRESSEDENV}\begin{ADDEDENV} |
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| 49 | The objective of COACH is to provide an integrated design flow for the design of |
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| 50 | multi-processors digital systems targeting FPGA devices. |
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| 51 | It will be dedicated to system/software designers, and hide as much as possible |
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| 52 | the hardware characteristics to the end-user. |
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| 53 | COACH will mainly target three kinds of digital systems: |
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| 54 | 1) embedded and autonomous application such as personal digital assistants (PDA), |
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| 55 | ambient computing components, or wireless sensor networks (WSN); |
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| 56 | 2) PCI/E extension boards connected to a PC to accelerate a specific application, |
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| 57 | it is the domain of High-Performance Computing (HPC) and High-Speed Signal Processing (HSSP); |
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| 58 | 3) sub-system application for generating an IP to a larger system. |
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| 59 | \end{ADDEDENV} |
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[99] | 60 | \parlf |
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[25] | 61 | %verrous scientifiques et techniques |
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[97] | 62 | The COACH environment will integrate several hardware and software technologies: |
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[49] | 63 | \begin{description} |
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[100] | 64 | \item[Design Space Exploration:] |
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[250] | 65 | The COACH environment will allow to describe an application as a process |
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| 66 | network i.e. a set of tasks communicating through FIFO channels. |
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| 67 | COACH will allow to map the application on a shared-memory, MPSoC architecture. |
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| 68 | It will permit to easily explore the design space to help the system designer |
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| 69 | to define the proper hardware/software partitioning of the application. |
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[49] | 70 | For each point in the design space, metrics such as throughput, latency, power |
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| 71 | consumption, silicon area, memory allocation and data locality will be provided. |
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[281] | 72 | \begin{SUPPRESSEDENV} |
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[49] | 73 | These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure |
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| 74 | and high-level estimation methodologies. |
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[281] | 75 | \end{SUPPRESSEDENV} |
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[100] | 76 | \item[Hardware Accelerators Synthesis (HAS):] |
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[49] | 77 | COACH will allow the automatic generation of hardware accelerators when required. |
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| 78 | Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor |
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| 79 | (ASIP) design environment and source-level transformation tools (loop transformations |
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[281] | 80 | and memory optimization) will be provided. |
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[49] | 81 | This will allow further exploration of the micro-architectural design space. |
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| 82 | HLS tools are sensitive to the coding style of the input specification and the domain |
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| 83 | they target (control vs. data dominated). |
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| 84 | The HLS tools of COACH will support a common language and coding style to avoid |
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| 85 | re-engineering by the designer. |
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[100] | 86 | \item[Platform based design:] |
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[52] | 87 | COACH will handle both \altera and \xilinx FPGA devices. |
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[49] | 88 | COACH will define architectural templates that can be customized by adding |
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| 89 | dedicated coprocessors and ASIPs and by fixing template parameters such as |
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[165] | 90 | the number of embedded processors, the number of sizes of embedded memory banks |
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[281] | 91 | or the embedded operating system. |
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| 92 | However, the specification of the application will be independent of both the |
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[165] | 93 | architectural template and the target FPGA device. |
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[234] | 94 | Basically, the following three architectural templates will be provided: |
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[49] | 95 | \begin{enumerate} |
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[246] | 96 | \item A Neutral architectural template based on the SoCLib IP core library and the |
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[49] | 97 | VCI/OCP communication infrastructure. |
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[165] | 98 | \item An \altera architectural template based on the \altera IP core library, the |
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| 99 | AVALON system bus and the NIOS processor. |
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[281] | 100 | \item A \xilinx architectural template based on the \xilinx IP core library, the PLB |
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[165] | 101 | system bus and the Microblaze processor. |
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[49] | 102 | \end{enumerate} |
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[100] | 103 | \item[Hardware/Software communication middleware:] |
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[134] | 104 | COACH will implement an homogeneous HW/SW communication infrastructure and |
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[97] | 105 | communication APIs (Application Programming Interface), that will be used for |
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| 106 | communications between software tasks running on embedded processors and |
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[165] | 107 | dedicated hardware coprocessors. |
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[281] | 108 | \begin{ADDEDENV} |
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| 109 | \item[Interaction with the industrial world] |
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| 110 | COACH will not be a closed framework but it will be opened to the industrial |
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| 111 | world by using the IP-XACT format \ref{IP-XACT-08} for describing the components of the |
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| 112 | architectural template and by providing the IP-XACT description of the generated MPSoC. |
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| 113 | This should facilitate the enhancement of the architectural template with IP and the |
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| 114 | integration of the IP produced by COACH in larger design. |
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| 115 | \end{ADDEDENV} |
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[49] | 116 | \end{description} |
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[281] | 117 | \begin{SUPPRESSEDENV} |
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| 118 | MOVED ABOVE |
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[49] | 119 | The COACH design flow will be dedicated to system designers, and will as |
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[165] | 120 | much as possible hide the hardware characteristics to the end-user. |
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[281] | 121 | \end{SUPPRESSEDENV} |
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[49] | 122 | %From the end user point of view, the specification of the application will be |
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| 123 | %independant from both the architectural template and from the selected FPGA |
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| 124 | %family. |
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[99] | 125 | \parlf |
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[16] | 126 | % le programme de travail |
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[49] | 127 | %The COACH project targets fundamental issues related to design methodologies for |
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| 128 | %digital systems by providing estimation, exploration and design tools targeting both |
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| 129 | %performance and power optimization at all the abstraction levels of the flow (system, |
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| 130 | %architecture, algorithm and logic). |
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| 131 | To reach this ambitious goal, the project will rely on the experience and the |
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| 132 | complementariness of partners in the following domains: |
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| 133 | Operating system and communication middleware (\tima, \upmc), |
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| 134 | MPSoC architectures (\tima, \ubs, \upmc), |
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| 135 | ASIP architectures (\irisa), |
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[281] | 136 | High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip), |
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| 137 | HPC (\bull, \thales), \mustbecompleted{XXX (\mds)}. |
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[49] | 138 | \\ |
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| 139 | The COACH project does not start from scratch. |
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[281] | 140 | \begin{SUPPRESSEDENV} |
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| 141 | It strongly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, |
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| 142 | (DSX, component library), operating systems (MUTEKH, DNA/OS). |
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[49] | 143 | It also leverages on several existing technologies: |
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| 144 | on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, |
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| 145 | on the ROMA~\cite{roma} project for ASIP, |
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[87] | 146 | on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations |
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[49] | 147 | and on the \xilinx and \altera IP core libraries. |
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[281] | 148 | \end{SUPPRESSEDENV}\begin{ADDEDENV} |
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| 149 | It relies |
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| 150 | on the SoCLib platform~\cite{soclib} for prototyping and operating systems (DNA/OS), |
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| 151 | on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, |
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| 152 | on the ROMA~\cite{roma} project for ASIP, |
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| 153 | on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and |
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| 154 | transformations, |
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| 155 | on the \mustbecompleted{XXXX:magillem} for \mustbecompleted{XXXX:magillem}, |
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| 156 | and on the \xilinx and \altera IP core libraries. |
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| 157 | \end{ADDEDENV} |
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| 158 | Finally it will use the \xilinx and \altera logic and physical synthesis tools |
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| 159 | to generate the FPGA configuration bitstreams. |
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[99] | 160 | \parlf |
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[49] | 161 | The COACH proposal has been prepared during one year by a technical working group |
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[97] | 162 | involving the 5 academic partners (one monthly meeting from january 2009 to february |
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| 163 | 2010). The objective was to analyse the issues of integrating |
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[281] | 164 | and enhancing the existing tools and technologies into a unique framework. |
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[97] | 165 | Most of the general software architecture of the proposed design flow (including the |
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| 166 | exchange format specification) has been define by this working group. |
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[281] | 167 | \SUPPRESSED{Because the COACH project leanes on the ANR SoCLib platform, it may be |
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| 168 | described as an extension of the SoCLib platform.} |
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[97] | 169 | %The main development steps of the COACH project are: |
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| 170 | %\begin{enumerate} |
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| 171 | % \item Definition of the end user inputs: |
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| 172 | % The coarse grain parallelism of the application will be described as a communicating |
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| 173 | % task graph, each task being described in C language. |
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| 174 | % Similarly the architectural templates with their parameters and the design constraints |
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| 175 | % will be specified. |
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| 176 | % \item Definition of an internal format for representing task. |
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| 177 | % \item Development of the GCC pluggin for generating the internal format of a |
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| 178 | % C task. |
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| 179 | % \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write |
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| 180 | % the internal format. This will allow to swap from one tool to another one, and to |
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| 181 | % chain them if necessary. |
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| 182 | % \item Modification of the DSX tool (Design Space eXplorer) of the SocLib |
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| 183 | % platform to generate the bitstream for the various FPGA families and architectural |
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| 184 | % templates. |
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| 185 | % \item Development of new tools such as ASIP compiler, HPC design environment and |
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| 186 | % dynamic reconfiguration of FPGA devices. |
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| 187 | %\end{enumerate} |
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[99] | 188 | \parlf |
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[263] | 189 | Two major FPGA companies are involved in the project: \xilinx will contribute |
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| 190 | as a contractual partner providing documentation and manpower; \altera will contribute as |
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| 191 | a supporter (see letter page \pageref{supp:1}) |
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[99] | 192 | providing documentation and development boards. These two companies are strongly motivated |
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[281] | 193 | to help the COACH project to generate efficient bitstreams for both FPGA families. |
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| 194 | The role of the industrial partners \bull, \thales and \mds is to provide |
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[165] | 195 | real use cases to benchmark the COACH design environment and to analyze the designer productivity |
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[246] | 196 | improvements. |
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[99] | 197 | \parlf |
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[281] | 198 | \begin{SUPPRESSEDENV} |
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[49] | 199 | Following the general policy of the SoCLib platform, the COACH project will be an open |
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| 200 | infrastructure, available in the framework of the SoCLib server. |
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| 201 | The architectural templates, and the COACH software tools will be distributed under the |
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| 202 | GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib |
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[281] | 203 | IP core library) will be freely available for non commercial use. |
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| 204 | \end{SUPPRESSEDENV}\begin{ADDEDENV} |
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| 205 | The COACH project will be an open infrastructure and freely distributed. |
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| 206 | The architectural templates and the COACH software tools will be distributed under the |
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| 207 | GPL license. The VHDL synthesizable models for the neutral architectural template |
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| 208 | will also be freely available for non commercial use. |
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| 209 | \end{ADDEDENV} |
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| 210 | For industrial exploitation the technology providers are ready to propose commercial licenses, |
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| 211 | directly to the end user, or through a third party. |
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[269] | 212 | \parlf |
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[281] | 213 | \mustbecompleted{LIST NON A JOUR} |
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| 214 | Finally, the COACH project is already supported by a large number of SMEs, as demonstrated by the |
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[269] | 215 | "letters of interest" (see Annex B), that have collected during the preparation of the project : |
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| 216 | ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL, |
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| 217 | ABOUND Logic, EADS-ASTRIUM. |
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[25] | 218 | |
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