[12] | 1 | \begin{figure}\leavevmode\center |
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| 2 | \includegraphics[width=.8\linewidth]{architecture-csg} |
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[105] | 3 | \caption{\label{archi-csg} Software architecture for digital system generation} |
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[12] | 4 | %\end{figure}\begin{figure}\leavevmode\center |
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| 5 | \mbox{}\vspace*{1ex}\\ |
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[21] | 6 | \includegraphics[width=1.0\linewidth]{architecture-hls} |
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[105] | 7 | \caption{\label{archi-hls} Software architecture of hardware accellerator synthesis} |
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[12] | 8 | %\end{figure}\begin{figure}\leavevmode\center |
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| 9 | \mbox{}\vspace*{1ex}\\ |
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| 10 | \includegraphics[width=.8\linewidth]{architecture-hpc} |
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[105] | 11 | \caption{\label{archi-hpc} Software architecture of HPC} |
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[12] | 12 | \end{figure} |
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| 13 | % |
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[33] | 14 | Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} |
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[65] | 15 | summarize the software architecture of the COACH framework we will develop. |
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[12] | 16 | In figures, the dotted boxes are the softwares or formats that COACH |
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[65] | 17 | has to provide and to support. |
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[99] | 18 | \parlf |
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[56] | 19 | For the system generation presented in figure~\ref{archi-csg}, the conductor |
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[21] | 20 | is the tool \verb!CSG! (COACH System Generator). Its inputs are a process |
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[119] | 21 | network describing the target application and the synthesis parameters. |
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[21] | 22 | The main parameters are the target hardware architectural template |
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[119] | 23 | with its instantiation parameters, the hardware/software mapping of the |
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[21] | 24 | tasks, the FPGA device and design constraints. |
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[119] | 25 | \verb+CSG+ thus requires an architectural template library, an operating system |
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[21] | 26 | library, two system hardware component (CPU, memories, BUS...) libraries |
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| 27 | (one for synthesis, one for simulation). |
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| 28 | For generating the coprocessor of a task mapped as hardware, \verb+CSG+ |
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| 29 | controls the HAS tools described below. |
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[255] | 30 | From these inputs \verb!CSG! can generate the entire system (both software and |
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[275] | 31 | hardware) either \ADDED{ as an IP under IP-XACT to integrate the SoC in larger |
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| 32 | design or} |
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[277] | 33 | as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the |
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[21] | 34 | design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and |
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[134] | 35 | launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the |
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[56] | 36 | FPGA device\footnote{Additional partial bitstreams are generated in case of |
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| 37 | dynamic partial reconfiguration}. |
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[275] | 38 | \begin{ADDEDENV} |
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| 39 | \\ |
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| 40 | Furthermore the architecture template and hardware component libraries will be described |
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| 41 | under the IP-XACT specification to make easilier the configuration of \verb+CSG+ to other |
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| 42 | architecture or the enhancement of existing template with IP. |
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| 43 | \end{ADDEDENV}% |
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[99] | 44 | \parlf |
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[21] | 45 | The software architecture for HAS is presented in figure~\ref{archi-hls}. |
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| 46 | The input is a single task of the process network. The HAS tools do not work |
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[12] | 47 | directly on the C++ task description but on an internal format called |
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[38] | 48 | \xcoach generated by a plugin into the GNU C compiler (GCC). |
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[183] | 49 | This will allow on the one hand to insure that all the tools will |
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[132] | 50 | accept the same C++ description and on the other hand make possible |
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[21] | 51 | their chaining. The front-end tools read a \xcoach description and generate |
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| 52 | a new \xcoach description that exibits more parallelism or implement |
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[132] | 53 | specific instructions for ASIP. The back-end tools read an \xcoach |
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| 54 | description and generate an \xcoachplus description. This is an \xcoach |
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| 55 | description annotated with hardware information (scheduling, binding) required by |
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[21] | 56 | the VHDL and systemC drivers. |
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| 57 | Furthermore, the back-end tools uses a macro-cell library (functional and memory |
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| 58 | unit). |
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[99] | 59 | \parlf |
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[21] | 60 | In addition to digital system design, HPC requires a supplementary |
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| 61 | partitioning step presented in figure~\ref{archi-hpc}. The designer |
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| 62 | splits the initial application (tag 1) in two parts: one still on the PC and the |
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| 63 | other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data |
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| 64 | through communication primitives (tag 2) implemented in a library. |
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[65] | 65 | To evaluate the relevance of the partitioning, the designer can build a |
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[21] | 66 | simulator. Once the partitioning is validated, the design of the FPGA part |
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| 67 | is done through \verb!CSG! (figure~\ref{archi-csg}). |
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[99] | 68 | \parlf |
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[237] | 69 | The project is split into 8 tasks numbered from 1 to 8. They are described |
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| 70 | in short below and in detail in section \ref{task-description}. |
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[99] | 71 | \begin{description} |
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| 72 | \item[Task-1: \textit{Project management}] |
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[132] | 73 | This task relates to the monitoring of the COACH project. |
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[99] | 74 | \item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the |
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[21] | 75 | project such as the defintion of the COACH inputs and outputs, |
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[254] | 76 | the internal formats (i.e. \xcoach and \xcoachplus) and their associated tools, |
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| 77 | the architectural templates and the design flow. |
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[183] | 78 | \item[Task-3: \textit{System generation}] This task addresses the prototyping and |
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| 79 | the generation of digital system. Apart from HAS that belongs to task 3 |
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[21] | 80 | and 4, its components are those presented figure~\ref{archi-csg} |
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| 81 | (e.g. \verb!CSG!, operating systems). |
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[99] | 82 | \item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: |
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[21] | 83 | optimization of the memory usage, parallelism enhancement through loop |
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| 84 | transformations, coarse grain parallelization and ASIP generation. |
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[99] | 85 | \item[Task-5: \textit{HAS back-end}] This task groups two functionalities: |
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[21] | 86 | High-Level Synthesis of data dominated description and HLS of control |
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| 87 | dominated description. |
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| 88 | This task contains also the development of a frequency adaptator |
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[255] | 89 | that will allow the coprocessors to respect the processor and the bus |
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[21] | 90 | frequency. |
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[99] | 91 | \item[Task-6: \textit{PC/FPGA communication middleware}] |
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[132] | 92 | This task pools the features dedicated to HPC. These are mainly the |
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[183] | 93 | validation of the partitioning (see figure~\ref{archi-hpc}), the sytem drivers for |
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[56] | 94 | both PC and FPGA-SoC sides, the hardware communication components and |
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[183] | 95 | the support for dynamic partial reconfiguration. |
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[99] | 96 | \item[Task-7: \textit{Industrial demonstrators}] |
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[33] | 97 | This task groups the demonstrators of the COACH project. |
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[132] | 98 | Most of them are industrial applications that will be developped within |
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| 99 | the COACH framework. |
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| 100 | Others consist in integrating the COACH framework as a driver of |
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| 101 | industrial proprietary design tools. |
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[183] | 102 | \item[Task 8: \textit{Dissemination}] |
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[132] | 103 | This task concerns the diffusion of the project results. |
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[99] | 104 | It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, |
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[183] | 105 | \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication |
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| 106 | of research papers in international journals and conferences and the organization of workshops and tutorials in |
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| 107 | international conferences. |
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[99] | 108 | \end{description} |
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[21] | 109 | % |
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[12] | 110 | \begin{figure}\leavevmode\center |
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[21] | 111 | %\includegraphics[width=.4\linewidth]{dependence-task} |
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| 112 | \includegraphics[width=0.70\linewidth]{dependence-task-h} |
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| 113 | \caption{\label{dependence-task}Task dependencies} |
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[12] | 114 | \end{figure} |
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[65] | 115 | Figure~\ref{dependence-task} presents the tasks dependencies. |
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[99] | 116 | "$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. |
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[132] | 117 | The more bold the arrow, the more important is the impact. |
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[21] | 118 | The graph shows: |
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| 119 | \begin{itemize} |
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[254] | 120 | \item Even though $T4$ and $T5$ functionalities are complementary, |
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[132] | 121 | their developments are independent (thanks to the \xcoach internal format). |
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[254] | 122 | \item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may work |
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| 123 | without $T4$ and $T5$ if targeted digital systems do not include hardware |
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[132] | 124 | accelerators. |
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| 125 | \item $T3$ strongly impacts $T6$ but $T3$ does not depend at all on |
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| 126 | $T6$. Hence demonstrators ($T7$) of embedded system would not be impacted if |
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[99] | 127 | $T6$ would fail. |
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[132] | 128 | \item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) and is at the heart of |
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[65] | 129 | the COACH project. |
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[254] | 130 | \item The demonstrators developped in $T7$, of course strongly depend on the achievements |
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[105] | 131 | of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$). |
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[254] | 132 | \item $T8$ and $T1$ depend on and impact all the other tasks. |
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[21] | 133 | \end{itemize} |
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[33] | 134 | This organisation offers enough robustness to insure the success of the |
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[99] | 135 | project except for the specification task $T2$. |
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| 136 | The only critical task in this chart is $T2$. \label{xcoach-problem} |
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[33] | 137 | However, the partners met |
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[254] | 138 | 12 times (a one-day meeting per month) during the last year: 10 meetings to exchange and work on scientific |
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| 139 | and technical aspects and 2 meetings to prepare the project proposal. This gives us a high degree of confidence |
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[99] | 140 | that $T2$ will be completed in time. |
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