[23] | 1 | \begin{taskinfo} |
---|
| 2 | \let\UPMC\leader |
---|
| 3 | \let\IRISA\enable |
---|
[49] | 4 | \let\TIMA\enable |
---|
[23] | 5 | \end{taskinfo} |
---|
| 6 | % |
---|
| 7 | \begin{objectif} |
---|
[39] | 8 | This task deals with the prototyping and the generation of FPGA-SoC digital systems. |
---|
[36] | 9 | Its is described on figure~\ref{archi-csg}. |
---|
| 10 | Its objective is to allow the system designer to explore the system space design by |
---|
| 11 | quickly prototyping and then to generate automatically the FPGA-SoC system. |
---|
[23] | 12 | This task consists of |
---|
| 13 | \begin{itemize} |
---|
[108] | 14 | \item the development of all the missing components (SytemC models and/or synthesizable VHDL models |
---|
| 15 | of the IP-cores), |
---|
| 16 | \item the configuration and the development of drivers %FIXME == {driver de quoi ???} |
---|
| 17 | of the operating systems, |
---|
| 18 | \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description |
---|
| 19 | of the FPGA-SoC system (i.e. its bitstream), %FIXME == {VHDL ou bitstream ???} |
---|
| 20 | \item the specification of enhanced communication schemes and their sofware and hardware implementations. |
---|
[23] | 21 | \end{itemize} |
---|
| 22 | This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ |
---|
| 23 | to allow the demonstrators to start working. |
---|
[38] | 24 | This release will include the standard communication schemes (base on SocLib MWMR component) |
---|
[23] | 25 | and support the COACH architectural template for prototyping and hardware generation. |
---|
| 26 | \end{objectif} |
---|
| 27 | % |
---|
[52] | 28 | \begin{workpackage} |
---|
[36] | 29 | \item This \ST corresponds to the Coach System Generator (CSG) software. |
---|
[23] | 30 | \begin{livrable} |
---|
[52] | 31 | \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} |
---|
[108] | 32 | The first software release of the CSG tool that will allow demonstrators to start working by using the COACH |
---|
[36] | 33 | hardware architecture template. |
---|
[52] | 34 | \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} |
---|
[36] | 35 | This milestone adds to CSG the support to the XILINX and ALTERA architectural |
---|
| 36 | templates and to the enhanced communication system. |
---|
| 37 | In this milestone only the SystemC prototyping will be supported for the XILINX |
---|
| 38 | and ALTERA architectural template. |
---|
[108] | 39 | HAS is available. %FIXME = {ca veut dire ???} |
---|
[52] | 40 | \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} |
---|
[36] | 41 | This milestone extends CSG (\csgPrototypingOnly) to |
---|
| 42 | FPGA-SoC generation for the XILINX and ALTERA architectural template. |
---|
[59] | 43 | \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6} |
---|
[52] | 44 | Maintenance work of CSG. |
---|
[23] | 45 | \end{livrable} |
---|
[108] | 46 | \item This \ST deals with the components of the architectural templates. |
---|
[36] | 47 | \\ |
---|
| 48 | For the COACH architectural template, it consists of the devlopment of the VHDL |
---|
[108] | 49 | synthesizable description of the missing components. %FIXME == {pas clair missing components} |
---|
| 50 | Notice that the SystemC models |
---|
[36] | 51 | comes from the SocLib ANR project, the processor with its cache comes from the TSAR |
---|
| 52 | ANR project. |
---|
| 53 | \\ |
---|
[108] | 54 | For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...). |
---|
[39] | 55 | The missing component is the MWMR used for communication between the tasks of the |
---|
[36] | 56 | application. |
---|
[23] | 57 | \begin{livrable} |
---|
[52] | 58 | \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0} |
---|
| 59 | The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. |
---|
| 60 | \itemV{6}{18}{x}{\Stima}{XILINX architecture} |
---|
[36] | 61 | \setMacroInAuxFile{csgXilinxSystemC} |
---|
| 62 | The SystemC simulation module of the MWMR component with a PLB bus interface plus |
---|
| 63 | the SystemC modules of the components of the XILINX architectural template |
---|
[108] | 64 | currently not available in the SocLib component library. |
---|
[57] | 65 | \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0} |
---|
[36] | 66 | The synthesizable VHDL description of the MWMR component corresponding to the |
---|
| 67 | SystemC module of the former delivrable (\csgXilinxSystemC). |
---|
[52] | 68 | \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture} |
---|
[36] | 69 | \setMacroInAuxFile{csgAlteraSystemC} |
---|
[39] | 70 | The SystemC simulation module of the MWMR component with an AVALON bus interface plus |
---|
[36] | 71 | the SystemC modules of the components of the ALTERA architectural template |
---|
[108] | 72 | currently not available in the SocLib component library. |
---|
[52] | 73 | \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0} |
---|
[36] | 74 | The synthesizable VHDL description of the MWMR component corresponding to the |
---|
| 75 | SystemC module of the former delivrable (\csgAlteraSystemC); |
---|
[74] | 76 | \itemV{6}{12}{d}{\Subs}{UBS communication adapter} |
---|
| 77 | \setMacroInAuxFile{gautCOMMoptimization} |
---|
| 78 | Specification of an optimized communication adapter (space and time) component to handle data interleaving. |
---|
[47] | 79 | This evolution aims to solve out of order communication weakness of the classical MWMR. |
---|
[74] | 80 | \itemV{12}{24}{x}{\Subs}{UBS communication adapter} |
---|
| 81 | First release of the tool that generates the VHDL description of the optimized communication adapter |
---|
[47] | 82 | and its corresponding SystemC module. |
---|
[74] | 83 | \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0} |
---|
| 84 | Final release of the tool that generates the VHDL description of the optimized communication adapter |
---|
| 85 | and its corresponding SystemC module (\gautCOMMoptimization). |
---|
[23] | 86 | \end{livrable} |
---|
[36] | 87 | \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating |
---|
| 88 | system and the development of drivers for the hardware architectural templates |
---|
[38] | 89 | and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. |
---|
[108] | 90 | For the ALTERA and XILINX architectural templates, the OSs must also be ported on |
---|
[36] | 91 | the NIOS2 and MICROBLAZE processors. |
---|
[23] | 92 | \begin{livrable} |
---|
[52] | 93 | \itemV{6}{8}{x}{\Supmc}{MUTEK OS} |
---|
[108] | 94 | The drivers %FIXME = {???} |
---|
| 95 | required for the first CSG milestone (delivrable \csgCoachArch). |
---|
[52] | 96 | \itemV{8}{18}{x}{\Supmc}{MUTEK 0S} |
---|
| 97 | The drivers required for the second CSG milestone ({\csgPrototypingOnly}). |
---|
| 98 | \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2} |
---|
| 99 | Maintenance work. |
---|
| 100 | \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0} |
---|
[108] | 101 | Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors. |
---|
[52] | 102 | \itemV{6}{8}{x}{\Stima}{DNA OS} |
---|
| 103 | The drivers required for the first CSG milestone (delivrable \csgCoachArch). |
---|
| 104 | \itemV{8}{18}{x}{\Stima}{DNA 0S} |
---|
| 105 | The drivers required for the second CSG milestone ({\csgPrototypingOnly}). |
---|
[63] | 106 | \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2} |
---|
[52] | 107 | Maintenance work. |
---|
[57] | 108 | \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0} |
---|
[108] | 109 | Porting of DNA OS on the NIOS2 and MICROBLAZE processors. |
---|
[23] | 110 | \end{livrable} |
---|
| 111 | \end{workpackage} |
---|