[23] | 1 | \begin{taskinfo} |
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| 2 | \let\UPMC\leader |
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| 3 | \let\TIMA\enable |
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| 4 | \let\ALTERA\enable |
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| 5 | \end{taskinfo} |
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| 6 | % |
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| 7 | \begin{objectif} |
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| 8 | This task pools the features dedicated to HPC system design. It is described on |
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| 9 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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| 10 | \begin{itemize} |
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| 11 | \item Helping the HPC designer to find a good partition of the initial application |
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| 12 | (figure~\ref{archi-hpc}. |
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[38] | 13 | \item Providing communication schemes between the software part runing on the PC and the |
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[23] | 14 | FPGA-SoC. |
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[38] | 15 | \item Implementing the communication scheme at all levels: partition help, software |
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[23] | 16 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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| 17 | \item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA} |
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| 18 | \end{itemize} |
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| 19 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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| 20 | transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for |
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| 21 | their FPGA and that GPU HPC softwares use also it. |
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[38] | 22 | This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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[23] | 23 | parts of the GPU softwares. |
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| 24 | \end{objectif} |
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| 25 | % |
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[52] | 26 | \begin{workpackage} |
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[38] | 27 | \item This \ST is the definition of the communication schemes as a software API |
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[23] | 28 | (Application Programing Interface) between the application part running on the PC and |
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| 29 | the application part running on the FPGA-SoC. |
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| 30 | \begin{livrable} |
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[52] | 31 | \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} |
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| 32 | \setMacroInAuxFile{hpcCommApi} |
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| 33 | User refernce manual describing the API. |
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[23] | 34 | \end{livrable} |
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[40] | 35 | \item This \ST consists in helping to partition the application. |
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[36] | 36 | It is a library implementing the communication API with features to profile |
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[40] | 37 | the partitioned application. |
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[23] | 38 | \begin{livrable} |
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[52] | 39 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 40 | A library implementing the communication API defined in the {\hpcCommApi} delivrable. |
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[23] | 41 | \end{livrable} |
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[40] | 42 | \item This \ST deals with the implementation of the communication API on the both sides (PC |
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[23] | 43 | part and FPGA-SoC). |
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| 44 | \begin{livrable} |
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[52] | 45 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0} |
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| 46 | The PC part of the HPC communication API that comminicates with the FPGA-SOC, a |
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| 47 | library and probably a LINUX module. |
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| 48 | \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0} |
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| 49 | \setMacroInAuxFile{hpcMutekDriver} |
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| 50 | The FPGA-SoC part of the communication API, a driver. |
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| 51 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:0:0} |
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| 52 | Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 53 | \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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| 54 | Maintenance work of HPC API for both Lunix PC and MUTEK OS. |
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[23] | 55 | \end{livrable} |
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[40] | 56 | \item This \ST deals with the implementation of hardware required by the COACH |
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[23] | 57 | architectural template for using the PCI/X IP of \altera and \xilinx. |
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| 58 | \begin{livrable} |
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[52] | 59 | \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{0:0:0} |
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[36] | 60 | \setMacroInAuxFile{hpcPlbBridge} |
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| 61 | The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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[52] | 62 | \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0} |
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[36] | 63 | \setMacroInAuxFile{hpcAvalonBridge} |
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[40] | 64 | The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[23] | 65 | \end{livrable} |
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[40] | 66 | \item This \ST deals with the dynamic reconfiguration of an FPGA. |
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[23] | 67 | \begin{livrable} |
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[52] | 68 | \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0} |
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| 69 | \setMacroInAuxFile{hpcDynconfDriver} |
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[36] | 70 | \mustbecompleted{FIXME:TIMA ....} |
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[52] | 71 | \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} |
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[36] | 72 | Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. |
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[52] | 73 | \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2} |
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[36] | 74 | \mustbecompleted{FIXME:TIMA ....} |
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[52] | 75 | \itemL{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}{0:0:0} |
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[36] | 76 | \mustbecompleted{FIXME:TIMA ....} |
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[23] | 77 | \end{livrable} |
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[27] | 78 | \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 79 | with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 80 | They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 81 | \begin{livrable} |
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[52] | 82 | \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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[27] | 83 | \end{livrable} |
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[23] | 84 | \end{workpackage} |
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