[56] | 1 | % vim:set spell: |
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| 2 | % vim:spell spelllang=en: |
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| 3 | |
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[23] | 4 | \begin{taskinfo} |
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| 5 | \let\UPMC\leader |
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| 6 | \let\TIMA\enable |
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| 7 | \let\ALTERA\enable |
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| 8 | \end{taskinfo} |
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| 9 | % |
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| 10 | \begin{objectif} |
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| 11 | This task pools the features dedicated to HPC system design. It is described on |
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| 12 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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| 13 | \begin{itemize} |
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| 14 | \item Helping the HPC designer to find a good partition of the initial application |
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[56] | 15 | (figure~\ref{archi-hpc}). |
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| 16 | \item Providing communication schemes between the software part running on the PC and the |
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[23] | 17 | FPGA-SoC. |
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[38] | 18 | \item Implementing the communication scheme at all levels: partition help, software |
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[23] | 19 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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[56] | 20 | \item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order to optimize FPGA ressource usage. |
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[23] | 21 | \end{itemize} |
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[56] | 22 | |
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[23] | 23 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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| 24 | transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for |
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| 25 | their FPGA and that GPU HPC softwares use also it. |
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[38] | 26 | This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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[23] | 27 | parts of the GPU softwares. |
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[56] | 28 | |
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| 29 | |
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[23] | 30 | \end{objectif} |
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| 31 | % |
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[52] | 32 | \begin{workpackage} |
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[38] | 33 | \item This \ST is the definition of the communication schemes as a software API |
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[23] | 34 | (Application Programing Interface) between the application part running on the PC and |
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| 35 | the application part running on the FPGA-SoC. |
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| 36 | \begin{livrable} |
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[52] | 37 | \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} |
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| 38 | \setMacroInAuxFile{hpcCommApi} |
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[56] | 39 | User reference manual describing the API. |
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[23] | 40 | \end{livrable} |
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[56] | 41 | \item This \ST consists in helping to partition applications. |
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[36] | 42 | It is a library implementing the communication API with features to profile |
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[40] | 43 | the partitioned application. |
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[56] | 44 | %FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application. |
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| 45 | % It is a profiling (or simulation) library implementing the communication API |
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| 46 | |
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[23] | 47 | \begin{livrable} |
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[52] | 48 | \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0} |
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| 49 | A library implementing the communication API defined in the {\hpcCommApi} delivrable. |
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[23] | 50 | \end{livrable} |
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[40] | 51 | \item This \ST deals with the implementation of the communication API on the both sides (PC |
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[23] | 52 | part and FPGA-SoC). |
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| 53 | \begin{livrable} |
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[52] | 54 | \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0} |
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| 55 | The PC part of the HPC communication API that comminicates with the FPGA-SOC, a |
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| 56 | library and probably a LINUX module. |
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| 57 | \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0} |
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| 58 | \setMacroInAuxFile{hpcMutekDriver} |
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| 59 | The FPGA-SoC part of the communication API, a driver. |
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| 60 | \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:0:0} |
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| 61 | Port of the {\hpcMutekDriver} driver on the DNA OS. |
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| 62 | \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} |
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[56] | 63 | Maintenance work of HPC API for both Linux PC and MUTEK OS. |
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[23] | 64 | \end{livrable} |
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[40] | 65 | \item This \ST deals with the implementation of hardware required by the COACH |
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[23] | 66 | architectural template for using the PCI/X IP of \altera and \xilinx. |
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| 67 | \begin{livrable} |
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[52] | 68 | \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{0:0:0} |
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[36] | 69 | \setMacroInAuxFile{hpcPlbBridge} |
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| 70 | The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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[52] | 71 | \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0} |
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[36] | 72 | \setMacroInAuxFile{hpcAvalonBridge} |
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[40] | 73 | The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model. |
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[23] | 74 | \end{livrable} |
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[56] | 75 | \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. |
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| 76 | It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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| 77 | |
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[23] | 78 | \begin{livrable} |
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[56] | 79 | \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration} |
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| 80 | Extension of the \xilinx architectural template ({\csgAllArch}) |
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| 81 | in order to integrate dynamic partial reconfiguration regions. |
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| 82 | Modification of CSG software to support the extended \xilinx template. |
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[52] | 83 | \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:0:0} |
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| 84 | \setMacroInAuxFile{hpcDynconfDriver} |
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[56] | 85 | The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA. |
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[52] | 86 | \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} |
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[56] | 87 | Port of the {\hpcDynconfDriver} drivers on the MUTEK OS. |
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| 88 | \itemL{18}{36}{x}{\Stima}{HPC support for \ganttlf dynamic reconfiguration}{0:0:2} |
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| 89 | Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features |
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| 90 | (reconfiguration time of regions, variable number of coprocessors) |
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| 91 | \end{livrable} |
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[27] | 92 | \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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| 93 | with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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| 94 | They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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| 95 | \begin{livrable} |
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[52] | 96 | \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. |
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[27] | 97 | \end{livrable} |
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[23] | 98 | \end{workpackage} |
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