[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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[123] | 18 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_ALL |
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| 19 | // #define MANAGE_EVENT MANAGE_EVENT_WAIT_DECODE |
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| 20 | #define MANAGE_EVENT MANAGE_EVENT_NO_WAIT |
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[83] | 21 | |
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[124] | 22 | #define PRIORITY_MISS_LOAD 3 |
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| 23 | #define PRIORITY_MISS_BRANCH 2 |
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| 24 | #define PRIORITY_EXCEPTION 1 |
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| 25 | #define PRIORITY_NONE 0 |
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| 26 | |
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[111] | 27 | #define get_priority(x) \ |
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| 28 | (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ |
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[123] | 29 | (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ |
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[111] | 30 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ |
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| 31 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ |
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[124] | 32 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?PRIORITY_MISS_LOAD: \ |
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[111] | 33 | (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ |
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| 34 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ |
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[145] | 35 | (state == CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE ) or \ |
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[124] | 36 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?PRIORITY_MISS_BRANCH: \ |
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| 37 | ((state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION: \ |
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[111] | 38 | 0))) |
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| 39 | |
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[83] | 40 | #undef FUNCTION |
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| 41 | #define FUNCTION "Context_State::transition" |
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| 42 | void Context_State::transition (void) |
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| 43 | { |
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| 44 | log_begin(Context_State,FUNCTION); |
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[88] | 45 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 46 | |
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| 47 | if (PORT_READ(in_NRESET) == 0) |
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| 48 | { |
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[88] | 49 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 50 | { |
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| 51 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 52 | reg_INTERRUPT_ENABLE [i] = 0; |
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[128] | 53 | |
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| 54 | reg_EVENT_ADDRESS [i] = 0; // not necessary |
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| 55 | reg_EVENT_ADDRESS_EPCR [i] = 0; // not necessary |
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| 56 | reg_EVENT_ADDRESS_EPCR_VAL [i] = 0; // not necessary |
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| 57 | reg_EVENT_ADDRESS_EEAR [i] = 0; // not necessary |
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| 58 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; // not necessary |
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| 59 | reg_EVENT_IS_DELAY_SLOT [i] = 0; // not necessary |
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| 60 | reg_EVENT_IS_DS_TAKE [i] = 0; // not necessary |
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| 61 | reg_EVENT_DEPTH [i] = 0; // not necessary |
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| 62 | reg_EVENT_FLUSH_ONLY [i] = 0; // not necessary |
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[88] | 63 | } |
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[83] | 64 | } |
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| 65 | else |
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| 66 | { |
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[88] | 67 | // ------------------------------------------------------------------- |
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[101] | 68 | // -----[ next state ]------------------------------------------------ |
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| 69 | // ------------------------------------------------------------------- |
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| 70 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 71 | { |
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| 72 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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| 73 | |
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[122] | 74 | Tcounter_t inst_commit_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]); |
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| 75 | // Tcounter_t inst_commit_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]); |
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| 76 | Tcounter_t inst_decod_all = PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 77 | Tcounter_t inst_all = inst_commit_all + inst_decod_all; |
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| 78 | // Tcounter_t inst_mem = inst_commit_mem + inst_decod_all; |
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[123] | 79 | bool condition = ( (MANAGE_EVENT == MANAGE_EVENT_WAIT_ALL )?(inst_all == 0): |
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| 80 | ((MANAGE_EVENT == MANAGE_EVENT_WAIT_DECODE)?(inst_decod_all == 0): |
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| 81 | true)); |
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[101] | 82 | |
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| 83 | context_state_t state = reg_STATE [i]; |
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| 84 | |
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| 85 | switch (state) |
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| 86 | { |
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| 87 | case CONTEXT_STATE_OK : |
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| 88 | { |
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| 89 | // nothing, wait an event |
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| 90 | break; |
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| 91 | } |
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| 92 | case CONTEXT_STATE_KO_EXCEP : |
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| 93 | { |
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| 94 | // Wait end of all instruction |
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| 95 | if (inst_all == 0) |
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[122] | 96 | // if (inst_decod_all == 0) |
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[101] | 97 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 98 | break; |
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| 99 | } |
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| 100 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 101 | { |
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| 102 | // nothing, wait the update of internal register (pc) |
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| 103 | break; |
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| 104 | } |
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[111] | 105 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
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| 106 | { |
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| 107 | // nothing : wait end of update upt |
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| 108 | break; |
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| 109 | } |
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[105] | 110 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
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[101] | 111 | { |
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[123] | 112 | if (condition) |
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[122] | 113 | // state = CONTEXT_STATE_OK; |
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[105] | 114 | state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[101] | 115 | break; |
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| 116 | } |
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[145] | 117 | case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : |
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| 118 | { |
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| 119 | if (inst_all == 0) |
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| 120 | // state = CONTEXT_STATE_OK; |
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| 121 | state = CONTEXT_STATE_OK; |
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| 122 | break; |
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| 123 | } |
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[105] | 124 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : |
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| 125 | { |
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| 126 | // Wait end of all instruction |
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[123] | 127 | if (condition) |
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[105] | 128 | state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
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| 129 | |
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| 130 | break; |
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| 131 | } |
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[101] | 132 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 133 | { |
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| 134 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 135 | break; |
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| 136 | } |
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[105] | 137 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
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[101] | 138 | { |
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| 139 | // nothing, wait the update of internal register (pc) |
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| 140 | break; |
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| 141 | } |
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[105] | 142 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
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| 143 | { |
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| 144 | // nothing, wait the update of internal register (pc) |
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| 145 | break; |
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| 146 | } |
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[111] | 147 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : |
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[108] | 148 | { |
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[111] | 149 | // nothing : wait end of update upt |
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| 150 | break; |
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| 151 | } |
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| 152 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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| 153 | { |
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[108] | 154 | // nothing, wait the update of internal register (pc) |
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| 155 | break; |
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| 156 | } |
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[111] | 157 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
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| 158 | { |
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| 159 | // Wait end of all instruction |
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[123] | 160 | if (condition) |
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[111] | 161 | // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) |
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| 162 | state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 163 | break; |
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| 164 | } |
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[101] | 165 | // case CONTEXT_STATE_KO_PSYNC : |
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| 166 | // { |
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| 167 | // // Wait end of all instruction |
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| 168 | // if (inst_all == 0) |
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| 169 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 170 | // break; |
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| 171 | // } |
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| 172 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 173 | { |
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| 174 | // nothing, wait end of flush (ifetch) |
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| 175 | if (inst_all == 0) |
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| 176 | // state = CONTEXT_STATE_KO_PSYNC_ADDR; |
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| 177 | state = CONTEXT_STATE_OK; |
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| 178 | |
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| 179 | break; |
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| 180 | } |
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| 181 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 182 | { |
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| 183 | // nothing, wait the pc write |
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| 184 | break; |
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| 185 | } |
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| 186 | // case CONTEXT_STATE_KO_CSYNC : |
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| 187 | // { |
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| 188 | // // Wait end of all instruction |
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| 189 | // if (inst_all == 0) |
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| 190 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 191 | // break; |
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| 192 | // } |
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| 193 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 194 | { |
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| 195 | // nothing, wait end of flush (all internal structure) |
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| 196 | if (inst_all == 0) |
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| 197 | state = CONTEXT_STATE_KO_CSYNC_ADDR; |
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| 198 | break; |
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| 199 | } |
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| 200 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 201 | { |
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| 202 | // nothing, wait the pc write |
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| 203 | break; |
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| 204 | } |
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| 205 | // case CONTEXT_STATE_KO_MSYNC : |
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| 206 | // { |
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| 207 | // // Wait end of memory instruction |
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| 208 | // if (inst_mem == 0) |
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| 209 | // state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 210 | // break; |
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| 211 | // } |
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| 212 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 213 | // { |
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| 214 | // // Wait the msync issue |
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| 215 | // if (inst_mem != 0) |
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| 216 | // state = CONTEXT_STATE_KO_MSYNC_EXEC; |
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| 217 | // break; |
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| 218 | // } |
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| 219 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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| 220 | { |
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| 221 | // Wait the end of msync |
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| 222 | if (inst_all == 0) |
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| 223 | state = CONTEXT_STATE_OK; |
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| 224 | break; |
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| 225 | } |
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| 226 | // case CONTEXT_STATE_KO_SPR : |
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| 227 | // { |
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| 228 | // // Wait end of all instruction |
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| 229 | // if (inst_all == 0) |
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| 230 | // state = CONTEXT_STATE_KO_SPR_ISSUE; |
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| 231 | // break; |
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| 232 | // } |
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| 233 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 234 | // { |
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| 235 | // // Wait the spr_access issue |
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| 236 | // if (inst_all != 0) |
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| 237 | // state = CONTEXT_STATE_KO_SPR_EXEC; |
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| 238 | // break; |
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| 239 | // } |
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| 240 | case CONTEXT_STATE_KO_SPR_EXEC : |
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| 241 | { |
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| 242 | // Wait the spr_access execution |
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| 243 | if (inst_all == 0) |
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| 244 | state = CONTEXT_STATE_OK; |
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| 245 | break; |
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| 246 | } |
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| 247 | |
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| 248 | default : |
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| 249 | { |
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| 250 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
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| 251 | } |
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| 252 | } |
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| 253 | reg_STATE [i] = state; |
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| 254 | } |
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| 255 | |
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| 256 | // ------------------------------------------------------------------- |
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[88] | 257 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 258 | // ------------------------------------------------------------------- |
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| 259 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 260 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 261 | { |
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[98] | 262 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); |
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| 263 | |
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[88] | 264 | context_state_t state = reg_STATE [i]; |
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[83] | 265 | |
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[98] | 266 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; |
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[88] | 267 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 268 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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[106] | 269 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; |
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[88] | 270 | |
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[106] | 271 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 272 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 273 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 274 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 275 | |
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[111] | 276 | // priority : miss_load > miss_branch > excep > spr/sync |
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| 277 | uint8_t priority0 = get_priority(state); |
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[124] | 278 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
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[83] | 279 | |
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[88] | 280 | // is_valid = can modify local information |
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| 281 | // if context_state_ok : yes |
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[98] | 282 | // if context_state_ko : test the depth, and the priority of event |
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[88] | 283 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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[111] | 284 | (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or |
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[124] | 285 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or |
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[88] | 286 | (depth1< depth0) or |
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[98] | 287 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
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[83] | 288 | |
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[124] | 289 | bool is_invalid = priority0 == PRIORITY_MISS_LOAD; |
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| 290 | |
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[111] | 291 | #ifdef DEBUG_TEST |
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| 292 | if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and |
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| 293 | (depth0 != depth1)) |
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| 294 | throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); |
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| 295 | #endif |
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| 296 | |
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[123] | 297 | log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); |
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[106] | 298 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 299 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 300 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 301 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 302 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 303 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 304 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 305 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 306 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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[128] | 307 | log_printf(TRACE,Context_State,FUNCTION," * is_invalid : %d",is_invalid); |
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[106] | 308 | |
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[124] | 309 | if (is_valid and not is_invalid) |
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[88] | 310 | { |
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[105] | 311 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[111] | 312 | |
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| 313 | if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) |
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| 314 | { |
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[124] | 315 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
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| 316 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
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| 317 | // #else |
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[111] | 318 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
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[124] | 319 | // #endif |
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[111] | 320 | } |
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| 321 | else |
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| 322 | { |
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[119] | 323 | Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); |
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| 324 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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[111] | 325 | |
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[119] | 326 | log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); |
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| 327 | log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); |
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| 328 | |
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| 329 | if (can_continue) |
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| 330 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
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[145] | 331 | else |
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| 332 | // cf UPT : dest_val = direction, accurate depend of jump type (e.g. jr is inacurate) |
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| 333 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; |
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| 334 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE; |
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[119] | 335 | |
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| 336 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 337 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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| 338 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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| 339 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 340 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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| 341 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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| 342 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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| 343 | reg_EVENT_DEPTH [i] = depth; |
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| 344 | reg_EVENT_FLUSH_ONLY [i] = can_continue; |
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[111] | 345 | } |
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| 346 | } |
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| 347 | } |
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[88] | 348 | |
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| 349 | // ------------------------------------------------------------------- |
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| 350 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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| 351 | // ------------------------------------------------------------------- |
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[83] | 352 | |
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[88] | 353 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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| 354 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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| 355 | { |
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[98] | 356 | log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); |
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| 357 | |
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[88] | 358 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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| 359 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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| 360 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 361 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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[106] | 362 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
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[88] | 363 | |
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[106] | 364 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 365 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 366 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 367 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 368 | |
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[88] | 369 | context_state_t state = reg_STATE [context]; |
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| 370 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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| 371 | |
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[111] | 372 | // miss_load > miss_branch > excep > spr/sync |
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| 373 | uint8_t priority0 = get_priority(state); |
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[124] | 374 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE; |
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[83] | 375 | |
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[88] | 376 | // is_valid = can modify local information |
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| 377 | // if context_state_ok : yes |
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| 378 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 379 | |
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[88] | 380 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 381 | (depth1< depth0) or |
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[105] | 382 | ((depth1==depth0) and (priority1>=priority0))); |
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[83] | 383 | |
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[106] | 384 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
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| 385 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
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| 386 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
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| 387 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
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| 388 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
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| 389 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
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| 390 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
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| 391 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
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| 392 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
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| 393 | |
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[88] | 394 | if (is_valid) |
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| 395 | { |
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[101] | 396 | log_printf(TRACE,Context_State,FUNCTION," * is_valid"); |
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| 397 | |
---|
[88] | 398 | // decod : |
---|
| 399 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
---|
| 400 | context_state_t state_next = state; |
---|
| 401 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
---|
| 402 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
---|
[83] | 403 | |
---|
[88] | 404 | switch (type) |
---|
| 405 | { |
---|
| 406 | case EVENT_TYPE_EXCEPTION : |
---|
| 407 | { |
---|
[101] | 408 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); |
---|
| 409 | |
---|
[88] | 410 | state_next = CONTEXT_STATE_KO_EXCEP; |
---|
[83] | 411 | |
---|
[88] | 412 | break; |
---|
| 413 | } |
---|
| 414 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 415 | { |
---|
[101] | 416 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); |
---|
| 417 | |
---|
| 418 | // state_next = CONTEXT_STATE_KO_SPR ; |
---|
| 419 | state_next = CONTEXT_STATE_KO_SPR_EXEC; |
---|
[88] | 420 | address++; // take next address |
---|
[101] | 421 | // if (is_delay_slot) |
---|
| 422 | // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
---|
[88] | 423 | break; |
---|
| 424 | } |
---|
| 425 | case EVENT_TYPE_MSYNC : |
---|
| 426 | { |
---|
[101] | 427 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); |
---|
| 428 | |
---|
| 429 | // state_next = CONTEXT_STATE_KO_MSYNC; |
---|
| 430 | state_next = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
[88] | 431 | address++; // take next address |
---|
[101] | 432 | // if (is_delay_slot) |
---|
| 433 | // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); |
---|
[88] | 434 | break; |
---|
| 435 | } |
---|
| 436 | case EVENT_TYPE_PSYNC : |
---|
| 437 | { |
---|
[101] | 438 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); |
---|
| 439 | |
---|
| 440 | // state_next = CONTEXT_STATE_KO_PSYNC; |
---|
| 441 | state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; |
---|
[88] | 442 | address++; // take next address |
---|
| 443 | if (is_delay_slot) |
---|
[101] | 444 | throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); |
---|
[88] | 445 | break; |
---|
| 446 | } |
---|
| 447 | case EVENT_TYPE_CSYNC : |
---|
| 448 | { |
---|
[101] | 449 | log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); |
---|
| 450 | |
---|
| 451 | // state_next = CONTEXT_STATE_KO_CSYNC; |
---|
| 452 | state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; |
---|
[88] | 453 | address++; // take next address |
---|
| 454 | if (is_delay_slot) |
---|
[101] | 455 | throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); |
---|
[88] | 456 | break; |
---|
| 457 | } |
---|
| 458 | case EVENT_TYPE_NONE : |
---|
[105] | 459 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 460 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 461 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 462 | default : |
---|
| 463 | { |
---|
| 464 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
---|
| 465 | } |
---|
| 466 | } |
---|
[83] | 467 | |
---|
[88] | 468 | reg_STATE [context] = state_next; |
---|
| 469 | reg_EVENT_ADDRESS [context] = address; |
---|
| 470 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
---|
| 471 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
---|
| 472 | //reg_EVENT_ADDRESS_EEAR [context] |
---|
| 473 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
---|
| 474 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
---|
| 475 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
| 476 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 477 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 478 | } |
---|
| 479 | } |
---|
[83] | 480 | |
---|
[88] | 481 | // ------------------------------------------------------------------- |
---|
[128] | 482 | // -----[ EVENT ]----------------------------------------------------- |
---|
| 483 | // ------------------------------------------------------------------- |
---|
| 484 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 485 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
---|
| 486 | { |
---|
| 487 | log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); |
---|
| 488 | // Write pc |
---|
| 489 | context_state_t state = reg_STATE [i]; |
---|
| 490 | |
---|
| 491 | switch (state) |
---|
| 492 | { |
---|
| 493 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
| 494 | { |
---|
| 495 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
---|
| 496 | break; |
---|
| 497 | } |
---|
| 498 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: |
---|
| 499 | |
---|
| 500 | // { |
---|
| 501 | // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) |
---|
| 502 | // break; |
---|
| 503 | // } |
---|
| 504 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
| 505 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
---|
| 506 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
---|
| 507 | { |
---|
| 508 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
| 509 | break; |
---|
| 510 | } |
---|
| 511 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
---|
| 512 | { |
---|
| 513 | reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
---|
| 514 | break; |
---|
| 515 | } |
---|
| 516 | default : |
---|
| 517 | { |
---|
| 518 | #ifdef DEBUG_TEST |
---|
| 519 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
| 520 | #endif |
---|
| 521 | break; |
---|
| 522 | } |
---|
| 523 | } |
---|
| 524 | } |
---|
| 525 | |
---|
| 526 | // ------------------------------------------------------------------- |
---|
| 527 | // -----[ BRANCH_COMPLETE ]---------------------------------------------- |
---|
| 528 | // ------------------------------------------------------------------- |
---|
| 529 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
---|
| 530 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] |
---|
| 531 | and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
---|
| 532 | { |
---|
| 533 | log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
| 534 | |
---|
| 535 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
---|
| 536 | |
---|
| 537 | context_state_t state = reg_STATE [context_id]; |
---|
| 538 | |
---|
| 539 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
---|
| 540 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id]; |
---|
| 541 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0; |
---|
| 542 | Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id]; |
---|
| 543 | |
---|
| 544 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 545 | Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 546 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 547 | // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
| 548 | |
---|
| 549 | // priority : miss_load > miss_branch > excep > spr/sync |
---|
| 550 | uint8_t priority0 = get_priority(state); |
---|
| 551 | uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss |
---|
| 552 | |
---|
| 553 | // is_valid = can modify local information |
---|
| 554 | // if context_state_ok : yes |
---|
| 555 | // if context_state_ko : test the depth, and the priority of event |
---|
| 556 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 557 | (depth1< depth0) or |
---|
| 558 | ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth |
---|
| 559 | |
---|
| 560 | log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id); |
---|
| 561 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
| 562 | log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 563 | log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 564 | log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 565 | log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 566 | log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 567 | log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 568 | log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
| 569 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 570 | |
---|
| 571 | if (is_valid) |
---|
| 572 | { |
---|
| 573 | // reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; |
---|
| 574 | reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; |
---|
| 575 | reg_EVENT_DEPTH [context_id] = depth; |
---|
| 576 | reg_EVENT_FLUSH_ONLY [context_id] = false; |
---|
| 577 | } |
---|
| 578 | } |
---|
| 579 | |
---|
| 580 | // ------------------------------------------------------------------- |
---|
[88] | 581 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
---|
| 582 | // ------------------------------------------------------------------- |
---|
[83] | 583 | |
---|
[88] | 584 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
---|
| 585 | { |
---|
[98] | 586 | log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); |
---|
| 587 | |
---|
[88] | 588 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
---|
| 589 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
---|
[111] | 590 | // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
---|
| 591 | // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
---|
| 592 | // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; |
---|
[88] | 593 | |
---|
[111] | 594 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
---|
| 595 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
---|
| 596 | // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
---|
| 597 | // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
---|
[83] | 598 | |
---|
[88] | 599 | context_state_t state = reg_STATE [context]; |
---|
| 600 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
---|
| 601 | |
---|
[111] | 602 | // // miss > excep > spr/sync |
---|
| 603 | // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or |
---|
| 604 | // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
---|
| 605 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or |
---|
| 606 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or |
---|
| 607 | // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or |
---|
| 608 | // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or |
---|
| 609 | // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
---|
| 610 | // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) |
---|
[88] | 611 | |
---|
[111] | 612 | // // is_valid = can modify local information |
---|
| 613 | // // if context_state_ok : yes |
---|
| 614 | // // if context_state_ko : test the depth, and the priority of envent |
---|
[88] | 615 | |
---|
[111] | 616 | // bool is_valid = ((state == CONTEXT_STATE_OK) or |
---|
| 617 | // (depth1< depth0) or |
---|
| 618 | // ((depth1==depth0) and (priority1>=priority0))); |
---|
[88] | 619 | |
---|
[111] | 620 | // if commit send an event, also they have not yet event previous this instruction |
---|
| 621 | bool is_valid = true; |
---|
| 622 | |
---|
[106] | 623 | log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); |
---|
[111] | 624 | // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); |
---|
| 625 | // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); |
---|
| 626 | // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); |
---|
| 627 | // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); |
---|
| 628 | // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); |
---|
| 629 | // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); |
---|
| 630 | // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); |
---|
[106] | 631 | log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); |
---|
| 632 | |
---|
[88] | 633 | if (is_valid) |
---|
| 634 | { |
---|
| 635 | // commit |
---|
| 636 | // type : exception |
---|
| 637 | context_state_t state_next = state; |
---|
| 638 | switch (type) |
---|
| 639 | { |
---|
[105] | 640 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
---|
[108] | 641 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
| 642 | { |
---|
| 643 | // Test if previous branch occure |
---|
[111] | 644 | switch (state) |
---|
| 645 | { |
---|
| 646 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 647 | { |
---|
| 648 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; |
---|
| 649 | break; |
---|
| 650 | } |
---|
| 651 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 652 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : |
---|
[145] | 653 | case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : |
---|
[111] | 654 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
---|
| 655 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : |
---|
| 656 | { |
---|
[124] | 657 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 658 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; |
---|
| 659 | // #else |
---|
[111] | 660 | state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; |
---|
[124] | 661 | // #endif |
---|
[111] | 662 | break; |
---|
| 663 | } |
---|
| 664 | default : |
---|
| 665 | { |
---|
[124] | 666 | // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 667 | // state_next = CONTEXT_STATE_KO_MISS_LOAD_ADDR; |
---|
| 668 | // #else |
---|
[111] | 669 | state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; |
---|
[124] | 670 | // #endif |
---|
[111] | 671 | break; |
---|
| 672 | } |
---|
| 673 | } |
---|
[123] | 674 | |
---|
| 675 | depth = (depth+1)%_param->_nb_inst_branch_speculated[context]; |
---|
| 676 | |
---|
[108] | 677 | break; |
---|
| 678 | } |
---|
[105] | 679 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
| 680 | case EVENT_TYPE_SPR_ACCESS : |
---|
| 681 | case EVENT_TYPE_MSYNC : |
---|
| 682 | case EVENT_TYPE_PSYNC : |
---|
| 683 | case EVENT_TYPE_CSYNC : |
---|
| 684 | case EVENT_TYPE_NONE : |
---|
| 685 | // case EVENT_TYPE_BRANCH_NO_ACCURATE : |
---|
[88] | 686 | default : |
---|
| 687 | { |
---|
| 688 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
---|
| 689 | } |
---|
| 690 | } |
---|
| 691 | reg_STATE [context] = state_next; |
---|
| 692 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
---|
| 693 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
---|
[105] | 694 | reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
---|
[88] | 695 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
---|
| 696 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
---|
| 697 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
---|
[105] | 698 | reg_EVENT_IS_DS_TAKE [context] = 0; |
---|
[88] | 699 | reg_EVENT_DEPTH [context] = depth; |
---|
[119] | 700 | reg_EVENT_FLUSH_ONLY [context] = false; |
---|
[88] | 701 | } |
---|
| 702 | } |
---|
| 703 | |
---|
| 704 | // ------------------------------------------------------------------- |
---|
| 705 | // -----[ SPR_EVENT ]------------------------------------------------- |
---|
| 706 | // ------------------------------------------------------------------- |
---|
| 707 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 708 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
---|
| 709 | { |
---|
[98] | 710 | log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); |
---|
| 711 | |
---|
[88] | 712 | // Write spr |
---|
[83] | 713 | #ifdef DEBUG_TEST |
---|
[88] | 714 | context_state_t state = reg_STATE [i]; |
---|
| 715 | |
---|
| 716 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
---|
| 717 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
---|
[83] | 718 | #endif |
---|
[88] | 719 | |
---|
| 720 | reg_STATE [i] = CONTEXT_STATE_OK; |
---|
| 721 | } |
---|
[83] | 722 | |
---|
[128] | 723 | // ------------------------------------------------------------------- |
---|
| 724 | // -----[ INTERRUPT ]------------------------------------------------- |
---|
| 725 | // ------------------------------------------------------------------- |
---|
[88] | 726 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 727 | { |
---|
| 728 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 729 | |
---|
| 730 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 731 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 732 | } |
---|
[124] | 733 | |
---|
| 734 | |
---|
| 735 | #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) |
---|
| 736 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 737 | switch (reg_STATE [i]) |
---|
| 738 | { |
---|
| 739 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR ; break; |
---|
| 740 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR ; break; |
---|
| 741 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; break; |
---|
| 742 | default : break; |
---|
| 743 | } |
---|
| 744 | #endif |
---|
[83] | 745 | } |
---|
| 746 | |
---|
[120] | 747 | |
---|
| 748 | #ifdef STATISTICS |
---|
| 749 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
| 750 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 751 | switch(reg_STATE[i]) |
---|
| 752 | { |
---|
| 753 | case CONTEXT_STATE_OK : (*_stat_nb_cycle_state_ok [i])++; break; |
---|
| 754 | |
---|
| 755 | case CONTEXT_STATE_KO_EXCEP : |
---|
| 756 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
---|
| 757 | case CONTEXT_STATE_KO_EXCEP_SPR : (*_stat_nb_cycle_state_ko_excep [i])++; break; |
---|
| 758 | |
---|
[145] | 759 | case CONTEXT_STATE_KO_MISS_BRANCH_INACCURATE : |
---|
[120] | 760 | case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : |
---|
| 761 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : |
---|
| 762 | case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_branch [i])++; break; |
---|
| 763 | |
---|
| 764 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : |
---|
| 765 | case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : (*_stat_nb_cycle_state_ko_miss_load [i])++; break; |
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| 766 | |
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| 767 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE: |
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| 768 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : |
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| 769 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : (*_stat_nb_cycle_state_ko_miss_load_and_branch [i])++; break; |
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| 770 | |
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| 771 | // case CONTEXT_STATE_KO_MSYNC : |
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| 772 | // case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 773 | case CONTEXT_STATE_KO_MSYNC_EXEC : (*_stat_nb_cycle_state_ko_msync [i])++; break; |
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| 774 | |
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| 775 | // case CONTEXT_STATE_KO_PSYNC : |
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| 776 | case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 777 | case CONTEXT_STATE_KO_PSYNC_ADDR : (*_stat_nb_cycle_state_ko_psync [i])++; break; |
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| 778 | |
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| 779 | // case CONTEXT_STATE_KO_CSYNC : |
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| 780 | case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 781 | case CONTEXT_STATE_KO_CSYNC_ADDR : (*_stat_nb_cycle_state_ko_csync [i])++; break; |
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| 782 | |
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| 783 | // case CONTEXT_STATE_KO_SPR : |
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| 784 | // case CONTEXT_STATE_KO_SPR_ISSUE : |
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| 785 | case CONTEXT_STATE_KO_SPR_EXEC : (*_stat_nb_cycle_state_ko_spr [i])++; break; |
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| 786 | } |
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| 787 | #endif |
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| 788 | |
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| 789 | |
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| 790 | |
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[83] | 791 | #if DEBUG >= DEBUG_TRACE |
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| 792 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 793 | { |
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[88] | 794 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
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| 795 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
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| 796 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
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| 797 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
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| 798 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
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| 799 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
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| 800 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
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| 801 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
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| 802 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
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| 803 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
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[119] | 804 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_FLUSH_ONLY : %d" ,reg_EVENT_FLUSH_ONLY [i]); |
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[83] | 805 | } |
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| 806 | #endif |
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| 807 | |
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| 808 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 809 | end_cycle (); |
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| 810 | #endif |
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| 811 | |
---|
| 812 | log_end(Context_State,FUNCTION); |
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| 813 | }; |
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| 814 | |
---|
| 815 | }; // end namespace context_state |
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| 816 | }; // end namespace front_end |
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| 817 | }; // end namespace multi_front_end |
---|
| 818 | }; // end namespace core |
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| 819 | |
---|
| 820 | }; // end namespace behavioural |
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| 821 | }; // end namespace morpheo |
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| 822 | #endif |
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