Changeset 111 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Timestamp:
- Feb 27, 2009, 7:37:40 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/Makefile.deps
r83 r111 16 16 #-----[ Directory ]---------------------------------------- 17 17 18 Context_State_DIR 18 Context_State_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Context_State 19 19 20 20 #-----[ Library ]------------------------------------------ … … 23 23 $(Behavioural_LIBRARY) 24 24 25 Context_State_DIR_LIBRARY 25 Context_State_DIR_LIBRARY = -L$(Context_State_DIR)/lib \ 26 26 $(Behavioural_DIR_LIBRARY) 27 27 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r106 r111 83 83 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 84 84 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); 85 86 87 85 //ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 86 //ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete); 87 //ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete); 88 88 89 89 … … 168 168 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 169 169 INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 170 171 172 170 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); 171 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); 172 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 173 173 174 174 INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context ); … … 1340 1340 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 1341 1341 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 1342 1343 1344 1342 //DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); 1343 //DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); 1344 //DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 1345 1345 DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context ); 1346 1346 DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r105 r111 68 68 //public : SC_IN (Tcontext_t ) ** in_BRANCH_EVENT_CONTEXT_ID ;//[nb_context] 69 69 public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context] 70 //public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context]// always70 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context]// always 71 71 public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] 72 72 public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context]// take or not … … 102 102 public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] 103 103 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] 104 105 106 104 //public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_TAKE ;//[nb_inst_branch_complete] 105 //public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS_SRC ;//[nb_inst_branch_complete] 106 //public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS_DEST ;//[nb_inst_branch_complete] 107 107 108 108 // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r108 r111 25 25 typedef enum 26 26 { 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_BRANCH_ADDR , // update address manager 32 CONTEXT_STATE_KO_MISS_BRANCH_WAITEND, // wait end of event (miss branch) 33 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 34 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 35 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR , // update address manager 36 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND, // wait end of event (miss branch) 37 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 38 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 39 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 40 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 41 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 42 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 43 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 44 CONTEXT_STATE_KO_CSYNC_FLUSH , 45 CONTEXT_STATE_KO_CSYNC_ADDR , 46 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 47 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 48 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE , // branch is complete, wait update by update_prediction_table 32 CONTEXT_STATE_KO_MISS_BRANCH_ADDR , // update address manager 33 CONTEXT_STATE_KO_MISS_BRANCH_WAITEND , // wait end of event (miss branch) 34 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 35 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 36 CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE, // branch is complete, wait update by update_prediction_table 37 CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR , // update address manager 38 CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND , // wait end of event (miss branch) 39 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 40 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 41 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 42 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 43 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 44 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 45 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 46 CONTEXT_STATE_KO_CSYNC_FLUSH , 47 CONTEXT_STATE_KO_CSYNC_ADDR , 48 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 49 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 50 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 49 51 } context_state_t; 50 52 … … 60 62 switch (x) 61 63 { 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 64 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 65 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : return "context_state_ko_miss_branch_and_load_addr" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : return "context_state_ko_miss_branch_and_load_waitend"; break; 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; 72 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 73 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 74 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 75 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 76 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 77 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 78 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 79 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 80 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 81 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 82 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 83 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 64 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 65 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : return "context_state_ko_miss_branch_wait_update" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend" ; break; 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : return "context_state_ko_miss_load_and_branch_wait_update"; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : return "context_state_ko_miss_load_and_branch_addr" ; break; 73 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : return "context_state_ko_miss_load_and_branch_waitend" ; break; 74 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; 76 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 77 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 78 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 79 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 80 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 81 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 82 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 83 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 84 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 85 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 86 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 87 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 84 88 default : return "" ; break; 85 89 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r105 r111 110 110 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 111 111 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"miss_prediction",Tcontrol_t ,1); 112 113 114 112 // ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t ,1); 113 // ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); 114 // ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); 115 115 } 116 116 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r105 r111 63 63 DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); 64 64 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1); 65 DELETE1_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1);66 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address);67 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address);65 // DELETE1_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); 66 // DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 67 // DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 68 68 69 69 DELETE1_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r108 r111 33 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or 34 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or 35 (state == CONTEXT_STATE_KO_MISS_ BRANCH_AND_LOAD_ADDR) or35 (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR) or 36 36 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 37 37 (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or … … 54 54 { 55 55 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 56 case CONTEXT_STATE_KO_MISS_ BRANCH_AND_LOAD_ADDR:56 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: 57 57 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; 58 58 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r108 r111 16 16 namespace context_state { 17 17 18 19 #define get_priority(x) \ 20 (((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \ 21 (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \ 22 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \ 23 (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \ 24 (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \ 25 (((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \ 26 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \ 27 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?2: \ 28 ((state == EVENT_TYPE_EXCEPTION)?1: \ 29 0))) 18 30 19 31 #undef FUNCTION … … 65 77 break; 66 78 } 79 case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : 80 { 81 // nothing : wait end of update upt 82 break; 83 } 67 84 case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : 68 85 { … … 82 99 break; 83 100 } 84 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : 101 case CONTEXT_STATE_KO_EXCEP_SPR : 102 { 103 // nothing, wait the update of internal register (epcr, eear, sr, esr) 104 break; 105 } 106 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 107 { 108 // nothing, wait the update of internal register (pc) 109 break; 110 } 111 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 112 { 113 // nothing, wait the update of internal register (pc) 114 break; 115 } 116 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE : 117 { 118 // nothing : wait end of update upt 119 break; 120 } 121 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : 122 { 123 // nothing, wait the update of internal register (pc) 124 break; 125 } 126 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : 85 127 { 86 128 // Wait end of all instruction … … 88 130 89 131 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 90 state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR; 91 break; 92 } 93 case CONTEXT_STATE_KO_EXCEP_SPR : 94 { 95 // nothing, wait the update of internal register (epcr, eear, sr, esr) 96 break; 97 } 98 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 99 { 100 // nothing, wait the update of internal register (pc) 101 break; 102 } 103 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 104 { 105 // nothing, wait the update of internal register (pc) 106 break; 107 } 108 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : 109 { 110 // nothing, wait the update of internal register (pc) 132 state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; 111 133 break; 112 134 } … … 203 225 204 226 // ------------------------------------------------------------------- 227 // -----[ EVENT ]----------------------------------------------------- 228 // ------------------------------------------------------------------- 229 for (uint32_t i=0; i<_param->_nb_context; i++) 230 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) 231 { 232 log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); 233 // Write pc 234 context_state_t state = reg_STATE [i]; 235 236 switch (state) 237 { 238 case CONTEXT_STATE_KO_EXCEP_ADDR : 239 { 240 reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; 241 break; 242 } 243 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: 244 245 // { 246 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 247 // break; 248 // } 249 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 250 case CONTEXT_STATE_KO_PSYNC_ADDR : 251 case CONTEXT_STATE_KO_CSYNC_ADDR : 252 { 253 reg_STATE [i] = CONTEXT_STATE_OK; 254 break; 255 } 256 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: 257 { 258 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; 259 break; 260 } 261 default : 262 { 263 #ifdef DEBUG_TEST 264 throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); 265 #endif 266 break; 267 } 268 } 269 } 270 271 // ------------------------------------------------------------------- 205 272 // -----[ BRANCH_EVENT ]---------------------------------------------- 206 273 // ------------------------------------------------------------------- … … 222 289 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 223 290 224 // priority : miss > excep > spr/sync 225 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 226 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 227 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 228 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 229 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 230 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 291 // priority : miss_load > miss_branch > excep > spr/sync 292 uint8_t priority0 = get_priority(state); 231 293 uint8_t priority1 = 2; // miss 232 294 … … 235 297 // if context_state_ko : test the depth, and the priority of event 236 298 bool is_valid = ((state == CONTEXT_STATE_OK) or 299 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or 300 (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or 237 301 (depth1< depth0) or 238 302 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 303 304 #ifdef DEBUG_TEST 305 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and 306 (depth0 != depth1)) 307 throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); 308 #endif 239 309 240 310 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); … … 250 320 if (is_valid) 251 321 { 252 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);253 322 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 254 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod) 255 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 256 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next 257 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; 258 //reg_EVENT_ADDRESS_EEAR [i] = 0; 259 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 260 reg_EVENT_IS_DELAY_SLOT [i] = 1; 261 reg_EVENT_IS_DS_TAKE [i] = dest_val; 323 324 if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) 325 { 326 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; 327 } 328 else 329 { 330 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod) 331 332 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 333 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 334 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next 335 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; 336 //reg_EVENT_ADDRESS_EEAR [i] = 0; 337 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 338 reg_EVENT_IS_DELAY_SLOT [i] = 1; 339 reg_EVENT_IS_DS_TAKE [i] = dest_val; 340 reg_EVENT_DEPTH [i] = depth; 341 } 342 } 343 } 344 345 // ------------------------------------------------------------------- 346 // -----[ BRANCH_COMPLETE ]---------------------------------------------- 347 // ------------------------------------------------------------------- 348 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) 349 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i] 350 and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 351 { 352 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); 353 354 context_state_t state = reg_STATE [i]; 355 356 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 357 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 358 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; 359 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; 360 361 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 362 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 363 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 364 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 365 366 // priority : miss_load > miss_branch > excep > spr/sync 367 uint8_t priority0 = get_priority(state); 368 uint8_t priority1 = 2; // miss 369 370 // is_valid = can modify local information 371 // if context_state_ok : yes 372 // if context_state_ko : test the depth, and the priority of event 373 bool is_valid = ((state == CONTEXT_STATE_OK) or 374 (depth1< depth0) or 375 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 376 377 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 378 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 379 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 380 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 381 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 382 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 383 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 384 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 385 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 386 387 if (is_valid) 388 { 389 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 390 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE; 262 391 reg_EVENT_DEPTH [i] = depth; 263 392 } … … 287 416 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); 288 417 289 // miss > excep > spr/sync 290 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 291 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 292 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 293 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 294 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 295 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 418 // miss_load > miss_branch > excep > spr/sync 419 uint8_t priority0 = get_priority(state); 296 420 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 297 421 … … 410 534 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; 411 535 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; 412 Tdepth_t depth_cur = reg_EVENT_DEPTH [context];413 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;414 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];536 // Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 537 // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 538 // Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; 415 539 416 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));417 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));418 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));419 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));540 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 541 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 542 // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 543 // // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 420 544 421 545 context_state_t state = reg_STATE [context]; 422 546 Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); 423 547 424 // miss > excep > spr/sync 425 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 426 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 427 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 428 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 429 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 430 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 431 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 432 433 // is_valid = can modify local information 434 // if context_state_ok : yes 435 // if context_state_ko : test the depth, and the priority of envent 436 437 bool is_valid = ((state == CONTEXT_STATE_OK) or 438 (depth1< depth0) or 439 ((depth1==depth0) and (priority1>=priority0))); 548 // // miss > excep > spr/sync 549 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 550 // (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 551 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or 552 // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 553 // (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or 554 // (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 555 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 556 // uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 557 558 // // is_valid = can modify local information 559 // // if context_state_ok : yes 560 // // if context_state_ko : test the depth, and the priority of envent 561 562 // bool is_valid = ((state == CONTEXT_STATE_OK) or 563 // (depth1< depth0) or 564 // ((depth1==depth0) and (priority1>=priority0))); 565 566 // if commit send an event, also they have not yet event previous this instruction 567 bool is_valid = true; 440 568 441 569 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 442 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );443 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );444 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );445 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );446 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );447 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );448 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );570 // log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 571 // log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 572 // log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 573 // log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 574 // log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 575 // log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 576 // log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 449 577 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 450 578 … … 460 588 { 461 589 // Test if previous branch occure 462 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 463 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 464 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 465 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND)) 466 state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND; 467 else 468 state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; 590 switch (state) 591 { 592 case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE : 593 { 594 state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE; 595 break; 596 } 597 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 598 case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : 599 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR : 600 case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND : 601 { 602 state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; 603 break; 604 } 605 default : 606 { 607 state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; 608 break; 609 } 610 } 469 611 break; 470 612 } … … 494 636 495 637 // ------------------------------------------------------------------- 496 // -----[ EVENT ]-----------------------------------------------------497 // -------------------------------------------------------------------498 for (uint32_t i=0; i<_param->_nb_context; i++)499 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))500 {501 log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);502 // Write pc503 context_state_t state = reg_STATE [i];504 505 switch (state)506 {507 case CONTEXT_STATE_KO_EXCEP_ADDR :508 {509 reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;510 break;511 }512 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:513 514 // {515 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)516 // break;517 // }518 case CONTEXT_STATE_KO_MISS_LOAD_ADDR :519 case CONTEXT_STATE_KO_PSYNC_ADDR :520 case CONTEXT_STATE_KO_CSYNC_ADDR :521 {522 reg_STATE [i] = CONTEXT_STATE_OK;523 break;524 }525 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR:526 {527 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;528 break;529 }530 default :531 {532 #ifdef DEBUG_TEST533 throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));534 #endif535 break;536 }537 }538 }539 540 // -------------------------------------------------------------------541 638 // -----[ SPR_EVENT ]------------------------------------------------- 542 639 // -------------------------------------------------------------------
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