Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Timestamp:
- Feb 12, 2009, 12:55:06 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r105 r108 33 33 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 34 34 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 35 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR , // update address manager 36 CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND, // wait end of event (miss branch) 35 37 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 36 38 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation … … 64 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 65 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : return "context_state_ko_miss_branch_and_load_addr" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : return "context_state_ko_miss_branch_and_load_waitend"; break; 66 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 67 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r105 r108 33 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or 34 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or 35 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR) or 35 36 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 36 37 (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or … … 53 54 { 54 55 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 56 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 55 57 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; 56 58 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r106 r108 82 82 break; 83 83 } 84 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : 85 { 86 // Wait end of all instruction 87 if (inst_all == 0) 88 89 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 90 state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR; 91 break; 92 } 84 93 case CONTEXT_STATE_KO_EXCEP_SPR : 85 94 { … … 93 102 } 94 103 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 104 { 105 // nothing, wait the update of internal register (pc) 106 break; 107 } 108 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR : 95 109 { 96 110 // nothing, wait the update of internal register (pc) … … 209 223 210 224 // priority : miss > excep > spr/sync 211 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 212 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 213 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 214 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 225 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 226 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 227 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 228 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 229 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 230 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 215 231 uint8_t priority1 = 2; // miss 216 232 … … 272 288 273 289 // miss > excep > spr/sync 274 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 275 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 276 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 277 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 290 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 291 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 292 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 293 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 294 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 295 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 278 296 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 279 297 … … 405 423 406 424 // miss > excep > spr/sync 407 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 408 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 409 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 410 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 425 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 426 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 427 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 428 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 429 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or 430 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 411 431 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 412 432 … … 437 457 { 438 458 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 439 case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;} 459 case EVENT_TYPE_LOAD_MISS_SPECULATION : 460 { 461 // Test if previous branch occure 462 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 463 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or 464 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR ) or 465 (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND)) 466 state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND; 467 else 468 state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; 469 break; 470 } 440 471 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 441 472 case EVENT_TYPE_SPR_ACCESS : … … 480 511 } 481 512 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: 513 482 514 // { 483 515 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) … … 489 521 { 490 522 reg_STATE [i] = CONTEXT_STATE_OK; 523 break; 524 } 525 case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 526 { 527 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR; 491 528 break; 492 529 }
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