Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop
- Timestamp:
- May 16, 2009, 4:42:39 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop
- Files:
-
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp
r116 r117 26 26 log_function(Functionnal_unit,FUNCTION,_name.c_str()); 27 27 28 { 29 internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0)); 30 31 PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); 32 } 33 34 { 35 internal_EXECUTE_IN_ACK = (not reg_BUSY_IN or 36 (reg_BUSY_IN and (not reg_BUSY_OUT or 37 (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))))); 38 39 PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); 40 } 28 if (PORT_READ(in_NRESET) != 0) 29 { 30 { 31 internal_EXECUTE_OUT_VAL = (reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0)); 32 33 PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); 34 } 35 36 { 37 internal_EXECUTE_IN_ACK = (not reg_BUSY_IN or 38 (reg_BUSY_IN and (not reg_BUSY_OUT or 39 (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))))); 40 41 PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); 42 } 43 } 41 44 42 45 log_end(Functionnal_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
r116 r117 60 60 61 61 if (reg_BUSY_IN and not reg_BUSY_OUT) 62 // if (not reg_BUSY_OUT_old or)63 62 { 64 63 reg_BUSY_OUT = reg_BUSY_IN; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
r113 r117 70 70 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 71 71 72 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 72 sc_signal<Tcontrol_t > ** in_MEMORY_IN_VAL ; 73 sc_signal<Tcontrol_t > ** out_MEMORY_IN_ACK ; 74 sc_signal<Tcontext_t > ** in_MEMORY_IN_CONTEXT_ID ; 75 sc_signal<Tcontext_t > ** in_MEMORY_IN_FRONT_END_ID ; 76 sc_signal<Tcontext_t > ** in_MEMORY_IN_OOO_ENGINE_ID ; 77 sc_signal<Tpacket_t > ** in_MEMORY_IN_PACKET_ID ; 78 sc_signal<Toperation_t > ** in_MEMORY_IN_OPERATION ; 79 sc_signal<Ttype_t > ** in_MEMORY_IN_TYPE ; 80 sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; 81 sc_signal<Tlsq_ptr_t > ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; 82 sc_signal<Tcontrol_t > ** in_MEMORY_IN_HAS_IMMEDIAT ; 83 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_IMMEDIAT ; 84 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RA ; 85 sc_signal<Tgeneral_data_t > ** in_MEMORY_IN_DATA_RB ; 86 sc_signal<Tspecial_data_t > ** in_MEMORY_IN_DATA_RC ; 87 sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RD ; 88 sc_signal<Tgeneral_address_t> ** in_MEMORY_IN_NUM_REG_RD ; 89 sc_signal<Tcontrol_t > ** in_MEMORY_IN_WRITE_RE ; 90 sc_signal<Tspecial_address_t> ** in_MEMORY_IN_NUM_REG_RE ; 91 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_VAL ; 92 sc_signal<Tcontrol_t > ** in_MEMORY_OUT_ACK ; 93 sc_signal<Tcontext_t > ** out_MEMORY_OUT_CONTEXT_ID ; 94 sc_signal<Tcontext_t > ** out_MEMORY_OUT_FRONT_END_ID ; 95 sc_signal<Tcontext_t > ** out_MEMORY_OUT_OOO_ENGINE_ID ; 96 sc_signal<Tpacket_t > ** out_MEMORY_OUT_PACKET_ID ; 97 //sc_signal<Toperation_t > ** out_MEMORY_OUT_OPERATION ; 98 //sc_signal<Ttype_t > ** out_MEMORY_OUT_TYPE ; 99 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RD ; 100 sc_signal<Tgeneral_address_t> ** out_MEMORY_OUT_NUM_REG_RD ; 101 sc_signal<Tgeneral_data_t > ** out_MEMORY_OUT_DATA_RD ; 102 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_WRITE_RE ; 103 sc_signal<Tspecial_address_t> ** out_MEMORY_OUT_NUM_REG_RE ; 104 sc_signal<Tspecial_data_t > ** out_MEMORY_OUT_DATA_RE ; 105 sc_signal<Texception_t > ** out_MEMORY_OUT_EXCEPTION ; 106 sc_signal<Tcontrol_t > ** out_MEMORY_OUT_NO_SEQUENCE ; 107 sc_signal<Taddress_t > ** out_MEMORY_OUT_ADDRESS ; 108 sc_signal<Tcontrol_t > ** out_DCACHE_REQ_VAL ; 109 sc_signal<Tcontrol_t > ** in_DCACHE_REQ_ACK ; 110 sc_signal<Tcontext_t > ** out_DCACHE_REQ_CONTEXT_ID ; 111 sc_signal<Tpacket_t > ** out_DCACHE_REQ_PACKET_ID ; 112 sc_signal<Tdcache_address_t > ** out_DCACHE_REQ_ADDRESS ; 113 sc_signal<Tdcache_type_t > ** out_DCACHE_REQ_TYPE ; 114 sc_signal<Tdcache_data_t > ** out_DCACHE_REQ_WDATA ; 115 sc_signal<Tcontrol_t > ** in_DCACHE_RSP_VAL ; 116 sc_signal<Tcontrol_t > ** out_DCACHE_RSP_ACK ; 117 sc_signal<Tcontext_t > ** in_DCACHE_RSP_CONTEXT_ID ; 118 sc_signal<Tpacket_t > ** in_DCACHE_RSP_PACKET_ID ; 119 sc_signal<Tdcache_data_t > ** in_DCACHE_RSP_RDATA ; 120 sc_signal<Tdcache_error_t > ** in_DCACHE_RSP_ERROR ; 121 sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL ; 122 sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID ; 123 sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG ; 124 sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA ; 125 73 126 ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory); 74 127 ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory); … … 379 432 tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp 380 433 381 const uint32_t nb_request = 64;//_param->_nb_packet; 434 const uint32_t nb_request = 66;//_param->_nb_packet; 435 // const uint32_t nb_request = 64;//_param->_nb_packet; 382 436 383 437 for (uint32_t i=0; i<nb_request; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r110 r117 157 157 158 158 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 159 protected : Tstore_queue_entry_t * _store_queue ;160 protected : Tload_queue_entry_t * _load_queue ;161 protected : Tspeculative_access_queue_entry_t * _speculative_access_queue ;159 protected : Tstore_queue_entry_t * _store_queue ;//[size_store_queue] 160 protected : Tload_queue_entry_t * _load_queue ;//[size_load_queue] 161 protected : Tspeculative_access_queue_entry_t * _speculative_access_queue ;//[size_speculative_access_queue] 162 162 protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control; 163 163 … … 174 174 175 175 // Registers 176 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ; 177 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; 178 public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY ; 176 public : Tlsq_ptr_t * reg_STORE_QUEUE_NB_CHECK ;//[size_store_queue] 177 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ ; 178 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; 179 public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY; 179 180 180 181 // signal -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r112 r117 146 146 147 147 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 148 if (usage_is_set(_usage,USE_SYSTEMC)) 149 { 150 _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue); 148 151 149 // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; 152 ALLOC1(_store_queue ,Tstore_queue_entry_t ,_param->_size_store_queue); 153 ALLOC1(_load_queue ,Tload_queue_entry_t ,_param->_size_load_queue); 154 ALLOC1(_speculative_access_queue,Tspeculative_access_queue_entry_t,_param->_size_speculative_access_queue); 150 155 151 // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; 152 // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; 153 // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; 154 // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; 155 156 // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; 157 // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; 158 // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; 156 ALLOC1(reg_STORE_QUEUE_NB_CHECK ,Tlsq_ptr_t ,_param->_size_store_queue); 157 158 // ALLOC1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,Tlsq_ptr_t ,_param->_nb_cache_port); 159 160 // ALLOC1(internal_MEMORY_IN_ACK ,Tcontrol_t ,_param->_nb_inst_memory); 161 // ALLOC1(internal_MEMORY_OUT_VAL ,Tcontrol_t ,_param->_nb_inst_memory); 162 // ALLOC1(internal_MEMORY_OUT_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_inst_memory); 163 // ALLOC1(internal_MEMORY_OUT_PTR ,Tlsq_ptr_t ,_param->_nb_inst_memory); 164 165 // ALLOC1(internal_DCACHE_RSP_ACK ,Tcontrol_t ,_param->_nb_cache_port ); 166 // ALLOC1(internal_DCACHE_REQ_VAL ,Tcontrol_t ,_param->_nb_cache_port ); 167 // ALLOC1(internal_DCACHE_REQ_SELECT_QUEUE ,Tselect_queue_t,_param->_nb_cache_port ); 168 } 159 169 160 170 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 164 174 _component->generate_file(); 165 175 #endif 166 167 _store_queue = new Tstore_queue_entry_t [_param->_size_store_queue];168 _load_queue = new Tload_queue_entry_t [_param->_size_load_queue];169 _speculative_access_queue = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];170 _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);171 176 172 177 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
r97 r117 95 95 96 96 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 97 delete _speculative_access_queue_control ; 97 98 98 // delete [] internal_MEMORY_IN_ACK ; 99 // delete [] internal_MEMORY_OUT_VAL ; 100 // delete [] internal_MEMORY_OUT_SELECT_QUEUE; 101 // delete [] internal_MEMORY_OUT_PTR ; 102 103 // delete [] internal_DCACHE_RSP_ACK ; 104 // delete [] internal_DCACHE_REQ_VAL ; 105 // delete [] internal_DCACHE_REQ_SELECT_QUEUE; 99 DELETE1(_store_queue ,_param->_size_store_queue); 100 DELETE1(_load_queue ,_param->_size_load_queue); 101 DELETE1(_speculative_access_queue,_param->_size_speculative_access_queue); 106 102 107 // delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ; 103 DELETE1(reg_STORE_QUEUE_NB_CHECK ,_param->_size_store_queue); 104 105 // DELETE1(internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ,_param->_nb_cache_port); 106 107 // DELETE1(internal_MEMORY_IN_ACK ,_param->_nb_inst_memory); 108 // DELETE1(internal_MEMORY_OUT_VAL ,_param->_nb_inst_memory); 109 // DELETE1(internal_MEMORY_OUT_SELECT_QUEUE ,_param->_nb_inst_memory); 110 // DELETE1(internal_MEMORY_OUT_PTR ,_param->_nb_inst_memory); 111 112 // DELETE1(internal_DCACHE_RSP_ACK ,_param->_nb_cache_port ); 113 // DELETE1(internal_DCACHE_REQ_VAL ,_param->_nb_cache_port ); 114 // DELETE1(internal_DCACHE_REQ_SELECT_QUEUE ,_param->_nb_cache_port ); 108 115 } 109 116 … … 112 119 delete _component; 113 120 114 delete [] _store_queue ;115 delete [] _load_queue ;116 delete _speculative_access_queue_control ;117 delete [] _speculative_access_queue ;118 121 119 122 log_printf(FUNC,Load_store_unit,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r104 r117 98 98 { 99 99 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); 100 if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) 100 // Can retire an store instruction if : 101 // * state is commit 102 // * none load must check this store 103 if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and 104 (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0)) 101 105 { 102 106 log_printf(TRACE,Load_store_unit,FUNCTION," * find : %d",reg_STORE_QUEUE_PTR_READ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r112 r117 242 242 243 243 for (uint32_t i=0; i< _param->_size_store_queue ; i++) 244 { 245 reg_STORE_QUEUE_NB_CHECK [i] = 0; 244 246 _store_queue [i]._state = STORE_QUEUE_EMPTY; 247 } 245 248 246 249 for (uint32_t i=0; i< _param->_size_load_queue ; i++) … … 252 255 else 253 256 { 257 //================================================================ 258 // Interface "MEMORY_OUT" 259 //================================================================ 260 261 if (( internal_MEMORY_OUT_VAL == 1) and 262 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 263 { 264 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); 265 266 switch (internal_MEMORY_OUT_SELECT_QUEUE) 267 { 268 case SELECT_STORE_QUEUE : 269 { 270 // ======================= 271 // ===== STORE_QUEUE ===== 272 // ======================= 273 274 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); 275 276 // Entry flush and increase the read pointer 277 _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; 278 279 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; 280 281 break; 282 } 283 case SELECT_LOAD_QUEUE : 284 { 285 // ====================== 286 // ===== LOAD_QUEUE ===== 287 // ====================== 288 289 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); 290 291 // Entry flush and increase the read pointer 292 293 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY; 294 295 // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; 296 297 break; 298 } 299 case SELECT_LOAD_QUEUE_SPECULATIVE : 300 { 301 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); 302 303 // !!! WARNING !!! 304 // !!! Test special case : 305 // !!! in a cycle an instruction can check the last store AND commit instruction 306 // !!! also the memory_out is before the port_check 307 308 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; 309 // NOTE : a speculative load write in the register file. 310 // if the speculation is a miss, write_rd is re set at 1. 311 _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; 312 313 #ifdef STATISTICS 314 if (usage_is_set(_usage,USE_STATISTICS)) 315 (*_stat_nb_inst_load_commit_speculative) ++; 316 #endif 317 318 break; 319 } 320 321 break; 322 } 323 } 324 254 325 //================================================================ 255 326 // Interface "PORT_CHECK" … … 278 349 279 350 // find a entry that it need a check 280 Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; 351 Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; 352 Tlsq_ptr_t index_store_old = index_store; 353 281 354 // Init variable 282 355 bool end_check = false; … … 534 607 // The check is finish if all bit is set 535 608 end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte); 609 536 610 } 537 611 } … … 553 627 log_printf(TRACE,Load_store_unit,FUNCTION," * next"); 554 628 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); 629 630 log_printf(TRACE,Load_store_unit,FUNCTION," * update reg_STORE_QUEUE_NB_CHECK"); 631 #ifdef DEBUG 632 if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0) 633 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 634 #endif 635 reg_STORE_QUEUE_NB_CHECK [index_store] --; 636 555 637 // if (_load_queue[index_load]._store_queue_ptr_write == 0) 556 638 // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; … … 615 697 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); 616 698 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); 699 700 if (end_check) 701 { 702 log_printf(TRACE,Load_store_unit,FUNCTION," * end check, decrease all nb_check"); 703 704 uint32_t i=index_store; 705 while (i!=reg_STORE_QUEUE_PTR_READ) 706 { 707 i=((i==0)?_param->_size_store_queue:i)-1; 708 709 #ifdef DEBUG 710 if (reg_STORE_QUEUE_NB_CHECK [i] == 0) 711 throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n")); 712 #endif 713 714 reg_STORE_QUEUE_NB_CHECK [i] --; 715 //i=(i+1)%_param->_size_store_queue; 716 } 717 } 617 718 } 618 719 } … … 803 904 804 905 //================================================================ 805 // Interface "MEMORY_OUT"806 //================================================================807 808 if (( internal_MEMORY_OUT_VAL == 1) and809 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))810 {811 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction");812 813 switch (internal_MEMORY_OUT_SELECT_QUEUE)814 {815 case SELECT_STORE_QUEUE :816 {817 // =======================818 // ===== STORE_QUEUE =====819 // =======================820 821 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);822 823 // Entry flush and increase the read pointer824 _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;825 826 reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;827 828 break;829 }830 case SELECT_LOAD_QUEUE :831 {832 // ======================833 // ===== LOAD_QUEUE =====834 // ======================835 836 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR);837 838 // Entry flush and increase the read pointer839 840 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;841 842 // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;843 844 break;845 }846 case SELECT_LOAD_QUEUE_SPECULATIVE :847 {848 log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR);849 850 _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK;851 // NOTE : a speculative load write in the register file.852 // if the speculation is a miss, write_rd is re set at 1.853 _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;854 855 #ifdef STATISTICS856 if (usage_is_set(_usage,USE_STATISTICS))857 (*_stat_nb_inst_load_commit_speculative) ++;858 #endif859 860 break;861 }862 863 break;864 }865 }866 867 //================================================================868 906 // Interface "DCACHE_REQ" 869 907 //================================================================ … … 943 981 Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); 944 982 Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; 983 Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; 945 984 946 985 log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); … … 955 994 _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id; 956 995 _load_queue [ptr_write]._operation = operation; 957 _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;996 _load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write; 958 997 _load_queue [ptr_write]._address = address; 959 998 _load_queue [ptr_write]._check_hit_byte = check_hit_byte; … … 964 1003 // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. 965 1004 _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; 966 967 1005 _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; 968 1006 _load_queue [ptr_write]._exception = exception; … … 980 1018 (*_stat_nb_inst_load) ++; 981 1019 #endif 1020 1021 // Only load need check 1022 if (is_operation_memory_load(_load_queue [ptr_write]._operation)) 1023 { 1024 log_printf(TRACE,Load_store_unit,FUNCTION," * update nb_check"); 1025 log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write); 1026 log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ); 1027 1028 uint32_t i=store_queue_ptr_write; 1029 while (i!=reg_STORE_QUEUE_PTR_READ) 1030 { 1031 i=((i==0)?_param->_size_store_queue:i)-1; 1032 1033 log_printf(TRACE,Load_store_unit,FUNCTION," * i : %d",i); 1034 1035 reg_STORE_QUEUE_NB_CHECK [i] ++; 1036 } 1037 } 982 1038 } 983 1039 … … 1075 1131 uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; 1076 1132 1077 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, % s",1133 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s", 1078 1134 j, 1079 1135 _store_queue[j]._context_id , … … 1088 1144 //_store_queue[j]._num_reg_rd , 1089 1145 _store_queue[j]._exception , 1146 reg_STORE_QUEUE_NB_CHECK [j] , 1090 1147 toString(_store_queue[j]._state).c_str()); 1091 1148 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
r104 r117 58 58 59 59 _size_dcache_context_id = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine); 60 _size_dcache_packet_id = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1; 61 60 _size_dcache_packet_id = log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue)+1; 62 61 _have_port_dcache_context_id = _size_dcache_context_id>0; 63 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h
r98 r117 121 121 _immediat = x._immediat ; 122 122 _read_ra = x._read_ra ; 123 _read_ra_val = x._read_ra == 1; //if not must read, the registerFile is already access123 _read_ra_val = ((x._read_ra == 1) and (x._num_reg_ra != 0)); //if not must read, the registerFile is already access 124 124 _num_reg_ra = x._num_reg_ra ; 125 _data_ra_val = ((x._read_ra == 0) or (x._num_reg_ra == 0)); //if not must read, the data is already valid 125 // _data_ra_val = ((x._read_ra == 0) or (x._num_reg_ra == 0)); //if not must read, the data is already valid 126 _data_ra_val = not _read_ra_val; 126 127 _data_ra = 0 ; 127 128 _read_rb = x._read_rb ; 128 _read_rb_val = x._read_rb == 1;129 _read_rb_val = ((x._read_rb == 1) and (x._num_reg_rb != 0)); 129 130 _num_reg_rb = x._num_reg_rb ; 130 _data_rb_val = ((x._read_rb == 0) or (x._num_reg_rb == 0)); 131 // _data_rb_val = ((x._read_rb == 0) or (x._num_reg_rb == 0)); 132 _data_rb_val = not _read_rb_val; 131 133 _data_rb = 0 ; 132 134 _read_rc = x._read_rc ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp
r112 r117 65 65 66 66 if(_param->_have_port_context_id ) 67 67 entry->_context_id = PORT_READ(in_READ_QUEUE_IN_CONTEXT_ID ); 68 68 if(_param->_have_port_front_end_id ) 69 69 entry->_front_end_id = PORT_READ(in_READ_QUEUE_IN_FRONT_END_ID); 70 70 if(_param->_have_port_ooo_engine_id) 71 71 entry->_ooo_engine_id= PORT_READ(in_READ_QUEUE_IN_OOO_ENGINE_ID); 72 72 if(_param->_have_port_rob_ptr ) 73 73 entry->_rob_id = PORT_READ(in_READ_QUEUE_IN_ROB_ID ); 74 74 entry->_operation = PORT_READ(in_READ_QUEUE_IN_OPERATION ); 75 75 entry->_type = PORT_READ(in_READ_QUEUE_IN_TYPE ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp
r115 r117 100 100 internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty() ) and 101 101 (not _queue->front()->_write_rd) and 102 (not _queue->front()->_write_re)); 102 (not _queue->front()->_write_re) and 103 (_queue->front()->_exception != EXCEPTION_MEMORY_LOAD_SPECULATIVE) 104 ); 103 105 104 106 PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp
r97 r117 22 22 void Read_unit_to_Execution_unit::genMealy (void) 23 23 { 24 log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); 24 log_begin(Read_unit_to_Execution_unit,FUNCTION); 25 log_function(Read_unit_to_Execution_unit,FUNCTION,_name.c_str()); 25 26 26 27 bool execute_unit_use [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port]; … … 35 36 bool ack = false; 36 37 37 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," Test Read_unit[%d][%d]",i,j);38 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test Read_unit[%d][%d]",i,j); 38 39 39 40 if (PORT_READ(in_READ_UNIT_OUT_VAL [i][j]) == true) 40 41 { 41 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"* have a valid entry.");42 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * have a valid entry."); 42 43 43 44 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i][j]):0; … … 51 52 #ifdef DEBUG_TEST 52 53 if (_destination[i][num_thread][type].empty()) 53 throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString(type)+"].");54 throw ERRORMORPHEO(FUNCTION,toString(_("Invalid Operation : They have no execute_unit to receive a operation from the read_unit [%d], thread [%d] and a operation's type [%s]."),i,num_thread,toString(type).c_str())); 54 55 #endif 55 56 … … 62 63 uint32_t port = (*it).elt; 63 64 64 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d][%d].",dest,port);65 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d][%d].",dest,port); 65 66 66 67 if (execute_unit_use [dest][port] == false) 67 68 { 68 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"* Is ok! Link.");69 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Is ok! Link."); 69 70 70 71 // have find !!! … … 104 105 PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i][j], execute_unit_use[i][j]); 105 106 106 log_ printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End");107 log_end(Read_unit_to_Execution_unit,FUNCTION); 107 108 }; 108 109 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
r115 r117 531 531 } 532 532 533 _have_port_dcache_context_id = (_max_size_dcache_context_id>1); 534 533 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : size_dcache_context_id : %d",_max_size_dcache_context_id ); 534 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : size_dcache_packet_id : %d",_max_size_dcache_packet_id ); 535 536 _have_port_dcache_context_id = (_max_size_dcache_context_id>0); 537 538 // log_printf(TRACE,Load_store_unit,FUNCTION,"kane : have_port_dcache_context_id : %d",_have_port_dcache_context_id); 535 539 536 540 if (is_toplevel)
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