- Timestamp:
- Oct 13, 2010, 8:15:51 PM (14 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine
- Files:
-
- 4 added
- 41 edited
- 39 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r142 r145 74 74 public : counter_t ** _stat_nb_cycle_state_wait_end ;//[nb_thread] 75 75 76 // 76 //public : uint32_t * _stat_last_inst ;//[nb_thread] 77 77 public : uint32_t * _stat_last_inst_type ;//[nb_thread] 78 78 public : uint32_t * _stat_last_inst_operation ;//[nb_thread] … … 97 97 //public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_insert] 98 98 public : SC_IN (Tdepth_t ) *** in_INSERT_DEPTH ;//[nb_rename_unit][nb_inst_insert] 99 public : SC_IN (Tcontrol_t ) *** in_INSERT_SAVE_RAT ;//[nb_rename_unit][nb_inst_insert] 99 100 #ifdef STATISTICS 100 101 public : SC_IN (uint32_t ) *** in_INSERT_INSTRUCTION ;//[nb_rename_unit][nb_inst_insert] … … 141 142 public : SC_OUT(Tcontext_t ) *** out_RETIRE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_retire] 142 143 //public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_retire] 144 //public : SC_OUT(Tdepth_t ) *** out_RETIRE_DEPTH ;//[nb_rename_unit][nb_inst_retire] 143 145 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_STORE_QUEUE ;//[nb_rename_unit][nb_inst_retire] 144 146 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_LOAD_QUEUE ;//[nb_rename_unit][nb_inst_retire] … … 234 236 public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] 235 237 236 237 238 239 238 // // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 239 //public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] 240 //public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] 241 //public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] 240 242 241 243 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 272 274 private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] 273 275 private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 276 private : Tcounter_t *** reg_NB_INST_DEPTH ;//[nb_front_end][nb_context][nb_branch_speculated] 274 277 275 278 private : Tcommit_event_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
r139 r145 24 24 { 25 25 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _nb_front_end ; 27 public : uint32_t * _nb_context ;//[nb_front_end] 28 public : uint32_t _nb_rename_unit ; 29 public : uint32_t _size_queue ; 30 public : uint32_t _nb_bank ; 31 public : Tretire_ooo_scheme_t _retire_ooo_scheme ; 32 public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] 33 public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] 34 public : uint32_t _nb_inst_commit ; 35 public : uint32_t _nb_inst_reexecute ; 36 public : uint32_t _nb_inst_branch_complete ; 37 public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] 38 //public : uint32_t _size_general_data ; 39 //public : uint32_t _size_store_queue_ptr ; 40 //public : uint32_t _size_load_queue_ptr ; 41 //public : uint32_t _size_general_register ; 42 //public : uint32_t _size_special_register ; 43 public : Trat_scheme_t * _rat_scheme ;//[nb_front_end] 44 public : Tpriority_t _priority ; 45 public : Tload_balancing_t _load_balancing ; 46 public : uint32_t _nb_rename_unit_select ; 47 public : uint32_t _nb_thread ; 48 public : uint32_t ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context] 49 public : const uint32_t _nb_bank_access_commit ; 26 public : uint32_t _nb_front_end ; 27 public : uint32_t * _nb_context ;//[nb_front_end] 28 public : uint32_t _nb_rename_unit ; 29 public : uint32_t _size_queue ; 30 public : uint32_t _nb_bank ; 31 public : Tretire_ooo_scheme_t _retire_ooo_scheme ; 32 public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] 33 public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] 34 public : uint32_t _nb_inst_commit ; 35 public : uint32_t _nb_inst_reexecute ; 36 public : uint32_t _nb_inst_branch_complete ; 37 public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] 38 //public : uint32_t _size_general_data ; 39 //public : uint32_t _size_store_queue_ptr ; 40 //public : uint32_t _size_load_queue_ptr ; 41 //public : uint32_t _size_general_register ; 42 //public : uint32_t _size_special_register ; 43 public : Trat_scheme_t * _rat_scheme ;//[nb_rename_unit] 44 public : std::vector<uint32_t>* _link_front_end_with_rename_unit ;//[nb_rename_unit] 50 45 51 public : uint32_t _max_nb_context ; 52 public : uint32_t _max_nb_inst_insert ; 53 public : uint32_t _max_nb_inst_retire ; 54 //public : uint32_t _size_address ; 55 //public : uint32_t _size_front_end_id ; 56 //public : uint32_t _size_context_id ; 57 public : uint32_t _size_rename_unit_id ; 58 public : uint32_t _size_bank ; 59 //public : uint32_t _size_nb_inst ; 60 //public : uint32_t _size_packet_id ; 61 public : uint32_t ** _array_size_depth ;//[nb_front_end][nb_context] 62 //public : uint32_t _max_size_depth ; 63 64 //public : Tpacket_t _shift_num_bank ; 65 public : Tpacket_t _mask_num_bank ; 66 public : Tpacket_t _shift_num_slot ; 67 //public : Tpacket_t _mask_num_slot ; 46 public : Tpriority_t _priority ; 47 public : Tload_balancing_t _load_balancing ; 48 public : uint32_t _nb_rename_unit_select ; 49 public : uint32_t _nb_thread ; 50 public : uint32_t ** _translate_num_context_to_num_thread;//[nb_front_end][nb_context] 51 public : Trat_scheme_t * _front_end_rat_scheme ;//[nb_front_end] 52 public : const uint32_t _nb_bank_access_commit ; 53 54 public : uint32_t _max_nb_context ; 55 public : uint32_t _max_nb_inst_insert ; 56 public : uint32_t _max_nb_inst_retire ; 57 //public : uint32_t _size_address ; 58 //public : uint32_t _size_front_end_id ; 59 //public : uint32_t _size_context_id ; 60 public : uint32_t _size_rename_unit_id ; 61 public : uint32_t _size_bank ; 62 //public : uint32_t _size_nb_inst ; 63 //public : uint32_t _size_packet_id ; 64 public : uint32_t ** _array_size_depth ;//[nb_front_end][nb_context] 65 //public : uint32_t _max_size_depth ; 66 67 //public : Tpacket_t _shift_num_bank ; 68 public : Tpacket_t _mask_num_bank ; 69 public : Tpacket_t _shift_num_slot ; 70 //public : Tpacket_t _mask_num_slot ; 68 71 69 72 … … 79 82 80 83 //-----[ methods ]----------------------------------------------------------- 81 public : Parameters (uint32_t nb_front_end , 82 uint32_t * nb_context ,//[nb_front_end] 83 uint32_t nb_rename_unit , 84 uint32_t size_queue , 85 uint32_t nb_bank , 86 Tretire_ooo_scheme_t retire_ooo_scheme , 87 uint32_t * nb_inst_insert ,//[nb_rename_unit] 88 uint32_t * nb_inst_retire ,//[nb_rename_unit] 89 uint32_t nb_inst_commit , 90 uint32_t nb_inst_reexecute , 91 uint32_t nb_inst_branch_complete , 92 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 93 uint32_t size_nb_inst_decod , 94 uint32_t size_general_data , 95 uint32_t size_store_queue_ptr , 96 uint32_t size_load_queue_ptr , 97 uint32_t size_general_register , 98 uint32_t size_special_register , 99 Trat_scheme_t * rat_scheme ,//[nb_front_end] 100 Tpriority_t priority , 101 Tload_balancing_t load_balancing , 102 uint32_t nb_rename_unit_select , 103 uint32_t nb_thread , 104 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 105 bool is_toplevel=false 84 public : Parameters (uint32_t nb_front_end , 85 uint32_t * nb_context ,//[nb_front_end] 86 uint32_t nb_rename_unit , 87 uint32_t size_queue , 88 uint32_t nb_bank , 89 Tretire_ooo_scheme_t retire_ooo_scheme , 90 uint32_t * nb_inst_insert ,//[nb_rename_unit] 91 uint32_t * nb_inst_retire ,//[nb_rename_unit] 92 uint32_t nb_inst_commit , 93 uint32_t nb_inst_reexecute , 94 uint32_t nb_inst_branch_complete , 95 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 96 uint32_t size_nb_inst_decod , 97 uint32_t size_general_data , 98 uint32_t size_store_queue_ptr , 99 uint32_t size_load_queue_ptr , 100 uint32_t size_general_register , 101 uint32_t size_special_register , 102 Trat_scheme_t * rat_scheme ,//[nb_rename_unit] 103 std::vector<uint32_t>* link_front_end_with_rename_unit ,//[nb_rename_unit] 104 Tpriority_t priority , 105 Tload_balancing_t load_balancing , 106 uint32_t nb_rename_unit_select , 107 uint32_t nb_thread , 108 uint32_t ** translate_num_context_to_num_thread, //[nb_front_end][nb_context] 109 bool is_toplevel=false 106 110 ); 107 111 // public : Parameters (Parameters & param) ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r139 r145 81 81 public : rob_state_t state ; 82 82 public : rob_state_t state_old ; 83 //public : Tcontrol_t restore ; 84 83 85 public : uint32_t ptr ; 84 86 public : Tcontext_t front_end_id ; … … 207 209 }; 208 210 211 template<> inline std::string toString<morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t>(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Tcommit_event_state_t& x) 212 { 213 switch (x) 214 { 215 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NO_EVENT : return "COMMIT_EVENT_STATE_NO_EVENT" ; break; 216 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_NOT_YET_EVENT : return "COMMIT_EVENT_STATE_NOT_YET_EVENT"; break; 217 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_EVENT : return "COMMIT_EVENT_STATE_EVENT" ; break; 218 // case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_DECOD : return "COMMIT_EVENT_STATE_WAIT_DECOD" ; break; 219 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_WAIT_END : return "COMMIT_EVENT_STATE_WAIT_END" ; break; 220 // case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::COMMIT_EVENT_STATE_END : return "COMMIT_EVENT_STATE_END" ; break; 221 222 default : return "" ; break; 223 } 224 }; 225 226 209 227 }; // end namespace morpheo 210 228 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp
r132 r145 115 115 sensitive << (*(in_CLOCK)).neg() // need internal register 116 116 << (*(in_NRESET)); 117 118 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 119 if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE) 120 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) 121 { 122 if (_param->_have_port_front_end_id ) 123 sensitive << (*(in_INSERT_FRONT_END_ID [i][j])); 124 if (_param->_have_port_context_id ) 125 sensitive << (*(in_INSERT_CONTEXT_ID [i][j])); 126 if (_param->_have_port_depth) 127 sensitive << (*(in_INSERT_DEPTH [i][j])); 128 sensitive << (*(in_INSERT_SAVE_RAT [i][j])); 129 } 130 131 117 132 // for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 118 133 // for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r139 r145 59 59 ALLOC2_INTERFACE_BEGIN("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 60 60 61 _ALLOC2_VALACK_IN ( in_INSERT_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 62 _ALLOC2_VALACK_OUT(out_INSERT_ACK ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 63 _ALLOC2_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 64 _ALLOC2_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 65 _ALLOC2_SIGNAL_OUT(out_INSERT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 66 // _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 67 _ALLOC2_SIGNAL_IN ( in_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 68 #ifdef STATISTICS 69 _ALLOC2_SIGNAL_IN ( in_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 70 #endif 71 _ALLOC2_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 _ALLOC2_SIGNAL_IN ( in_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 76 #ifdef DEBUG 77 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 78 #endif 79 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 80 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 81 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 82 _ALLOC2_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 83 _ALLOC2_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 84 #ifdef DEBUG 85 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 86 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 87 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 88 #endif 89 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 90 #ifdef DEBUG 91 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 92 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 93 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 94 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 95 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 96 #endif 97 _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 98 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 99 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 100 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 101 _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 102 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 103 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 104 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 61 _ALLOC2_VALACK_IN ( in_INSERT_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 62 _ALLOC2_VALACK_OUT (out_INSERT_ACK ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 63 _ALLOC2_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 64 _ALLOC2_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 65 _ALLOC2_SIGNAL_OUT (out_INSERT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 66 // _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 67 _ALLOC2_SIGNAL_IN ( in_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 68 _ALLOC2_SIGNAL_IN_COND ( in_INSERT_SAVE_RAT ,"save_rat" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE); 69 #ifdef STATISTICS 70 _ALLOC2_SIGNAL_IN ( in_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 71 #endif 72 _ALLOC2_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 _ALLOC2_SIGNAL_IN ( in_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 76 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 77 #ifdef DEBUG 78 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 79 #endif 80 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 81 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 82 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 83 _ALLOC2_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 84 _ALLOC2_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 85 #ifdef DEBUG 86 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 87 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 88 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 89 #endif 90 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 91 #ifdef DEBUG 92 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 93 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 94 _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 95 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 96 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 97 #endif 98 _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 99 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 100 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 101 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 102 _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 103 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 104 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 105 _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 105 106 106 107 ALLOC2_INTERFACE_END(_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 116 117 _ALLOC2_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 117 118 // _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 119 // _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_rat_scheme[it1] == RAT_DEPTH_SAVE); 118 120 _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); 119 121 _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); … … 150 152 // _ALLOC2_SIGNAL_OUT (out_RETIRE_EVENT_FLUSH ,"flush" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 151 153 _ALLOC2_SIGNAL_OUT (out_RETIRE_EVENT_STOP ,"stop" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 152 _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_ rat_scheme[it1] == RAT_DEPTH_SAVE);153 _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1],_param->_ rat_scheme[it1] == RAT_DEPTH_SAVE);154 _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 155 _ALLOC2_SIGNAL_OUT_COND(out_RETIRE_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 154 156 155 157 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); … … 255 257 } 256 258 257 258 259 260 261 262 263 264 265 266 259 // // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 260 // { 261 // ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 262 // 263 // _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); 264 // _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); 265 // _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 266 // 267 // ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 268 // } 267 269 268 270 … … 332 334 333 335 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 334 ALLOC2(_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]); 335 ALLOC1(_rob ,std::list<entry_t*> ,_param->_nb_bank); 336 ALLOC2 (_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]); 337 ALLOC1 (_rob ,std::list<entry_t*> ,_param->_nb_bank); 338 339 ALLOC1 (reg_BANK_PTR ,uint32_t ,_param->_nb_bank); 340 341 ALLOC2 (reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 342 ALLOC2 (reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 343 ALLOC3_COND(reg_NB_INST_DEPTH ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 344 ALLOC2 (reg_EVENT_STATE ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]); 345 ALLOC2 (reg_EVENT_TYPE ,Tevent_type_t ,_param->_nb_front_end,_param->_nb_context [it1]); 346 // ALLOC2 (reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 347 // ALLOC2 (reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 348 // ALLOC2 (reg_EVENT_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 349 // ALLOC2 (reg_EVENT_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 350 // ALLOC2 (reg_EVENT_CAN_RESTART ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 351 ALLOC2 (reg_EVENT_PACKET ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 352 ALLOC2 (reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_front_end,_param->_nb_context [it1]); 353 ALLOC2 (reg_EVENT_NB_INST ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 354 ALLOC2 (reg_EVENT_LAST ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 355 ALLOC2 (reg_EVENT_LAST_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 356 ALLOC2 (reg_EVENT_LAST_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 357 358 ALLOC2 (reg_EVENT_NEXT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 359 ALLOC2 (reg_EVENT_NEXT_PACKET ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 360 361 // ALLOC2 (reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 362 ALLOC2 (reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 363 ALLOC2 (reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 364 ALLOC2 (reg_PC_CURRENT_IS_DS_TAKE,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 365 ALLOC2 (reg_PC_NEXT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 366 367 ALLOC3 (rat_gpr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic); 368 ALLOC3 (rat_spr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic); 369 336 370 337 ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank);338 339 ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]);340 ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]);341 342 ALLOC2(reg_EVENT_STATE ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]);343 ALLOC2(reg_EVENT_TYPE ,Tevent_type_t ,_param->_nb_front_end,_param->_nb_context [it1]);344 // ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]);345 // ALLOC2(reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]);346 // ALLOC2(reg_EVENT_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);347 // ALLOC2(reg_EVENT_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);348 // ALLOC2(reg_EVENT_CAN_RESTART ,bool ,_param->_nb_front_end,_param->_nb_context [it1]);349 ALLOC2(reg_EVENT_PACKET ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);350 ALLOC2(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_front_end,_param->_nb_context [it1]);351 ALLOC2(reg_EVENT_NB_INST ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);352 ALLOC2(reg_EVENT_LAST ,bool ,_param->_nb_front_end,_param->_nb_context [it1]);353 ALLOC2(reg_EVENT_LAST_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);354 ALLOC2(reg_EVENT_LAST_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);355 356 ALLOC2(reg_EVENT_NEXT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]);357 ALLOC2(reg_EVENT_NEXT_PACKET ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]);358 359 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]);360 ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]);361 ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]);362 ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]);363 ALLOC2(reg_PC_NEXT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]);364 365 ALLOC3(rat_gpr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic);366 ALLOC3(rat_spr_update_table ,bool ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic);367 371 } 368 372 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r139 r145 28 28 delete in_NRESET; 29 29 30 DELETE2_SIGNAL( in_INSERT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 31 DELETE2_SIGNAL(out_INSERT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 32 DELETE2_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); 33 DELETE2_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); 34 DELETE2_SIGNAL(out_INSERT_PACKET_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr ); 35 // DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id ); 36 DELETE2_SIGNAL( in_INSERT_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth ); 37 #ifdef STATISTICS 38 DELETE2_SIGNAL( in_INSERT_INSTRUCTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32); 39 #endif 40 DELETE2_SIGNAL( in_INSERT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); 41 DELETE2_SIGNAL( in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); 42 DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 43 DELETE2_SIGNAL( in_INSERT_LAST_EVENT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 44 DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 45 #ifdef DEBUG 46 DELETE2_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 47 #endif 48 DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 49 DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 50 DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 51 DELETE2_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); 52 DELETE2_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); 53 #ifdef DEBUG 54 DELETE2_SIGNAL( in_INSERT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 55 DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 56 DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 57 #endif 58 DELETE2_SIGNAL( in_INSERT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 59 #ifdef DEBUG 60 DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 61 DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 62 DELETE2_SIGNAL( in_INSERT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 63 DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); 64 DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 65 #endif 66 DELETE2_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 67 DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 68 DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 69 DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 70 DELETE2_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 71 DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); 72 DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 73 DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 30 DELETE2_SIGNAL ( in_INSERT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 31 DELETE2_SIGNAL (out_INSERT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 32 DELETE2_SIGNAL ( in_INSERT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); 33 DELETE2_SIGNAL ( in_INSERT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); 34 DELETE2_SIGNAL (out_INSERT_PACKET_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr ); 35 // DELETE2_SIGNAL ( in_INSERT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id ); 36 DELETE2_SIGNAL ( in_INSERT_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth ); 37 DELETE2_SIGNAL_COND( in_INSERT_SAVE_RAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE); 38 #ifdef STATISTICS 39 DELETE2_SIGNAL ( in_INSERT_INSTRUCTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],32); 40 #endif 41 DELETE2_SIGNAL ( in_INSERT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); 42 DELETE2_SIGNAL ( in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); 43 DELETE2_SIGNAL ( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 44 DELETE2_SIGNAL ( in_INSERT_LAST_EVENT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 45 DELETE2_SIGNAL ( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 46 #ifdef DEBUG 47 DELETE2_SIGNAL ( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 48 #endif 49 DELETE2_SIGNAL ( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 50 DELETE2_SIGNAL ( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 51 DELETE2_SIGNAL ( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 52 DELETE2_SIGNAL ( in_INSERT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); 53 DELETE2_SIGNAL ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); 54 #ifdef DEBUG 55 DELETE2_SIGNAL ( in_INSERT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 56 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RA_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 57 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 58 #endif 59 DELETE2_SIGNAL ( in_INSERT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 60 #ifdef DEBUG 61 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RB_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 62 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 63 DELETE2_SIGNAL ( in_INSERT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 64 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RC_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); 65 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 66 #endif 67 DELETE2_SIGNAL ( in_INSERT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 68 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); 69 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 70 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); 71 DELETE2_SIGNAL ( in_INSERT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 72 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); 73 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 74 DELETE2_SIGNAL ( in_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); 74 75 75 76 DELETE2_SIGNAL(out_RETIRE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); … … 78 79 DELETE2_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_context_id ); 79 80 // DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_rename_unit_id ); 81 // DELETE2_SIGNAL_COND(out_RETIRE_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_depth ,_param->_rat_scheme[it1] == RAT_DEPTH_SAVE); 80 82 DELETE2_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 81 83 DELETE2_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 82 84 DELETE2_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_store_queue_ptr ); 83 85 DELETE2_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_load_queue_ptr ); 84 // 85 // 86 // 87 // 88 // 89 // 86 // DELETE2_SIGNAL(out_RETIRE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 87 // DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); 88 // DELETE2_SIGNAL(out_RETIRE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 89 // DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); 90 // DELETE2_SIGNAL(out_RETIRE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 91 // DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register ); 90 92 DELETE2_SIGNAL(out_RETIRE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); 91 93 DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register_logic); … … 105 107 // DELETE2_SIGNAL (out_RETIRE_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context[it1],1); 106 108 DELETE2_SIGNAL (out_RETIRE_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context[it1],1); 107 DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_ rat_scheme[it1] == RAT_DEPTH_SAVE);108 DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ,_param->_ rat_scheme[it1] == RAT_DEPTH_SAVE);109 DELETE2_SIGNAL_COND(out_RETIRE_EVENT_TYPE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_type,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 110 DELETE2_SIGNAL_COND(out_RETIRE_EVENT_DEPTH ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ,_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 109 111 110 112 DELETE1_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit,1 ); … … 164 166 DELETE2_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod); 165 167 166 167 168 168 // DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); 169 // DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); 170 // DELETE2_SIGNAL( in_DEPTH_FULL ,_param->_nb_front_end, _param->_nb_context[it1],1); 169 171 170 172 DELETE2_SIGNAL( in_SPR_READ_SR_OVE ,_param->_nb_front_end, _param->_nb_context[it1],1); … … 221 223 } 222 224 223 DELETE2(_nb_cycle_idle ,_param->_nb_front_end,_param->_nb_context [it1]); 224 DELETE1(_rob ,_param->_nb_bank); 225 DELETE1(reg_BANK_PTR ,_param->_nb_bank); 226 DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); 227 DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); 228 229 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 230 DELETE2(reg_EVENT_TYPE ,_param->_nb_front_end,_param->_nb_context [it1]); 231 // DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 232 // DELETE2(reg_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 233 // DELETE2(reg_EVENT_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 234 // DELETE2(reg_EVENT_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 235 // DELETE2(reg_EVENT_CAN_RESTART ,_param->_nb_front_end,_param->_nb_context [it1]); 236 DELETE2(reg_EVENT_PACKET ,_param->_nb_front_end,_param->_nb_context [it1]); 237 DELETE2(reg_EVENT_DEPTH ,_param->_nb_front_end,_param->_nb_context [it1]); 238 DELETE2(reg_EVENT_NB_INST ,_param->_nb_front_end,_param->_nb_context [it1]); 239 DELETE2(reg_EVENT_LAST ,_param->_nb_front_end,_param->_nb_context [it1]); 240 DELETE2(reg_EVENT_LAST_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 241 DELETE2(reg_EVENT_LAST_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 242 243 DELETE2(reg_EVENT_NEXT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 244 DELETE2(reg_EVENT_NEXT_PACKET ,_param->_nb_front_end,_param->_nb_context [it1]); 245 246 // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 247 DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); 248 DELETE2(reg_PC_CURRENT_IS_DS ,_param->_nb_front_end,_param->_nb_context [it1]); 249 DELETE2(reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]); 250 DELETE2(reg_PC_NEXT ,_param->_nb_front_end,_param->_nb_context [it1]); 251 252 DELETE3(rat_gpr_update_table ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic); 253 DELETE3(rat_spr_update_table ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic); 225 DELETE2 (_nb_cycle_idle ,_param->_nb_front_end,_param->_nb_context [it1]); 226 DELETE1 (_rob ,_param->_nb_bank); 227 DELETE1 (reg_BANK_PTR ,_param->_nb_bank); 228 DELETE2 (reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); 229 DELETE2 (reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); 230 DELETE3_COND(reg_NB_INST_DEPTH ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_branch_speculated[it1][it2],_param->_front_end_rat_scheme[it1] == RAT_DEPTH_SAVE); 231 232 DELETE2 (reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 233 DELETE2 (reg_EVENT_TYPE ,_param->_nb_front_end,_param->_nb_context [it1]); 234 // DELETE2 (reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 235 // DELETE2 (reg_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 236 // DELETE2 (reg_EVENT_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 237 // DELETE2 (reg_EVENT_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 238 // DELETE2 (reg_EVENT_CAN_RESTART ,_param->_nb_front_end,_param->_nb_context [it1]); 239 DELETE2 (reg_EVENT_PACKET ,_param->_nb_front_end,_param->_nb_context [it1]); 240 DELETE2 (reg_EVENT_DEPTH ,_param->_nb_front_end,_param->_nb_context [it1]); 241 DELETE2 (reg_EVENT_NB_INST ,_param->_nb_front_end,_param->_nb_context [it1]); 242 DELETE2 (reg_EVENT_LAST ,_param->_nb_front_end,_param->_nb_context [it1]); 243 DELETE2 (reg_EVENT_LAST_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 244 DELETE2 (reg_EVENT_LAST_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 245 246 DELETE2 (reg_EVENT_NEXT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 247 DELETE2 (reg_EVENT_NEXT_PACKET ,_param->_nb_front_end,_param->_nb_context [it1]); 248 249 // DELETE2 (reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 250 DELETE2 (reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); 251 DELETE2 (reg_PC_CURRENT_IS_DS ,_param->_nb_front_end,_param->_nb_context [it1]); 252 DELETE2 (reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]); 253 DELETE2 (reg_PC_NEXT ,_param->_nb_front_end,_param->_nb_context [it1]); 254 255 DELETE3 (rat_gpr_update_table ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_general_register_logic); 256 DELETE3 (rat_spr_update_table ,_param->_nb_front_end,_param->_nb_context [it1],_param->_nb_special_register_logic); 254 257 } 255 258 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
r124 r145 101 101 if (not bank_full [num_bank]) 102 102 { 103 // find !!! 104 insert_ack [num_rename_unit][num_inst_insert] = true; 103 bool cond = true; 104 105 if (_param->_rat_scheme[num_rename_unit] == RAT_DEPTH_SAVE) 106 { 107 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [num_rename_unit][num_inst_insert]):0; 108 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [num_rename_unit][num_inst_insert]):0; 109 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_INSERT_DEPTH [num_rename_unit][num_inst_insert]):0; 110 Tcontrol_t save_rat = PORT_READ(in_INSERT_SAVE_RAT [num_rename_unit][num_inst_insert]); 111 112 cond = not (save_rat and (reg_NB_INST_DEPTH[front_end_id][context_id][depth]>0)); 113 114 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 115 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 116 log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); 117 log_printf(TRACE,Commit_unit,FUNCTION," * save_rat : %d",save_rat ); 118 log_printf(TRACE,Commit_unit,FUNCTION," * cond : %d",cond ); 119 120 } 105 121 106 Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank); 107 122 if (cond) 123 { 124 // find !!! 125 insert_ack [num_rename_unit][num_inst_insert] = true; 126 127 Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank); 128 108 129 #ifdef SYSTEMC_VHDL_COMPATIBILITY 109 insert_packet_id [num_rename_unit][num_inst_insert] = packet_id;130 insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; 110 131 #else 111 if (_param->_have_port_rob_ptr )112 PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id);132 if (_param->_have_port_rob_ptr ) 133 PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); 113 134 #endif 114 internal_BANK_INSERT_VAL [num_bank] = true; 115 internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; 116 internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; 117 118 break; 135 internal_BANK_INSERT_VAL [num_bank] = true; 136 internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; 137 internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; 138 139 break; 140 } 119 141 } 120 142 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r139 r145 225 225 PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); 226 226 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); 227 // if (_param->_have_port_depth and (_param->_rat_scheme[x] == RAT_DEPTH_SAVE)) 228 // PORT_WRITE(out_RETIRE_DEPTH [x][y], entry->depth ); 227 229 PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); 228 230 PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r139 r145 331 331 PORT_WRITE(out_RETIRE_EVENT_STOP [i][j], ((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_NOT_YET_EVENT) or 332 332 reg_EVENT_NEXT_STOP [i][j])); 333 if (_param->_ rat_scheme[i] == RAT_DEPTH_SAVE)333 if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE) 334 334 { 335 335 PORT_WRITE(out_RETIRE_EVENT_TYPE [i][j], reg_EVENT_TYPE [i][j]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
r142 r145 48 48 uint32_t mask_operation = gen_mask<uint32_t>(SIZE_OPERATION ); 49 49 50 msgInformation("Number of iteration couple of instructions.\n"); 51 50 52 for (uint32_t i=0; i<_param->_nb_thread; ++i) 51 53 for(stat_inst_fusion_t::iterator it = _stat_inst_fusion [i].begin(); … … 64 66 uint32_t operation_1 = inst &mask_operation ; 65 67 66 // log_printf(STAT,Commit_unit,FUNCTION,67 68 msgInformation( 68 69 //" * %s - %s : %d\n" 69 70 //,toString_instruction((inst>>SIZE_INSTRUCTION)&mask_inst).c_str() 70 71 //,toString_instruction( inst &mask_inst).c_str(),value 71 " * %s.%s - %s.%s : %d\n" 72 " * (%d) \t%s.%s - %s.%s\n" 73 ,value 72 74 ,toString (type_0 ).c_str() 73 75 ,toString_operation(type_0,operation_0).c_str() 74 76 ,toString (type_1 ).c_str() 75 77 ,toString_operation(type_1,operation_1).c_str() 76 ,value77 78 ); 78 79 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r144 r145 48 48 _nb_cycle_idle [i][j] = 0; 49 49 50 reg_NB_INST_COMMIT_ALL [i][j] = 0;51 reg_NB_INST_COMMIT_MEM [i][j] = 0;52 53 50 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; 54 51 // reg_EVENT_FLUSH [i][j] = false; … … 72 69 reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; 73 70 reg_PC_NEXT [i][j] = (0x100+4)>>2; 71 72 reg_NB_INST_COMMIT_ALL [i][j] = 0; 73 reg_NB_INST_COMMIT_MEM [i][j] = 0; 74 75 if (_param->_front_end_rat_scheme[i] == RAT_DEPTH_SAVE) 76 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 77 reg_NB_INST_DEPTH [i][j][k] = 0; 74 78 } 75 79 … … 281 285 uint32_t ptr = reg_BANK_PTR [num_bank]; 282 286 287 // entry->restore = false; 283 288 entry->ptr = ptr; 284 289 entry->front_end_id = front_end_id; … … 353 358 { 354 359 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} 355 case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store 360 case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;} 356 361 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 357 362 } … … 378 383 if (type == TYPE_MEMORY) 379 384 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; 380 385 386 if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE) 387 reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] ++; 381 388 382 389 // flush = present event or future event. … … 856 863 if (type == TYPE_MEMORY) 857 864 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 858 865 if (_param->_front_end_rat_scheme[front_end_id] == RAT_DEPTH_SAVE) 866 reg_NB_INST_DEPTH [front_end_id][context_id][entry->depth] --; 859 867 // Update pointer 860 868 reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; … … 1191 1199 switch (state) 1192 1200 { 1193 case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;}1194 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}1201 case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;} 1202 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 1195 1203 case ROB_END_BRANCH_MISS : 1196 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}1204 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 1197 1205 case ROB_END_LOAD_MISS : 1198 1206 case ROB_END_LOAD_MISS_UPDATE : 1199 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}1200 case ROB_STORE_OK : {state = ROB_STORE_KO ; break;}1207 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 1208 case ROB_STORE_OK : {state = ROB_STORE_KO ; break;} 1201 1209 case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;} 1202 1210 case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;} 1203 case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;}1211 case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END ; break;} 1204 1212 case ROB_END_OK : 1205 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}1213 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 1206 1214 case ROB_END_KO : 1207 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}1215 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 1208 1216 case ROB_END_EXCEPTION_UPDATE : 1209 1217 case ROB_END_EXCEPTION : 1210 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}1218 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 1211 1219 1212 1220 // don't change state -> wait … … 1348 1356 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); 1349 1357 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); 1350 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str()); 1358 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d",reg_EVENT_DEPTH [i][j]); 1359 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_TYPE : %s",toString(reg_EVENT_TYPE [i][j]).c_str()); 1351 1360 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); 1352 1361 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]); … … 1436 1445 } 1437 1446 1438 log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT 1447 log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT_Update Table"); 1439 1448 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 1440 1449 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
r139 r145 21 21 #undef FUNCTION 22 22 #define FUNCTION "Commit_unit::Parameters" 23 Parameters::Parameters (uint32_t nb_front_end , 24 uint32_t * nb_context ,//[nb_front_end] 25 uint32_t nb_rename_unit , 26 uint32_t size_queue , 27 uint32_t nb_bank , 28 Tretire_ooo_scheme_t retire_ooo_scheme , 29 uint32_t * nb_inst_insert ,//[nb_rename_unit] 30 uint32_t * nb_inst_retire ,//[nb_rename_unit] 31 uint32_t nb_inst_commit , 32 uint32_t nb_inst_reexecute , 33 uint32_t nb_inst_branch_complete , 34 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 35 uint32_t size_nb_inst_decod , 36 uint32_t size_general_data , 37 uint32_t size_store_queue_ptr , 38 uint32_t size_load_queue_ptr , 39 uint32_t size_general_register , 40 uint32_t size_special_register , 41 Trat_scheme_t * rat_scheme ,//[nb_front_end] 42 Tpriority_t priority , 43 Tload_balancing_t load_balancing , 44 uint32_t nb_rename_unit_select , 45 uint32_t nb_thread , 46 uint32_t ** translate_num_context_to_num_thread,//[nb_front_end][nb_context] 47 bool is_toplevel): 23 Parameters::Parameters (uint32_t nb_front_end , 24 uint32_t * nb_context ,//[nb_front_end] 25 uint32_t nb_rename_unit , 26 uint32_t size_queue , 27 uint32_t nb_bank , 28 Tretire_ooo_scheme_t retire_ooo_scheme , 29 uint32_t * nb_inst_insert ,//[nb_rename_unit] 30 uint32_t * nb_inst_retire ,//[nb_rename_unit] 31 uint32_t nb_inst_commit , 32 uint32_t nb_inst_reexecute , 33 uint32_t nb_inst_branch_complete , 34 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 35 uint32_t size_nb_inst_decod , 36 uint32_t size_general_data , 37 uint32_t size_store_queue_ptr , 38 uint32_t size_load_queue_ptr , 39 uint32_t size_general_register , 40 uint32_t size_special_register , 41 Trat_scheme_t * rat_scheme ,//[nb_rename_unit] 42 std::vector<uint32_t>* link_front_end_with_rename_unit ,//[nb_rename_unit] 43 Tpriority_t priority , 44 Tload_balancing_t load_balancing , 45 uint32_t nb_rename_unit_select , 46 uint32_t nb_thread , 47 uint32_t ** translate_num_context_to_num_thread,//[nb_front_end][nb_context] 48 bool is_toplevel): 48 49 _nb_bank_access_commit (1 ) 49 50 { … … 63 64 _nb_branch_speculated = nb_branch_speculated ; 64 65 _rat_scheme = rat_scheme ; 66 _link_front_end_with_rename_unit = link_front_end_with_rename_unit ; 65 67 _priority = priority ; 66 68 _load_balancing = load_balancing ; … … 81 83 82 84 _have_port_rename_unit_id = _size_rename_unit_id > 0; 85 86 ALLOC1(_front_end_rat_scheme, Trat_scheme_t,_nb_front_end); 87 // one rename unit per front_end 88 for (uint32_t i=0; i<_nb_rename_unit; ++i) 89 for (std::vector<uint32_t>::iterator it=_link_front_end_with_rename_unit[i].begin(); 90 it != _link_front_end_with_rename_unit[i].end(); 91 ++it) 92 _front_end_rat_scheme[*it] = _rat_scheme[i]; 83 93 84 94 ALLOC2(_array_size_depth,uint32_t,_nb_front_end,_nb_context [it1]); … … 138 148 log_begin(Commit_unit,FUNCTION); 139 149 140 DELETE1(_have_thread ,_nb_thread); 141 DELETE2(_array_size_depth,_nb_front_end,_nb_context [it1]); 150 DELETE1(_have_thread ,_nb_thread); 151 DELETE2(_array_size_depth ,_nb_front_end,_nb_context [it1]); 152 DELETE1(_front_end_rat_scheme,_nb_front_end); 142 153 143 154 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h
r138 r145 112 112 private : uint32_t * internal_RETIRE_LSQ ; // [nb_inst_retire] 113 113 private : Tlsq_ptr_t * internal_RETIRE_PTR ; // [nb_inst_retire] 114 private : Tcontrol_t ** internal_RETIRE_EVENT_ACK ; //[nb_front_end][nb_context]114 private : Tcontrol_t ** internal_RETIRE_EVENT_ACK ; //[nb_front_end][nb_context] 115 115 116 116 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_insert.cpp
r138 r145 27 27 if (PORT_READ(in_NRESET)) 28 28 { 29 // TODO : limité à nb_inst_memory le nombre d'accès par lsq !!! 30 31 uint32_t nb_use_lsq [_param->_nb_load_store_queue]; 29 // Limit at nb_inst_memory access per load_store_queue 30 // uint32_t nb_use_lsq [_param->_nb_load_store_queue]; 32 31 Tlsq_ptr_t STORE_QUEUE_PTR_WRITE [_param->_nb_load_store_queue]; 33 32 bool STORE_QUEUE_USE [_param->_nb_load_store_queue][_param->_max_size_store_queue]; … … 38 37 for (uint32_t i=0; i<_param->_nb_load_store_queue; i++) 39 38 { 40 nb_use_lsq [i] = _param->_nb_inst_memory[i];39 // nb_use_lsq [i] = _param->_nb_inst_memory[i]; 41 40 42 41 STORE_QUEUE_PTR_WRITE [i] = reg_STORE_QUEUE_PTR_WRITE [i]; … … 82 81 // Test if a previous instruction use the same lsq 83 82 // Authorize once memory access by load store unit 84 if (nb_use_lsq [lsq] > 0)83 // if (nb_use_lsq [lsq] > 0) 85 84 { 86 nb_use_lsq [lsq] --;85 // nb_use_lsq [lsq] --; 87 86 88 87 uint32_t ptr; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h
r139 r145 36 36 37 37 public : uint32_t _max_nb_context ; 38 public : uint32_t _max_nb_branch_speculated; 38 39 //public : uint32_t _size_front_end_id ; 39 40 //public : uint32_t _size_context_id ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h
r139 r145 107 107 108 108 // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 109 public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] 110 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] 111 public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 112 public : SC_IN (Tevent_type_t ) *** in_RETIRE_EVENT_TYPE ;//[nb_front_end][nb_context] 113 public : SC_IN (Tdepth_t ) *** in_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context] 109 public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] 110 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] 111 public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 112 public : SC_IN (Tevent_type_t ) *** in_RETIRE_EVENT_TYPE ;//[nb_front_end][nb_context] 113 public : SC_IN (Tdepth_t ) *** in_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context] 114 115 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] 117 public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] 118 public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] 114 119 115 120 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 116 121 117 122 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 118 private : Tgeneral_address_t *** rat_gpr_not_speculative; //[nb_front_end][nb_context] [nb_general_register_logic]119 private : Tgeneral_address_t *** rat_gpr_speculative; //[nb_front_end][nb_context] [nb_general_register_logic]120 private : bool *** rat_gpr_speculative_valid; //[nb_front_end][nb_context] [nb_general_register_logic]121 private : Tgeneral_address_t **** rat_gpr_save; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic]122 123 private : Tspecial_address_t *** rat_spr_not_speculative; //[nb_front_end][nb_context] [nb_special_register_logic]124 private : Tspecial_address_t *** rat_spr_speculative; //[nb_front_end][nb_context] [nb_special_register_logic]125 private : bool *** rat_spr_speculative_valid; //[nb_front_end][nb_context] [nb_special_register_logic]126 private : Tspecial_address_t **** rat_spr_save; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] 127 128 private : Tdepth_t ** rat_depth; //[nb_front_end][nb_context]123 // NO ONE DEPTH 124 private : Tgeneral_address_t *** RAT_GPR_NOT_SPECULATIVE; //[nb_front_end][nb_context] [nb_general_register_logic] X X X 125 private : Tgeneral_address_t **** RAT_GPR_SPECULATIVE; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic] X X 126 private : bool **** RAT_GPR_SPECULATIVE_VALID; //[nb_front_end][nb_context][nb_branch_speculated][nb_general_register_logic] X X 127 128 private : Tspecial_address_t *** RAT_SPR_NOT_SPECULATIVE; //[nb_front_end][nb_context] [nb_special_register_logic] X X X 129 private : Tspecial_address_t **** RAT_SPR_SPECULATIVE; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] X X 130 private : bool **** RAT_SPR_SPECULATIVE_VALID; //[nb_front_end][nb_context][nb_branch_speculated][nb_special_register_logic] X X 131 132 private : bool *** reg_RAT_USE; //[nb_front_end][nb_context][nb_branch_speculated] X 133 private : bool ** reg_SAVE_RAT; //[nb_front_end][nb_context] X 129 134 130 135 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 136 private : Tcontrol_t * internal_RENAME_ACK; //[nb_inst_insert] 132 private : Tcontrol_t * internal_RENAME_SAVE; //[nb_inst_insert]133 137 private : Tcontrol_t * internal_INSERT_ACK; //[nb_inst_insert] 134 138 private : Tcontrol_t * internal_RETIRE_ACK; //[nb_inst_retire] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp
r144 r145 41 41 _nb_branch_speculated = nb_branch_speculated; 42 42 43 _max_nb_context = max<uint32_t>(_nb_context, _nb_front_end); 43 _max_nb_context = max<uint32_t>(_nb_context, _nb_front_end); 44 _max_nb_branch_speculated= max<uint32_t>(_nb_branch_speculated, _nb_front_end, _nb_context); 44 45 45 46 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
r139 r145 160 160 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 161 161 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 162 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 163 << (*(in_RETIRE_EVENT_STATE [i][j])); 162 { 163 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 164 << (*(in_RETIRE_EVENT_STATE [i][j])) 165 << (*(in_DEPTH_FULL [i][j])); 166 if (_param->_have_port_depth) 167 sensitive << (*(in_DEPTH_MIN [i][j])) 168 << (*(in_DEPTH_MAX [i][j])); 169 } 164 170 165 171 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp
r139 r145 131 131 } 132 132 133 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 134 { 135 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 136 137 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 138 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 139 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 140 141 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 142 } 143 133 144 if (usage_is_set(_usage,USE_SYSTEMC)) 134 145 { 135 146 ALLOC1(internal_RENAME_ACK ,Tcontrol_t,_param->_nb_inst_insert); 136 ALLOC1(internal_RENAME_SAVE ,Tcontrol_t,_param->_nb_inst_insert);137 147 ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); 138 148 ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); 139 149 ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); 140 150 141 ALLOC3( rat_gpr_speculative,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);142 ALLOC3( rat_spr_speculative,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);151 ALLOC3(RAT_GPR_NOT_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 152 ALLOC3(RAT_SPR_NOT_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 143 153 144 154 switch(_param->_rat_scheme) … … 150 160 case RAT_ONE_SAVE : 151 161 { 152 ALLOC 3(rat_gpr_not_speculative ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);153 ALLOC 3(rat_gpr_speculative_valid,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);154 155 ALLOC 3(rat_spr_not_speculative ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);156 ALLOC 3(rat_spr_speculative_valid,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);162 ALLOC4(RAT_GPR_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 163 ALLOC4(RAT_SPR_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 164 165 ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 166 ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 157 167 158 168 break; … … 160 170 case RAT_DEPTH_SAVE : 161 171 { 162 ALLOC4(rat_gpr_save ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 163 ALLOC4(rat_spr_save ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 164 ALLOC2(rat_depth ,Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); 165 172 ALLOC4(RAT_GPR_SPECULATIVE ,Tgeneral_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 173 ALLOC4(RAT_SPR_SPECULATIVE ,Tspecial_address_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 174 175 ALLOC4(RAT_GPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 176 ALLOC4(RAT_SPR_SPECULATIVE_VALID,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 177 178 ALLOC3(reg_RAT_USE ,bool ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]); 179 ALLOC2(reg_SAVE_RAT ,bool ,_param->_nb_front_end,_param->_nb_context[it1]); 180 166 181 break; 167 182 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp
r139 r145 76 76 DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ,_param->_rat_scheme == RAT_DEPTH_SAVE); 77 77 78 DELETE2_SIGNAL ( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 79 DELETE2_SIGNAL ( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 80 DELETE2_SIGNAL ( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 81 78 82 DELETE1(internal_RENAME_ACK ,_param->_nb_inst_insert); 79 DELETE1(internal_RENAME_SAVE ,_param->_nb_inst_insert);80 DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert);81 83 DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); 82 84 DELETE2(internal_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); 83 85 84 DELETE3( rat_gpr_speculative,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);85 DELETE3( rat_spr_speculative,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);86 86 DELETE3(RAT_GPR_NOT_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic); 87 DELETE3(RAT_SPR_NOT_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic); 88 87 89 switch(_param->_rat_scheme) 88 90 { … … 93 95 case RAT_ONE_SAVE : 94 96 { 95 DELETE 3(rat_gpr_not_speculative ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);96 DELETE 3(rat_gpr_speculative_valid ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_general_register_logic);97 98 DELETE 3(rat_spr_not_speculative ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);99 DELETE 3(rat_spr_speculative_valid ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_special_register_logic);97 DELETE4(RAT_GPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 98 DELETE4(RAT_SPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 99 100 DELETE4(RAT_GPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_general_register_logic); 101 DELETE4(RAT_SPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],1,_param->_nb_special_register_logic); 100 102 101 103 break; … … 103 105 case RAT_DEPTH_SAVE : 104 106 { 105 DELETE4(rat_gpr_save ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 106 DELETE4(rat_spr_save ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 107 DELETE2(rat_depth ,_param->_nb_front_end,_param->_nb_context[it1]); 107 DELETE4(RAT_GPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 108 DELETE4(RAT_SPR_SPECULATIVE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 109 110 DELETE4(RAT_GPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_general_register_logic); 111 DELETE4(RAT_SPR_SPECULATIVE_VALID ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2],_param->_nb_special_register_logic); 112 113 DELETE3(reg_RAT_USE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_branch_speculated[it1][it2]); 114 DELETE2(reg_SAVE_RAT ,_param->_nb_front_end,_param->_nb_context[it1]); 108 115 109 116 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_constant.cpp
r139 r145 30 30 { 31 31 internal_INSERT_ACK [i] = 1; 32 internal_RENAME_ACK [i] = 1; 32 33 33 34 PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]); 35 PORT_WRITE(out_RENAME_ACK[i],internal_RENAME_ACK [i]); 34 36 } 35 37 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp
r139 r145 28 28 if (PORT_READ(in_NRESET) != 0) 29 29 { 30 bool have_branch_previous = false; 31 bool can_continue [_param->_nb_front_end][_param->_max_nb_context]; 30 bool rat_gpr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_general_register_logic]; 31 bool rat_spr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_special_register_logic]; 32 // bool reg_save_rat [_param->_nb_front_end][_param->_max_nb_context]; 32 33 33 34 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 34 35 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 35 can_continue [i][j] = true; 36 { 37 // reg_save_rat [i][j] = reg_SAVE_RAT [i][j]; 38 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 39 { 40 for (uint32_t l=0; l<_param->_nb_general_register_logic; ++l) 41 rat_gpr_speculative_valid [i][j][k][l] = RAT_GPR_SPECULATIVE_VALID [i][j][k][l]; 42 for (uint32_t l=0; l<_param->_nb_special_register_logic; ++l) 43 rat_spr_speculative_valid [i][j][k][l] = RAT_SPR_SPECULATIVE_VALID [i][j][k][l]; 44 } 45 } 36 46 37 47 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 38 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access39 {40 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i);41 42 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;43 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID[i]):0;44 // bool have_event = (PORT_READ(in_RETIRE_EVENT_VAL [front_end_id][context_id]) and // always ack45 // (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) == EVENT_STATE_EVENT));46 47 bool have_branch_current = PORT_READ(in_RENAME_SAVE_RAT [i]);48 { 49 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access 50 { 51 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i); 52 53 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 54 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 55 56 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 57 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 48 58 49 // one branch per cycle 50 can_continue[front_end_id][context_id] &= not (have_branch_current and have_branch_previous); 59 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 60 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 61 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 51 62 52 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 53 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 54 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_event : %d",have_event); 55 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_branch_previous : %d",have_branch_previous); 56 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * have_branch_current : %d",have_branch_current ); 57 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * can_continue : %d",can_continue[front_end_id][context_id]); 58 59 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 60 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 61 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 62 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 63 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 64 65 Tgeneral_address_t num_reg_ra_phy = rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]; 66 Tgeneral_address_t num_reg_rb_phy = rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]; 67 Tspecial_address_t num_reg_rc_phy = rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]; 68 Tgeneral_address_t num_reg_rd_phy_old= rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]; 69 Tspecial_address_t num_reg_re_phy_old= rat_spr_speculative[front_end_id][context_id][num_reg_re_log]; 70 71 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); 72 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); 73 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); 74 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); 75 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); 76 77 internal_RENAME_ACK [i] = can_continue[front_end_id][context_id]; 78 PORT_WRITE(out_RENAME_ACK [i],internal_RENAME_ACK [i]); 79 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); 80 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); 81 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); 82 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); 83 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); 63 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 64 // Tcontrol_t save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); 65 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth/min/max/full : %d - [%d:%d] - %d",depth,depth_min,depth_max,depth_full); 66 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); 67 // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",reg_save_rat [front_end_id][context_id]); 68 69 // if (reg_save_rat [front_end_id][context_id]) 70 // { 71 // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) 72 // rat_gpr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; 73 // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) 74 // rat_spr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; 75 // } 76 77 // reg_save_rat[front_end_id][context_id] = save_rat; 78 79 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 80 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 81 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 82 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 83 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 84 85 Tgeneral_address_t num_reg_ra_phy ; 86 Tgeneral_address_t num_reg_rb_phy ; 87 Tspecial_address_t num_reg_rc_phy ; 88 Tgeneral_address_t num_reg_rd_phy_old; 89 Tspecial_address_t num_reg_re_phy_old; 90 91 bool find_ra = false; 92 bool find_rb = false; 93 bool find_rc = false; 94 bool find_rd = false; 95 bool find_re = false; 96 97 for (uint32_t num_branch=0; num_branch<_param->_nb_branch_speculated[front_end_id][context_id]; ++num_branch) 98 { 99 uint32_t index = (depth-num_branch)%_param->_nb_branch_speculated[front_end_id][context_id]; 84 100 85 internal_RENAME_SAVE [i] = have_branch_current; 101 if (not find_ra and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_ra_log]) 102 { 103 find_ra = true; 104 num_reg_ra_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_ra_log]; 105 } 106 107 if (not find_rb and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rb_log]) 108 { 109 find_rb = true; 110 num_reg_rb_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rb_log]; 111 } 112 113 if (not find_rc and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_rc_log]) 114 { 115 find_rc = true; 116 num_reg_rc_phy = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rc_log]; 117 } 118 119 if (not find_rd and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rd_log]) 120 { 121 find_rd = true; 122 num_reg_rd_phy_old = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rd_log]; 123 } 124 125 if (not find_re and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_re_log]) 126 { 127 find_re = true; 128 num_reg_re_phy_old = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_re_log]; 129 } 86 130 87 // save info to the next instruction 88 have_branch_previous |= have_branch_current; 89 } 131 // if index == depth_min, stop because depth_min is the not speculative. 132 // if (index == depth_min) 133 // break; 134 } 135 136 if (not find_ra) 137 num_reg_ra_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log]; 138 if (not find_rb) 139 num_reg_rb_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log]; 140 if (not find_rc) 141 num_reg_rc_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log]; 142 if (not find_rd) 143 num_reg_rd_phy_old = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log]; 144 if (not find_re) 145 num_reg_re_phy_old = RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log]; 146 147 // if rat_SPECULATIVE is valid, 148 // then read rat_SPECULATIVE have the most valid alias register 149 // else, they have an previous event, the rat_NOT_SPECULATIVE have the valid register 150 151 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); 152 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); 153 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); 154 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); 155 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); 156 157 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); 158 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); 159 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); 160 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); 161 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); 162 } 163 } 90 164 } 91 165 92 166 log_end(Register_Address_Translation_unit,FUNCTION); 93 167 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_depth_save_transition.cpp
r144 r145 34 34 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 35 35 { 36 rat_depth [i][j] = 0; 37 rat_gpr_speculative [i][j][0] = 0; 36 RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; 37 RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; 38 RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary 38 39 39 40 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 40 rat_gpr_speculative [i][j][k] = gpr++; 41 { 42 RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; 43 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 44 { 45 RAT_GPR_SPECULATIVE_VALID [i][j][l][k] = false; 46 RAT_GPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 47 } 48 } 41 49 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 42 rat_spr_speculative [i][j][k] = spr++; // not necessary 50 { 51 RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; 52 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 53 { 54 RAT_SPR_SPECULATIVE_VALID [i][j][l][k] = false; 55 RAT_SPR_SPECULATIVE [i][j][l][k] = 0 ; // not necessary 56 } 57 } 58 59 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 60 reg_RAT_USE [i][j][k] = false; 61 reg_SAVE_RAT [i][j] = false; 43 62 } 44 63 } … … 46 65 { 47 66 // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) 67 bool free_rat [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated]; 68 for (uint32_t i=0; i<_param->_nb_front_end; i++) 69 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 70 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 71 free_rat [i][j][k] = false; 48 72 49 73 // ===================================================== … … 55 79 { 56 80 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j); 81 82 // Test if event have just occure 83 // * if exception -> reset valid table (rat_NOT_SPECULATIVE have the good value) 57 84 58 // Test if event have just occure59 85 if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) 60 { 61 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 86 switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j])) 87 { 88 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 62 89 { 63 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 64 case EVENT_TYPE_LOAD_MISS_SPECULATION : 65 { 66 // Miss speculation (branch or load) 67 // Restore contexte and update depth 68 69 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * MISS_SPECULATION : Restore RAT"); 70 71 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0; 72 73 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 74 75 // restore GPR 76 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 77 rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr]; 78 79 // restore SPR 80 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 81 rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr]; 82 83 // update rat_depth 84 rat_depth[i][j] = depth; 85 86 break; 87 } 88 // case EVENT_TYPE_EXCEPTION : 89 // case EVENT_TYPE_SPR_ACCESS : 90 // case EVENT_TYPE_MSYNC : 91 // case EVENT_TYPE_PSYNC : 92 // case EVENT_TYPE_CSYNC : 93 default : 94 { 95 // nothing 96 break; 97 } 90 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * BRANCH_MISS_SPECULATION - Reset Update Table"); 91 92 reg_SAVE_RAT [i][j] = true; 93 94 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH[i][j]):0; 95 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 96 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 97 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 98 99 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 100 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 101 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 102 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 103 104 Tdepth_t it = depth_min; 105 106 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 107 { 108 it = (it-1)%_param->_nb_branch_speculated[i][j]; 109 110 if (it == depth) 111 break; 112 113 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",it); 114 115 free_rat[i][j][it] = true; 116 } 117 118 break; 98 119 } 99 100 } 120 case EVENT_TYPE_EXCEPTION : 121 { 122 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * EXCEPTION - Reset Update Table"); 123 124 reg_SAVE_RAT [i][j] = true; 125 126 // Reset validity table 127 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 128 free_rat [i][j][k] = true; 129 130 break; 131 } 132 default : 133 { 134 break; 135 } 136 } 101 137 } 102 138 … … 114 150 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 115 151 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 116 Tcontrol_t save = internal_RENAME_SAVE [i]; 152 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 153 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 154 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 155 Tcontrol_t save_rat = reg_SAVE_RAT[front_end_id][context_id]; 156 // TODO SAVE_RAT 117 157 118 158 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); 119 159 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); 120 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save : %d",save); 121 122 // Test if write and modifie RAT (RD and RE) 123 124 Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); 125 Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); 126 160 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth); 161 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",save_rat); 162 163 if (save_rat) 164 { 165 // #ifdef DEBUG_TEST 166 // if (reg_RAT_USE[front_end_id][context_id][depth]) 167 // throw ERRORMORPHEO(FUNCTION,toString(_("Invalid RAT and need save_rat (%d).\n"),depth)); 168 // #endif 169 reg_RAT_USE[front_end_id][context_id][depth] = true; 170 171 // new branch, new RAT 172 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) 173 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 174 for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) 175 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_log] = false; 176 } 177 178 save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); 179 reg_SAVE_RAT[front_end_id][context_id] = save_rat; 180 181 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); 182 183 // Test if write and modifie RAT 127 184 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); 128 185 if (write_rd == 1) … … 134 191 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); 135 192 136 rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; 193 RAT_GPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_rd_log] = num_reg_rd_phy; 194 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_rd_log] = true; 137 195 } 138 196 … … 146 204 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); 147 205 148 rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; 149 } 150 151 if (save) 152 { 153 // Need save RAT 154 155 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; 156 157 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth old - new : %d",depth); 158 159 // #ifdef DEBUG_TEST 160 // if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id])) 161 // throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth)); 162 // #endif 163 164 // save GPR 165 for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++) 166 rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr]; 167 168 // save SPR 169 for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++) 170 rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr]; 171 172 // update rat_depth with new depth 173 rat_depth[front_end_id][context_id] = depth; 206 RAT_SPR_SPECULATIVE [front_end_id][context_id][depth][num_reg_re_log] = num_reg_re_phy; 207 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][depth][num_reg_re_log] = true; 174 208 } 175 209 } … … 179 213 // ===================================================== 180 214 // Second : interface retire 181 // (because if an event on the same thread : the instruction is already renamed) 182 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 183 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 184 { 215 // if event AND event is exception, restore rat_NOT_SPECULATIVE 216 217 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 218 if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) 219 { 185 220 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); 186 221 187 // if no event : no effect, because the RAT content the most recently register188 // but if they have a event (exception or miss speculation), the rat must restore the oldest value189 // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register190 // the retire interface became of the Re Order Buffer, also is in program sequence !191 192 #ifdef DEBUG193 222 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; 194 223 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; 195 #endif196 224 Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); 197 225 Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); … … 206 234 if (write_rd == 1) 207 235 { 208 #ifdef DEBUG209 236 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); 210 #endif211 237 212 238 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); … … 214 240 if (not restore) 215 241 { 216 #ifdef DEBUG217 242 Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 218 #endif 243 219 244 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); 220 245 221 // rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;246 RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; 222 247 } 223 248 } … … 226 251 if (write_re == 1) 227 252 { 228 #ifdef DEBUG229 253 Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); 254 255 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 256 257 if (not restore) 258 { 259 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 260 261 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 262 263 RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 264 } 265 } 266 } 267 268 // ===================================================== 269 // ====[ DEPTH ]======================================== 270 // ===================================================== 271 #if 1 272 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 273 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 274 { 275 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * DEPTH[%d][%d]",i,j); 276 277 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[i][j]):0; 278 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[i][j]):0; 279 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [i][j]); 280 281 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_min : %d",depth_min); 282 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_max : %d",depth_max); 283 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth_full : %d",depth_full); 284 285 if (not depth_full) 286 { 287 Tdepth_t depth = depth_max; 288 289 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 290 { 291 if (depth == depth_min) 292 break; 293 294 if (reg_RAT_USE[i][j][depth]) 295 { 296 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * flush : %d",depth); 297 298 free_rat [i][j][depth] = true; 299 // reg_RAT_USE[i][j][depth] = false; 300 301 // for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 302 // RAT_GPR_SPECULATIVE_VALID [i][j][depth][l] = false; 303 // for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 304 // RAT_SPR_SPECULATIVE_VALID [i][j][depth][l] = false; 305 } 306 307 depth = (depth+1)%_param->_nb_branch_speculated[i][j]; 308 } 309 } 310 } 230 311 #endif 231 232 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); 233 234 if (not restore) 235 { 236 #ifdef DEBUG 237 Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 238 #endif 239 240 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 241 242 // rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 243 } 244 } 245 246 } 312 // ===================================================== 313 // ====[ FREE RAT ]===================================== 314 // ===================================================== 315 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 316 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 317 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 318 if (free_rat[i][j][k]) 319 { 320 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Free RAT : [%d][%d][%d]",i,j,k); 321 322 reg_RAT_USE[i][j][k] = false; 323 324 for (uint32_t l=0; l<_param->_nb_general_register_logic; l++) 325 RAT_GPR_SPECULATIVE_VALID [i][j][k][l] = false; 326 for (uint32_t l=0; l<_param->_nb_special_register_logic; l++) 327 RAT_SPR_SPECULATIVE_VALID [i][j][k][l] = false; 328 } 329 247 330 } 248 331 … … 255 338 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 256 339 { 257 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);258 259 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)340 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - SAVE_RAT : %d",i,j,reg_SAVE_RAT[i][j]); 341 342 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 260 343 { 261 344 std::string str = ""; 262 345 for (uint32_t x=0; x<limit; x++) 263 346 { 264 uint32_t index = k+x;347 uint32_t index = l+x; 265 348 if (index >= _param->_nb_general_register_logic) 266 349 break; 267 350 else 268 str+=toString("GPR[%.4d] - %.5d | ",index,rat_gpr_speculative[i][j][index]);351 str+=toString("GPR[%.4d] - %.5d | ",index,RAT_GPR_NOT_SPECULATIVE [i][j][index]); 269 352 } 270 353 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 271 354 } 272 355 273 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 274 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) 275 { 276 std::string str = ""; 277 for (uint32_t x=0; x<limit; x++) 278 { 279 uint32_t index = k+x; 280 if (index >= _param->_nb_general_register_logic) 281 break; 282 else 283 str+=toString("GPR_%d[%.4d] - %.5d | ",l,index,rat_gpr_save [i][j][l][index]); 284 } 285 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 286 } 287 288 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 356 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 357 { 358 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 359 360 for (uint32_t l=0; l<_param->_nb_general_register_logic; l+=limit) 361 { 362 std::string str = ""; 363 for (uint32_t x=0; x<limit; x++) 364 { 365 uint32_t index = l+x; 366 if (index >= _param->_nb_general_register_logic) 367 break; 368 else 369 str+=toString("GPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_GPR_SPECULATIVE_VALID [i][j][k][index],RAT_GPR_SPECULATIVE [i][j][k][index]); 370 } 371 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 372 } 373 } 374 375 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 289 376 { 290 377 std::string str = ""; … … 292 379 for (uint32_t x=0; x<limit; x++) 293 380 { 294 uint32_t index = k+x;381 uint32_t index = l+x; 295 382 if (index >= _param->_nb_special_register_logic) 296 383 break; 297 384 else 298 str+=toString("SPR[%.4d] - %.5d | ",index,rat_spr_speculative[i][j][index]);385 str+=toString("SPR[%.4d] - %.5d | ",index,RAT_SPR_NOT_SPECULATIVE [i][j][index]); 299 386 } 300 387 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 301 388 } 302 389 303 for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l) 304 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 305 { 306 std::string str = ""; 307 for (uint32_t x=0; x<limit; x++) 308 { 309 uint32_t index = k+x; 310 if (index >= _param->_nb_special_register_logic) 311 break; 312 else 313 str+=toString("SPR_%d[%.4d] - %.5d | ",l,index,rat_spr_save [i][j][l][index]); 314 } 315 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 316 } 317 390 391 for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) 392 { 393 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR [%.4d] - USE : %d",k,reg_RAT_USE [i][j][k]); 394 395 for (uint32_t l=0; l<_param->_nb_special_register_logic; l+=limit) 396 { 397 std::string str = ""; 398 399 for (uint32_t x=0; x<limit; x++) 400 { 401 uint32_t index = l+x; 402 if (index >= _param->_nb_special_register_logic) 403 break; 404 else 405 str+=toString("SPR[%.4d][%.4d] - %.1d %.5d | ",index,k,RAT_SPR_SPECULATIVE_VALID [i][j][k][index],RAT_SPR_SPECULATIVE [i][j][k][index]); 406 } 407 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 408 } 409 } 318 410 } 319 411 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_genMealy_rename.cpp
r139 r145 52 52 // else, they have an previous event, the rat_not_speculative have the valid register 53 53 54 Tgeneral_address_t num_reg_ra_phy = ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_ra_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_ra_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_ra_log];55 Tgeneral_address_t num_reg_rb_phy = ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rb_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rb_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rb_log];56 Tspecial_address_t num_reg_rc_phy = ( rat_spr_speculative_valid[front_end_id][context_id][num_reg_rc_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_rc_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_rc_log];57 Tgeneral_address_t num_reg_rd_phy_old= ( rat_gpr_speculative_valid[front_end_id][context_id][num_reg_rd_log] and not have_event)?rat_gpr_speculative[front_end_id][context_id][num_reg_rd_log]:rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log];58 Tspecial_address_t num_reg_re_phy_old= ( rat_spr_speculative_valid[front_end_id][context_id][num_reg_re_log] and not have_event)?rat_spr_speculative[front_end_id][context_id][num_reg_re_log]:rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log];54 Tgeneral_address_t num_reg_ra_phy = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_ra_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_ra_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log]; 55 Tgeneral_address_t num_reg_rb_phy = (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rb_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rb_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log]; 56 Tspecial_address_t num_reg_rc_phy = (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rc_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rc_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log]; 57 Tgeneral_address_t num_reg_rd_phy_old= (RAT_GPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_rd_log] and not have_event)?RAT_GPR_SPECULATIVE[front_end_id][context_id][0][num_reg_rd_log]:RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log]; 58 Tspecial_address_t num_reg_re_phy_old= (RAT_SPR_SPECULATIVE_VALID[front_end_id][context_id][0][num_reg_re_log] and not have_event)?RAT_SPR_SPECULATIVE[front_end_id][context_id][0][num_reg_re_log]:RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log]; 59 59 60 60 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp
r139 r145 34 34 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 35 35 { 36 rat_gpr_not_speculative [i][j][0]= 0;37 rat_gpr_speculative_valid [i][j][0] = false;38 rat_gpr_speculative [i][j][0] = 0 ; // not necessary36 RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; 37 RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; 38 RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary 39 39 40 40 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 41 41 { 42 rat_gpr_not_speculative [i][j][k]= gpr++;43 rat_gpr_speculative_valid [i][j][k] = false;44 rat_gpr_speculative [i][j][k] = 0 ; // not necessary42 RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; 43 RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; 44 RAT_GPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary 45 45 } 46 46 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 47 47 { 48 rat_spr_not_speculative [i][j][k]= spr++;49 rat_spr_speculative_valid [i][j][k] = false;50 rat_spr_speculative [i][j][k] = 0 ; // not necessary48 RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; 49 RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; 50 RAT_SPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary 51 51 } 52 52 } … … 69 69 // Reset validity table 70 70 for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) 71 rat_gpr_speculative_valid [i][j][k] = false;71 RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; 72 72 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 73 rat_spr_speculative_valid [i][j][k] = false;73 RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; 74 74 } 75 75 … … 103 103 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); 104 104 105 rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;106 rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;105 RAT_GPR_SPECULATIVE [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy; 106 RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true; 107 107 } 108 108 … … 116 116 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); 117 117 118 rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;119 rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;118 RAT_SPR_SPECULATIVE [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy; 119 RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true; 120 120 } 121 121 } … … 160 160 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); 161 161 162 rat_gpr_not_speculative[front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;162 RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; 163 163 } 164 164 } … … 177 177 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); 178 178 179 rat_spr_not_speculative[front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;179 RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; 180 180 } 181 181 } … … 203 203 break; 204 204 else 205 str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index, rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative[i][j][index]);205 str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]); 206 206 } 207 207 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); … … 218 218 break; 219 219 else 220 str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index, rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative[i][j][index]);220 str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]); 221 221 } 222 222 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); … … 235 235 for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) 236 236 { 237 if ( rat_gpr_speculative_valid [i][j][x] and238 rat_gpr_speculative_valid [i][j][y] and239 ( rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))240 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));241 if ( rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])242 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));237 if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and 238 RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and 239 (RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y])) 240 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x])); 241 if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y]) 242 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x])); 243 243 244 244 } … … 246 246 for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) 247 247 { 248 if( rat_spr_speculative_valid [i][j][x] and249 rat_spr_speculative_valid [i][j][y] and250 ( rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))251 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));252 if ( rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])253 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));248 if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and 249 RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and 250 (RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y])) 251 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x])); 252 if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y]) 253 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x])); 254 254 255 255 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r139 r145 17 17 namespace register_translation_unit { 18 18 namespace stat_list_unit { 19 20 21 #if (DEBUG >= DEBUG_TRACE) 22 # define dump_stat_list \ 23 do \ 24 { \ 25 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); \ 26 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); \ 27 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); \ 28 \ 29 for (uint32_t i=0; i<_param->_nb_bank; i++) \ 30 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) \ 31 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \ 32 i, \ 33 j, \ 34 (i<<_param->_shift_gpr)|j, \ 35 gpr_stat_list[i][j]._is_free, \ 36 gpr_stat_list[i][j]._is_link, \ 37 gpr_stat_list[i][j]._is_use \ 38 ); \ 39 for (uint32_t i=0; i<_param->_nb_bank; i++) \ 40 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) \ 41 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", \ 42 i, \ 43 j, \ 44 (i<<_param->_shift_spr)|j, \ 45 spr_stat_list[i][j]._is_free, \ 46 spr_stat_list[i][j]._is_link, \ 47 spr_stat_list[i][j]._is_use \ 48 ); \ 49 } \ 50 while (0) 51 #else 52 # define dump_stat_list 53 #endif 19 54 20 55 … … 107 142 for (uint32_t i=0; i<_param->_nb_bank; i++) 108 143 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 109 if (not gpr_stat_list [i][j]._is_free)144 if (not (gpr_stat_list [i][j]._is_free or gpr_stat_list [i][j].can_free())) 110 145 list_gpr_not_free+=toString((i<<_param->_shift_gpr)|j)+" "; 111 146 … … 114 149 for (uint32_t i=0; i<_param->_nb_bank; i++) 115 150 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 116 if (not spr_stat_list [i][j]._is_free)151 if (not (spr_stat_list [i][j]._is_free or spr_stat_list [i][j].can_free())) 117 152 list_spr_not_free+=toString((i<<_param->_shift_spr)|j)+" "; 153 154 if (error_nb_gpr_free or 155 error_nb_spr_free or 156 error_rob_nb_gpr_free or 157 error_rob_nb_spr_free) 158 dump_stat_list; 118 159 119 160 if (error_nb_gpr_free) … … 334 375 335 376 336 #if (DEBUG >= DEBUG_TRACE) 337 { 338 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); 339 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); 340 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); 341 342 for (uint32_t i=0; i<_param->_nb_bank; i++) 343 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 344 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", 345 i, 346 j, 347 (i<<_param->_shift_gpr)|j, 348 gpr_stat_list[i][j]._is_free, 349 gpr_stat_list[i][j]._is_link, 350 gpr_stat_list[i][j]._is_use// , 351 // gpr_stat_list[i][j]._is_valid, 352 // gpr_stat_list[i][j]._counter 353 ); 354 for (uint32_t i=0; i<_param->_nb_bank; i++) 355 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 356 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, use %.1d", 357 i, 358 j, 359 (i<<_param->_shift_spr)|j, 360 spr_stat_list[i][j]._is_free, 361 spr_stat_list[i][j]._is_link, 362 spr_stat_list[i][j]._is_use// , 363 // spr_stat_list[i][j]._is_valid, 364 // spr_stat_list[i][j]._counter 365 ); 366 } 367 #endif 377 dump_stat_list; 378 368 379 369 380 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h
r139 r145 144 144 public : SC_IN (Tdepth_t ) *** in_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context] 145 145 146 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 147 public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] 148 public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] 149 public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] 150 146 151 // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 147 152 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
r139 r145 123 123 ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 124 124 ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 125 // 126 // 127 // 128 // 129 // 130 // 125 // ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 126 // ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); 127 // ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 128 // ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ); 129 // ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 130 // ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ); 131 131 ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 132 132 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic); … … 155 155 156 156 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 157 } 158 159 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 { 161 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 162 163 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 164 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 165 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 166 167 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 157 168 } 158 169 … … 429 440 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_DEPTH"); 430 441 } 442 } 443 444 for (uint32_t i=0; i<_param->_nb_front_end; i++) 445 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 446 { 447 dest = _name; 448 449 #ifdef POSITION 450 _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j), 451 dest,"depth_"+toString(i)+"_"+toString(j)); 452 #endif 453 if (_param->_have_port_depth) 454 { 455 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" , 456 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ); 457 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" , 458 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ); 459 } 460 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL", 461 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL"); 431 462 } 432 463 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp
r139 r145 102 102 DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ,_param->_rat_scheme == RAT_DEPTH_SAVE); 103 103 104 DELETE2_SIGNAL ( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 105 DELETE2_SIGNAL ( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 106 DELETE2_SIGNAL ( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 107 104 108 #ifdef DEBUG_TEST 105 109 DELETE0_SIGNAL ( in_INFO_ROB_EMPTY ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h
r139 r145 69 69 public : SC_OUT(Tcontext_t ) ** out_INSERT_CONTEXT_ID ;//[nb_inst_insert] 70 70 public : SC_OUT(Tdepth_t ) ** out_INSERT_DEPTH ;//[nb_inst_insert] 71 public : SC_OUT(Tcontrol_t ) ** out_INSERT_SAVE_RAT ;//[nb_inst_insert] 71 72 public : SC_OUT(Ttype_t ) ** out_INSERT_TYPE ;//[nb_inst_insert] 72 73 public : SC_OUT(Toperation_t ) ** out_INSERT_OPERATION ;//[nb_inst_insert] … … 82 83 public : SC_IN (Tcontext_t ) ** in_INSERT_RENAME_SELECT_CONTEXT_ID ;//[nb_inst_insert] 83 84 public : SC_IN (Tdepth_t ) ** in_INSERT_RENAME_SELECT_DEPTH ;//[nb_inst_insert] 85 public : SC_IN (Tcontrol_t ) ** in_INSERT_RENAME_SELECT_SAVE_RAT ;//[nb_inst_insert] 84 86 public : SC_IN (Ttype_t ) ** in_INSERT_RENAME_SELECT_TYPE ;//[nb_inst_insert] 85 87 public : SC_IN (Toperation_t ) ** in_INSERT_RENAME_SELECT_OPERATION ;//[nb_inst_insert] … … 94 96 public : SC_OUT(Tcontext_t ) ** out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ;//[nb_inst_insert] 95 97 public : SC_OUT(Tdepth_t ) ** out_INSERT_REGISTER_TRANSLATION_DEPTH ;//[nb_inst_insert] 98 public : SC_OUT(Tcontrol_t ) ** out_INSERT_REGISTER_TRANSLATION_SAVE_RAT ;//[nb_inst_insert] 96 99 public : SC_IN (Tspecial_address_t) ** in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW;//[nb_inst_insert] 97 100 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp
r139 r145 163 163 if (_param->_have_port_context_id) 164 164 sensitive << (*(in_INSERT_RENAME_SELECT_CONTEXT_ID [i])); 165 if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE)) 165 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 166 { 167 if (_param->_have_port_depth) 166 168 sensitive << (*(in_INSERT_RENAME_SELECT_DEPTH [i])); 169 sensitive << (*(in_INSERT_RENAME_SELECT_SAVE_RAT [i])); 170 } 167 171 sensitive << (*(in_INSERT_RENAME_SELECT_TYPE [i])) 168 172 << (*(in_INSERT_RENAME_SELECT_OPERATION [i])) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp
r139 r145 66 66 ALLOC1_SIGNAL_OUT (out_INSERT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); 67 67 ALLOC1_SIGNAL_OUT_COND(out_INSERT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE); 68 ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT ,"SAVE_RAT" ,Tcontrol_t ,1,_param->_rat_scheme == RAT_DEPTH_SAVE); 68 69 ALLOC1_SIGNAL_OUT (out_INSERT_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type); 69 70 ALLOC1_SIGNAL_OUT (out_INSERT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); … … 79 80 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_CONTEXT_ID ,"RENAME_SELECT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); 80 81 ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_DEPTH ,"RENAME_SELECT_DEPTH" ,Tdepth_t ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE); 82 ALLOC1_SIGNAL_IN_COND ( in_INSERT_RENAME_SELECT_SAVE_RAT ,"RENAME_SELECT_SAVE_RAT" ,Tcontrol_t ,1,_param->_rat_scheme == RAT_DEPTH_SAVE); 81 83 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_TYPE ,"RENAME_SELECT_TYPE" ,Ttype_t ,_param->_size_type); 82 84 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_OPERATION ,"RENAME_SELECT_OPERATION" ,Toperation_t ,_param->_size_operation); … … 91 93 ALLOC1_SIGNAL_OUT (out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,"REGISTER_TRANSLATION_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); 92 94 ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_DEPTH ,"REGISTER_TRANSLATION_DEPTH" ,Tdepth_t ,_param->_size_depth,_param->_rat_scheme == RAT_DEPTH_SAVE); 95 ALLOC1_SIGNAL_OUT_COND(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT ,"REGISTER_TRANSLATION_SAVE_RAT" ,Tcontrol_t ,1,_param->_rat_scheme == RAT_DEPTH_SAVE); 93 96 ALLOC1_SIGNAL_IN ( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,"REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_size_special_register); 94 97 ALLOC1_SIGNAL_OUT (out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,"LOAD_STORE_QUEUE_POINTER_VAL" ,Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp
r139 r145 32 32 Tcontext_t FRONT_END_ID = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_RENAME_SELECT_FRONT_END_ID [i]):0; 33 33 Tcontext_t CONTEXT_ID = (_param->_have_port_context_id )?PORT_READ(in_INSERT_RENAME_SELECT_CONTEXT_ID [i]):0; 34 Tdepth_t DEPTH = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH [i]):0; 34 Tdepth_t DEPTH = ((_param->_rat_scheme == RAT_DEPTH_SAVE) and _param->_have_port_depth)?PORT_READ(in_INSERT_RENAME_SELECT_DEPTH [i]):0; 35 Tcontrol_t SAVE_RAT = ( _param->_rat_scheme == RAT_DEPTH_SAVE )?PORT_READ(in_INSERT_RENAME_SELECT_SAVE_RAT [i]):0; 35 36 Ttype_t TYPE = PORT_READ(in_INSERT_RENAME_SELECT_TYPE [i]); 36 37 Toperation_t OPERATION = PORT_READ(in_INSERT_RENAME_SELECT_OPERATION [i]); … … 97 98 PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID [i],CONTEXT_ID ); 98 99 PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID [i],CONTEXT_ID ); 99 } 100 if (_param->_have_port_depth and (_param->_rat_scheme == RAT_DEPTH_SAVE)) 101 { 100 } 101 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 102 { 103 if (_param->_have_port_depth) 104 { 102 105 PORT_WRITE(out_INSERT_DEPTH [i],DEPTH ); 103 106 PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_DEPTH [i],DEPTH ); 107 } 108 PORT_WRITE(out_INSERT_SAVE_RAT [i],SAVE_RAT ); 109 PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_SAVE_RAT [i],SAVE_RAT ); 104 110 } 105 111 PORT_WRITE(out_INSERT_TYPE [i],TYPE ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
r139 r145 117 117 public : SC_OUT(Tcontrol_t ) ** out_INSERT_LAST_EVENT ;//[nb_inst_insert] 118 118 public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] 119 public : SC_OUT(Tcontrol_t ) ** out_INSERT_SAVE_RAT ;//[nb_inst_insert] 119 120 #ifdef DEBUG 120 121 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] … … 194 195 public : SC_IN (Tspr_t ) *** in_SPR_READ_SR ;//[nb_front_end][nb_context] 195 196 197 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 198 public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] 199 public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] 200 public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] 201 196 202 // ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 197 203 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r139 r145 15 15 namespace ooo_engine { 16 16 namespace rename_unit { 17 18 19 17 20 18 #undef FUNCTION … … 101 99 ALLOC1_INTERFACE_BEGIN("insert",OUT,WEST , _("Instruction with physical register"), _param->_nb_inst_insert); 102 100 103 ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); 104 ALLOC1_VALACK_IN ( in_INSERT_ACK ,ACK); 105 ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 106 ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 107 ALLOC1_SIGNAL_OUT(out_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 108 #ifdef STATISTICS 109 ALLOC1_SIGNAL_OUT(out_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32); 110 #endif 111 ALLOC1_SIGNAL_OUT(out_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 112 ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 113 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 114 ALLOC1_SIGNAL_OUT(out_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ); 115 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 101 ALLOC1_VALACK_OUT (out_INSERT_VAL ,VAL); 102 ALLOC1_VALACK_IN ( in_INSERT_ACK ,ACK); 103 ALLOC1_SIGNAL_OUT (out_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 104 ALLOC1_SIGNAL_OUT (out_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 105 ALLOC1_SIGNAL_OUT (out_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 106 #ifdef STATISTICS 107 ALLOC1_SIGNAL_OUT (out_INSERT_INSTRUCTION ,"instruction" ,uint32_t ,32); 108 #endif 109 ALLOC1_SIGNAL_OUT (out_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 110 ALLOC1_SIGNAL_OUT (out_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 111 ALLOC1_SIGNAL_OUT (out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 112 ALLOC1_SIGNAL_OUT (out_INSERT_LAST_EVENT ,"last_event" ,Tcontrol_t ,1 ); 113 ALLOC1_SIGNAL_OUT (out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 114 ALLOC1_SIGNAL_OUT_COND(out_INSERT_SAVE_RAT ,"save_rat" ,Tcontrol_t ,1 ,_param->_rat_scheme == RAT_DEPTH_SAVE); 116 115 #ifdef DEBUG 117 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address );118 #endif 119 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address );120 ALLOC1_SIGNAL_OUT (out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 );121 ALLOC1_SIGNAL_OUT (out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data );122 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr );123 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr );124 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1 );125 ALLOC1_SIGNAL_OUT (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr );126 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use );127 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );128 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 );129 #ifdef DEBUG 130 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic);131 #endif 132 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register );133 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 );134 #ifdef DEBUG 135 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic);136 #endif 137 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register );138 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 );139 #ifdef DEBUG 140 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic);141 #endif 142 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register );143 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );144 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic);145 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register );146 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register );147 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );148 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic);149 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register );150 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register );116 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 117 #endif 118 ALLOC1_SIGNAL_OUT (out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 119 ALLOC1_SIGNAL_OUT (out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 120 ALLOC1_SIGNAL_OUT (out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 121 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 122 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_PTR_READ ,"store_queue_ptr_read" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 123 ALLOC1_SIGNAL_OUT (out_INSERT_STORE_QUEUE_EMPTY ,"store_queue_empty" ,Tcontrol_t ,1 ); 124 ALLOC1_SIGNAL_OUT (out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 125 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use ); 126 ALLOC1_SIGNAL_OUT (out_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 127 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 128 #ifdef DEBUG 129 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 130 #endif 131 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); 132 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); 133 #ifdef DEBUG 134 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 135 #endif 136 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ); 137 ALLOC1_SIGNAL_OUT (out_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); 138 #ifdef DEBUG 139 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic); 140 #endif 141 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ); 142 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 143 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic); 144 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ); 145 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ); 146 ALLOC1_SIGNAL_OUT (out_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 147 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic); 148 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); 149 ALLOC1_SIGNAL_OUT (out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); 151 150 152 151 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); … … 210 209 211 210 ALLOC2_INTERFACE_END(_param->_nb_front_end, _param->_nb_context[it1]); 211 } 212 213 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 214 { 215 ALLOC2_INTERFACE_BEGIN("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); 216 217 _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 218 _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); 219 _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); 220 221 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); 212 222 } 213 223 … … 440 450 #endif 441 451 452 if (_param->_rat_scheme != RAT_DEPTH_SAVE) 442 453 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_SAVE_RAT" , 443 454 dest, "in_RENAME_" +toString(i)+"_SAVE_RAT" ); … … 483 494 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_DEPTH" , 484 495 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_DEPTH" ); 496 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 497 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_SAVE_RAT" , 498 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_SAVE_RAT" ); 485 499 COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_TYPE" , 486 500 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_TYPE" ); … … 559 573 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_DEPTH" , 560 574 dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_DEPTH" ); 575 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 576 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_SAVE_RAT" , 577 dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_SAVE_RAT" ); 561 578 562 579 // in_RENAME_SAVE_RAS - rename_select … … 733 750 } 734 751 752 for (uint32_t i=0; i<_param->_nb_front_end; i++) 753 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 754 { 755 dest = _name; 756 757 #ifdef POSITION 758 _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j), 759 dest,"depth_"+toString(i)+"_"+toString(j)); 760 #endif 761 if (_param->_have_port_depth) 762 { 763 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" , 764 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN" ); 765 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" , 766 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX" ); 767 } 768 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL", 769 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL"); 770 } 735 771 736 772 #ifdef DEBUG_TEST … … 909 945 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_DEPTH" , 910 946 dest,"out_INSERT_"+toString(i)+"_DEPTH" ); 947 if (_param->_rat_scheme == RAT_DEPTH_SAVE) 948 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_SAVE_RAT" , 949 dest,"out_INSERT_"+toString(i)+"_SAVE_RAT" ); 911 950 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_TYPE" , 912 951 dest,"out_INSERT_"+toString(i)+"_TYPE" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
r139 r145 75 75 DELETE1_SIGNAL (out_INSERT_LAST_EVENT ,_param->_nb_inst_insert,1 ); 76 76 DELETE1_SIGNAL (out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); 77 DELETE1_SIGNAL_COND(out_INSERT_SAVE_RAT ,_param->_nb_inst_insert,1 ,_param->_rat_scheme == RAT_DEPTH_SAVE); 77 78 #ifdef DEBUG 78 79 DELETE1_SIGNAL (out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_instruction_address ); … … 147 148 DELETE2_SIGNAL_COND( in_RETIRE_EVENT_DEPTH ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ,_param->_rat_scheme == RAT_DEPTH_SAVE); 148 149 149 DELETE2_SIGNAL (in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); 150 DELETE2_SIGNAL ( in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); 151 152 DELETE2_SIGNAL ( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 153 DELETE2_SIGNAL ( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth); 154 DELETE2_SIGNAL ( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 150 155 151 156 #ifdef DEBUG_TEST -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r139 r145 208 208 public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 209 209 public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] 210 210 211 211 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 212 212 public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
r139 r145 98 98 public : uint32_t * _rename_unit_size_front_end_id ;//[nb_rename_unit] 99 99 public : uint32_t * _rename_unit_size_context_id ;//[nb_rename_unit] 100 public : Trat_scheme_t * _commit_unit_rat_scheme ;//[nb_front_end]101 100 public : uint32_t _max_nb_context ; 102 101 public : uint32_t _max_branch_speculated ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r139 r145 534 534 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , 535 535 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); 536 if (_param->_rat_scheme[i] == RAT_DEPTH_SAVE) 537 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_SAVE_RAT" , 538 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_SAVE_RAT" ); 536 539 // COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_HAVE_EVENT" , 537 540 // dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_HAVE_EVENT" ); … … 633 636 #endif 634 637 635 636 637 638 COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_VAL" , 638 639 dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_VAL" ); … … 670 671 COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_LOAD_QUEUE_PTR_WRITE" , 671 672 dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); 672 // 673 // 674 // 675 // 676 // 677 // 678 // 679 // 680 // 681 // 682 // 683 // 673 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RA" , 674 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA" ); 675 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RA_PHY" , 676 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY" ); 677 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RB" , 678 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB" ); 679 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RB_PHY" , 680 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY" ); 681 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RC" , 682 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC" ); 683 // COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RC_PHY" , 684 // dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY" ); 684 685 COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_LOG" , 685 686 dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_LOG" ); … … 755 756 } 756 757 } 758 759 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 760 { 761 std::vector<uint32_t>::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); 762 uint32_t x = 0; 763 for (uint32_t j=0; j<_param->_nb_front_end; j++) 764 if (j == *it) 765 { 766 for (uint32_t k=0; k<_param->_nb_context[j]; k++) 767 { 768 dest = _name; 769 770 #ifdef POSITION 771 _component->interface_map (src ,"spr_read_"+toString(x)+"_"+toString(k), 772 dest,"spr_" +toString(j)+"_"+toString(k)); 773 #endif 774 775 if (_param->_have_port_depth) 776 { 777 PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MIN" , 778 dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MIN" ); 779 PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_MAX" , 780 dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MAX" ); 781 } 782 PORT_MAP(_component,src , "in_DEPTH_"+toString(x)+"_"+toString(k)+"_FULL", 783 dest, "in_DEPTH_"+toString(j)+"_"+toString(k)+"_FULL"); 784 } 785 x++; 786 ++it; 787 } 788 } 789 757 790 758 791 // ~~~~~[ Interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 919 952 // out_RETIRE_CONTEXT_ID - component_rename_unit 920 953 ////out_RETIRE_RENAME_UNIT_ID - component_rename_unit 954 // out_RETIRE_DEPTH - component_rename_unit 921 955 // out_RETIRE_USE_STORE_QUEUE - component_rename_unit 922 956 // out_RETIRE_USE_LOAD_QUEUE - component_rename_unit … … 981 1015 COMPONENT_MAP(_component,src ,"out_COMMIT_"+toString(i)+"_NUM_REG_RD" , 982 1016 dest, "in_COMMIT_"+toString(i)+"_NUM_REG_RD" ); 983 //@@@@@@@@@@984 1017 } 985 1018 … … 1111 1144 } 1112 1145 1113 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1114 for (uint32_t i=0; i<_param->_nb_front_end; i++)1115 for (uint32_t j=0; j<_param->_nb_context[i]; j++)1116 {1117 dest = _name;1118 #ifdef POSITION1119 _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j),1120 dest,"depth_"+toString(i)+"_"+toString(j));1121 #endif1122 1123 if (_param->_have_port_depth)1124 {1125 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN",1126 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN");1127 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX",1128 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX");1129 }1130 PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL",1131 dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL");1132 }1146 // // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1147 // for (uint32_t i=0; i<_param->_nb_front_end; i++) 1148 // for (uint32_t j=0; j<_param->_nb_context[i]; j++) 1149 // { 1150 // dest = _name; 1151 //#ifdef POSITION 1152 // _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j), 1153 // dest,"depth_"+toString(i)+"_"+toString(j)); 1154 //#endif 1155 // 1156 // if (_param->_have_port_depth) 1157 // { 1158 // PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN", 1159 // dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN"); 1160 // PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX", 1161 // dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX"); 1162 // } 1163 // PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL", 1164 // dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL"); 1165 // } 1133 1166 1134 1167 // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
r139 r145 82 82 log_begin(OOO_Engine,FUNCTION); 83 83 84 _nb_front_end = nb_front_end ; 85 _nb_context = nb_context ; 86 _nb_rename_unit = nb_rename_unit ; 87 _nb_execute_loop = nb_execute_loop ; 88 _nb_inst_decod = nb_inst_decod ; 89 _nb_inst_insert = nb_inst_insert ; 90 _nb_inst_retire = nb_inst_retire ; 91 // _nb_inst_issue = nb_inst_issue ; 92 _nb_inst_execute = nb_inst_execute ; 93 _nb_inst_reexecute = nb_inst_reexecute ; 94 _nb_inst_commit = nb_inst_commit ; 95 _nb_inst_branch_complete = nb_inst_branch_complete ; 96 _nb_branch_speculated = nb_branch_speculated ; 97 _nb_rename_unit_select = nb_rename_unit_select ; 98 _nb_execute_loop_select = nb_execute_loop_select ; 99 // _size_general_data = size_general_data ; 100 // _size_special_data = size_special_data ; 101 _link_rename_unit_with_front_end = link_rename_unit_with_front_end ; 102 _size_re_order_buffer = size_re_order_buffer ; 103 _nb_re_order_buffer_bank = nb_re_order_buffer_bank ; 104 _retire_ooo_scheme = retire_ooo_scheme ; 105 _commit_priority = commit_priority ; 106 _commit_load_balancing = commit_load_balancing ; 107 _size_issue_queue = size_issue_queue ; 108 _issue_queue_scheme = issue_queue_scheme ; 109 _nb_issue_queue_bank = nb_issue_queue_bank ; 110 _issue_priority = issue_priority ; 111 _issue_load_balancing = issue_load_balancing ; 112 // _table_routing = table_routing ; 113 // _table_issue_type = table_issue_type ; 114 _size_reexecute_queue = size_reexecute_queue ; 115 _rename_select_priority = rename_select_priority ; 116 _rename_select_load_balancing = rename_select_load_balancing ; 117 _rename_select_nb_front_end_select = rename_select_nb_front_end_select; 118 _nb_general_register = nb_general_register ; 119 _nb_special_register = nb_special_register ; 120 _rat_scheme = rat_scheme ; 121 _nb_reg_free = nb_reg_free ; 122 _nb_rename_unit_bank = nb_rename_unit_bank ; 123 // _size_read_counter = size_read_counter ; 124 _nb_load_store_queue = nb_load_store_queue ; 125 _size_store_queue = size_store_queue ; 126 _size_load_queue = size_load_queue ; 127 _nb_inst_memory = nb_inst_memory ; 128 _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; 129 _implement_group = implement_group ; 130 84 _nb_front_end = nb_front_end ; 85 _nb_context = nb_context ; 86 _nb_rename_unit = nb_rename_unit ; 87 _nb_execute_loop = nb_execute_loop ; 88 _nb_inst_decod = nb_inst_decod ; 89 _nb_inst_insert = nb_inst_insert ; 90 _nb_inst_retire = nb_inst_retire ; 91 // _nb_inst_issue = nb_inst_issue ; 92 _nb_inst_execute = nb_inst_execute ; 93 _nb_inst_reexecute = nb_inst_reexecute ; 94 _nb_inst_commit = nb_inst_commit ; 95 _nb_inst_branch_complete = nb_inst_branch_complete ; 96 _nb_branch_speculated = nb_branch_speculated ; 97 _nb_rename_unit_select = nb_rename_unit_select ; 98 _nb_execute_loop_select = nb_execute_loop_select ; 99 // _size_general_data = size_general_data ; 100 // _size_special_data = size_special_data ; 101 _link_rename_unit_with_front_end = link_rename_unit_with_front_end ; 102 _size_re_order_buffer = size_re_order_buffer ; 103 _nb_re_order_buffer_bank = nb_re_order_buffer_bank ; 104 _retire_ooo_scheme = retire_ooo_scheme ; 105 _commit_priority = commit_priority ; 106 _commit_load_balancing = commit_load_balancing ; 107 _size_issue_queue = size_issue_queue ; 108 _issue_queue_scheme = issue_queue_scheme ; 109 _nb_issue_queue_bank = nb_issue_queue_bank ; 110 _issue_priority = issue_priority ; 111 _issue_load_balancing = issue_load_balancing ; 112 // _table_routing = table_routing ; 113 // _table_issue_type = table_issue_type ; 114 _size_reexecute_queue = size_reexecute_queue ; 115 _rename_select_priority = rename_select_priority ; 116 _rename_select_load_balancing = rename_select_load_balancing ; 117 _rename_select_nb_front_end_select = rename_select_nb_front_end_select; 118 _nb_general_register = nb_general_register ; 119 _nb_special_register = nb_special_register ; 120 _rat_scheme = rat_scheme ; 121 _nb_reg_free = nb_reg_free ; 122 _nb_rename_unit_bank = nb_rename_unit_bank ; 123 // _size_read_counter = size_read_counter ; 124 _nb_load_store_queue = nb_load_store_queue ; 125 _size_store_queue = size_store_queue ; 126 _size_load_queue = size_load_queue ; 127 _nb_inst_memory = nb_inst_memory ; 128 _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; 129 _implement_group = implement_group ; 131 130 _nb_thread = nb_thread ; 132 131 _translate_num_context_to_num_thread = translate_num_context_to_num_thread; … … 144 143 _link_front_end_with_rename_unit[num_rename_unit].push_back(i); 145 144 } 145 146 146 _rename_unit_size_front_end_id = new uint32_t [_nb_rename_unit]; 147 147 _rename_unit_size_context_id = new uint32_t [_nb_rename_unit]; … … 197 197 } 198 198 } 199 200 ALLOC1(_commit_unit_rat_scheme,Trat_scheme_t,_nb_front_end);201 202 for (uint32_t num_front_end=0; num_front_end<_nb_front_end; ++num_front_end)203 _commit_unit_rat_scheme [num_front_end] = rat_scheme [_link_rename_unit_with_front_end [num_front_end]];204 199 205 200 _max_nb_context = max<uint32_t>(_nb_context,_nb_front_end); … … 265 260 _param_commit_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters 266 261 ( 267 _nb_front_end , 268 _nb_context , 269 _nb_rename_unit , 270 _size_re_order_buffer , 271 _nb_re_order_buffer_bank , 272 _retire_ooo_scheme , 273 _nb_inst_insert , 274 _nb_inst_retire , 275 _nb_inst_commit , 276 _nb_inst_reexecute , 277 _nb_inst_branch_complete , 278 _nb_branch_speculated , 279 size_nb_inst_decod , 280 size_general_data , 281 size_store_queue_ptr , 282 size_load_queue_ptr , 283 size_general_register , 284 size_special_register , 285 _commit_unit_rat_scheme , 286 _issue_priority , 287 _issue_load_balancing , 288 _nb_rename_unit_select , 289 _nb_thread , 262 _nb_front_end , 263 _nb_context , 264 _nb_rename_unit , 265 _size_re_order_buffer , 266 _nb_re_order_buffer_bank , 267 _retire_ooo_scheme , 268 _nb_inst_insert , 269 _nb_inst_retire , 270 _nb_inst_commit , 271 _nb_inst_reexecute , 272 _nb_inst_branch_complete , 273 _nb_branch_speculated , 274 size_nb_inst_decod , 275 size_general_data , 276 size_store_queue_ptr , 277 size_load_queue_ptr , 278 size_general_register , 279 size_special_register , 280 _rat_scheme , 281 _link_front_end_with_rename_unit, 282 _issue_priority , 283 _issue_load_balancing , 284 _nb_rename_unit_select , 285 _nb_thread , 290 286 _translate_num_context_to_num_thread 291 287 ); … … 430 426 delete [] _link_front_end_with_rename_unit ; 431 427 432 DELETE1(_commit_unit_rat_scheme,_nb_front_end);433 434 428 for (uint32_t i=0; i<_nb_rename_unit; i++) 435 429 delete _param_rename_unit [i] ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp
r88 r145 36 36 test.error(toString(_("Front_end [%d] is linked with invalid rename_unit.\n"),i)); 37 37 else 38 _is_link [x] = true; 38 { 39 if (_is_link [x]) 40 test.error(toString(_("Front_end [%d] can't be connected with multiple rename_unit.\n"),i)); 41 else 42 _is_link [x] = true; 43 } 39 44 } 40 45
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