- Timestamp:
- Dec 31, 2008, 11:18:08 AM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine
- Files:
-
- 29 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r97 r98 35 35 // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); 36 36 // _usage = usage_unset(_usage,USE_POSITION ); 37 _usage = usage_unset(_usage,USE_STATISTICS );37 // _usage = usage_unset(_usage,USE_STATISTICS ); 38 38 // _usage = usage_unset(_usage,USE_INFORMATION ); 39 39 … … 139 139 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 140 140 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); 141 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ FLAG ,"out_BRANCH_COMPLETE_FLAG",Tcontrol_t ,_param->_nb_inst_branch_complete);141 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 142 142 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); 143 143 ALLOC_SC_SIGNAL (out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); … … 282 282 INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 283 283 INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 284 INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);284 INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 285 285 INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 286 286 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL ); … … 678 678 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 679 679 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 680 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ FLAG,_param->_nb_inst_branch_complete);680 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 681 681 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); 682 682 DELETE_SC_SIGNAL (out_UPDATE_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r97 r98 57 57 public : counter_t * _stat_nb_inst_commit; 58 58 public : counter_t * _stat_nb_inst_commit_conflit_access; 59 public : counter_t ** _stat_nb_inst_retire; 59 public : counter_t ** _stat_nb_inst_retire_ok; 60 public : counter_t ** _stat_nb_inst_retire_ko; 60 61 public : counter_t ** _stat_bank_nb_inst;// [nb_bank] 61 62 #endif … … 161 162 public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] 162 163 public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] 163 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] 164 //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] 165 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] 164 166 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] 165 167 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r97 r98 167 167 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); 168 168 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 169 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t ,1); 169 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t ,1); 170 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); 170 171 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 171 172 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r88 r98 108 108 DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr); 109 109 110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1 111 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1 110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); 111 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); 112 112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); 113 113 DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete,_param->_size_front_end_id); 114 114 DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); 115 115 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); 116 DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1 ); 117 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1 ); 116 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1); 117 DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); 118 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); 118 119 119 120 DELETE_SIGNAL (out_UPDATE_VAL ,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r88 r98 86 86 87 87 if (_param->_have_port_context_id) 88 PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id 88 PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); 89 89 if (_param->_have_port_front_end_id) 90 PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id 90 PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); 91 91 if (_param->_have_port_depth) 92 PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); 93 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->data_commit ); 94 PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i], (entry->flags&FLAG_F)!=0 ); 92 PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); 93 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->data_commit ); 94 // PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i],(entry->flags&FLAG_F)!=0); 95 PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); 95 96 96 97 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
r88 r98 28 28 29 29 _stat_nb_inst_insert = new counter_t * [_param->_nb_rename_unit]; 30 _stat_nb_inst_retire = new counter_t * [_param->_nb_rename_unit]; 30 _stat_nb_inst_retire_ok = new counter_t * [_param->_nb_rename_unit]; 31 _stat_nb_inst_retire_ko = new counter_t * [_param->_nb_rename_unit]; 31 32 _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; 32 33 33 34 { 34 std::string sum_nb_inst_insert = ""; 35 std::string sum_nb_inst_retire = ""; 35 std::string sum_nb_inst_insert = "0"; 36 std::string sum_nb_inst_retire_ok = "0"; 37 std::string sum_nb_inst_retire_ko = "0"; 36 38 37 39 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 38 40 { 39 _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_"+toString(i)); 40 _stat_nb_inst_retire [i] = _stat->create_variable("nb_inst_retire_"+toString(i)); 41 _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_" +toString(i)); 42 _stat_nb_inst_retire_ok [i] = _stat->create_variable("nb_inst_retire_ok_"+toString(i)); 43 _stat_nb_inst_retire_ko [i] = _stat->create_variable("nb_inst_retire_ko_"+toString(i)); 41 44 42 45 _stat->create_expr_average_by_cycle("average_use_interface_insert_"+toString(i), "nb_inst_insert_"+toString(i), "", toString(_("Average instruction by cycle on insert interface (rename_unit %d)"),i)); 43 _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), " nb_inst_retire_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i));46 _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "+ nb_inst_retire_ok_"+toString(i)+" nb_inst_retire_ko_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i)); 44 47 _stat->create_expr_percent ("percent_use_interface_insert_"+toString(i) , "average_use_interface_insert_"+toString(i), toString(_param->_nb_inst_insert [i]), toString(_("Percent usage of insert interface (rename_unit %d)"),i)); 45 48 _stat->create_expr_percent ("percent_use_interface_retire_"+toString(i) , "average_use_interface_retire_"+toString(i), toString(_param->_nb_inst_retire [i]), toString(_("Percent usage of retire interface (rename_unit %d)"),i)); 46 49 47 if (i == 0) 48 { 49 sum_nb_inst_insert = "nb_inst_insert_"+toString(i); 50 sum_nb_inst_retire = "nb_inst_retire_"+toString(i); 51 } 52 else 53 { 54 sum_nb_inst_insert = "+ nb_inst_insert_"+toString(i) + " " +sum_nb_inst_insert; 55 sum_nb_inst_retire = "+ nb_inst_retire_"+toString(i) + " " +sum_nb_inst_retire; 56 } 50 sum_nb_inst_insert = "+ nb_inst_insert_"+ toString(i) + " " +sum_nb_inst_insert; 51 sum_nb_inst_retire_ok = "+ nb_inst_retire_ok_"+toString(i) + " " +sum_nb_inst_retire_ok; 52 sum_nb_inst_retire_ko = "+ nb_inst_retire_ko_"+toString(i) + " " +sum_nb_inst_retire_ko; 57 53 } 58 54 59 _stat->create_expr_average_by_cycle("average_inst_insert", sum_nb_inst_insert, "", _("Average instruction insert by cycle")); 60 _stat->create_expr_average_by_cycle("average_inst_retire", sum_nb_inst_retire, "", _("Average instruction retire by cycle")); 55 _stat->create_expr_average_by_cycle("average_inst_insert" , sum_nb_inst_insert , "", _("Average instruction insert by cycle")); 56 _stat->create_expr_average_by_cycle("average_inst_retire_ok", sum_nb_inst_retire_ok, "", _("Average instruction retire ok by cycle (IPC)")); 57 _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle")); 58 _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); 61 59 } 62 60 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
r88 r98 28 28 29 29 delete [] _stat_nb_inst_insert; 30 delete [] _stat_nb_inst_retire; 30 delete [] _stat_nb_inst_retire_ok; 31 delete [] _stat_nb_inst_retire_ko; 31 32 delete [] _stat_bank_nb_inst; 32 33 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r97 r98 281 281 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); 282 282 283 #ifdef STATISTICS284 if (usage_is_set(_usage,USE_STATISTICS))285 (*_stat_nb_inst_retire [x]) ++;286 #endif287 288 283 #ifdef DEBUG_TEST 289 284 if (not PORT_READ(in_RETIRE_ACK [x][y])) … … 291 286 #endif 292 287 293 294 288 entry_t * entry = _rob [i].front(); 295 289 #ifdef STATISTICS 290 if (usage_is_set(_usage,USE_STATISTICS)) 291 { 292 rob_state_t state = entry->state; 293 294 if (state == ROB_END_OK) 295 (*_stat_nb_inst_retire_ok [x]) ++; 296 else 297 (*_stat_nb_inst_retire_ko [x]) ++; 298 } 299 #endif 300 296 301 Tcontext_t front_end_id = entry->front_end_id; 297 302 Tcontext_t context_id = entry->context_id ; … … 478 483 it++) 479 484 { 480 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d",485 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 481 486 x, 482 487 (*it)->front_end_id , … … 487 492 (*it)->operation , 488 493 (*it)->address , 494 (*it)->address << 2 , 489 495 (*it)->is_delay_slot , 490 496 (*it)->use_store_queue , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp
r97 r98 21 21 { 22 22 log_begin(Reexecute_unit,FUNCTION); 23 log_function(Reexecute_unit,FUNCTION,_name.c_str()); 23 24 24 25 // Initialisation -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp
r88 r98 22 22 { 23 23 log_begin(Reexecute_unit,FUNCTION); 24 log_function(Reexecute_unit,FUNCTION,_name.c_str()); 24 25 25 26 // =================================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp
r88 r98 22 22 { 23 23 log_begin(Reexecute_unit,FUNCTION); 24 log_function(Reexecute_unit,FUNCTION,_name.c_str()); 24 25 25 26 // =================================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp
r88 r98 22 22 { 23 23 log_begin(Reexecute_unit,FUNCTION); 24 log_function(Reexecute_unit,FUNCTION,_name.c_str()); 24 25 25 26 if (PORT_READ(in_NRESET) == 0) … … 135 136 } 136 137 138 #if ((DEBUG >= DEBUG_TRACE) and DEBUG_Reexecute_unit) 139 log_printf(TRACE,Reexecute_unit,FUNCTION," * Dump Reexecute_queue"); 140 141 for (uint32_t i=0; i<_param->_nb_bank; ++i) 142 { 143 uint32_t j=0; 144 for (std::list<entry_t *>::iterator it=_reexecute_queue[i].begin(); 145 it!=_reexecute_queue[i].end(); 146 ++it) 147 { 148 log_printf(TRACE,Reexecute_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d, %.1d %.1d, %.4d %.4d, %.8x (%.2d %.4d) %.8x, %.1d %.5d, %s", 149 i, 150 j, 151 (*it)->context_id , 152 (*it)->front_end_id , 153 (*it)->packet_id , 154 (*it)->spr_wen , 155 (*it)->reexecute , 156 (*it)->type , 157 (*it)->operation , 158 (*it)->address , 159 ((*it)->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group, 160 ((*it)->address ) & _param->_mask_spr_num_reg , 161 (*it)->data , 162 (*it)->write_rd , 163 (*it)->num_reg_rd , 164 toString((*it)->state).c_str()); 165 166 ++j; 167 } 168 } 169 // // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 170 // private : std::list<entry_t *> * _reexecute_queue ;//[nb_bank] 171 typedef struct 172 { 173 } entry_t; 174 175 #endif 176 137 177 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 138 178 end_cycle (); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
r88 r98 132 132 133 133 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 134 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%. 2d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]);134 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); 135 135 136 136 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 137 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%. 2d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]);137 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); 138 138 } 139 139 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp
r88 r98 50 50 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 51 51 52 ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL ," in_INSERT_RENAME_VAL ",Tcontrol_t,_param->_nb_inst_insert); 53 ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK ,"out_INSERT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); 54 ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL ,"out_INSERT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); 55 ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK ," in_INSERT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); 56 ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,"out_INSERT_RAT_INSERT_VAL",Tcontrol_t,_param->_nb_inst_insert); 57 ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK," in_INSERT_RAT_RENAME_ACK",Tcontrol_t,_param->_nb_inst_insert); 58 ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK," in_INSERT_RAT_INSERT_ACK",Tcontrol_t,_param->_nb_inst_insert); 59 ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); 60 ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); 61 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); 62 ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); 52 ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL ," in_INSERT_RENAME_VAL ",Tcontrol_t,_param->_nb_inst_insert); 53 ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK ,"out_INSERT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); 54 ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL ,"out_INSERT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); 55 ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK ," in_INSERT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); 56 ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,"out_INSERT_RAT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); 57 ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ," in_INSERT_RAT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); 58 ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ," in_INSERT_RAT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); 59 ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); 60 ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); 61 ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,"out_INSERT_FREE_LIST_GPR_VAL ",Tcontrol_t,_param->_nb_inst_insert); 62 ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,"out_INSERT_FREE_LIST_SPR_VAL ",Tcontrol_t,_param->_nb_inst_insert); 63 ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); 64 ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); 63 65 64 66 ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ," in_INSERT_DEPENDENCY_CHECKING_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); … … 126 128 (*(_Register_translation_unit_Glue->in_NRESET)) (*(in_NRESET)); 127 129 128 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); 129 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); 130 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); 131 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); 132 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert); 133 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert); 134 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert); 135 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); 136 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); 137 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); 138 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); 130 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); 131 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); 132 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); 133 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); 134 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert); 135 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert); 136 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert); 137 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); 138 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); 139 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert); 140 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert); 141 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); 142 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); 139 143 140 144 INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); … … 243 247 for (uint32_t i=0; i<_param->_nb_inst_insert;i++) 244 248 { 245 TEST(Tcontrol_t,out_INSERT_RENAME_ACK [i]->read(),(in_INSERT_INSERT_ACK [i]->read() and 246 in_INSERT_RAT_RENAME_ACK [i]->read() and 247 in_INSERT_RAT_INSERT_ACK [i]->read() and 248 in_INSERT_FREE_LIST_ACK [i]->read() and 249 in_INSERT_STAT_LIST_ACK [i]->read() )); 250 TEST(Tcontrol_t,out_INSERT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 251 in_INSERT_RAT_RENAME_ACK [i]->read() and 252 in_INSERT_RAT_INSERT_ACK [i]->read() and 253 in_INSERT_FREE_LIST_ACK [i]->read() and 254 in_INSERT_STAT_LIST_ACK [i]->read() )); 255 TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 256 in_INSERT_INSERT_ACK [i]->read() and 257 in_INSERT_RAT_RENAME_ACK [i]->read() and 258 in_INSERT_FREE_LIST_ACK [i]->read() and 259 in_INSERT_STAT_LIST_ACK [i]->read() )); 260 TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 261 in_INSERT_INSERT_ACK [i]->read() and 262 in_INSERT_RAT_RENAME_ACK [i]->read() and 263 in_INSERT_RAT_INSERT_ACK [i]->read() and 264 in_INSERT_STAT_LIST_ACK [i]->read() )); 265 TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 266 in_INSERT_INSERT_ACK [i]->read() and 267 in_INSERT_RAT_RENAME_ACK [i]->read() and 268 in_INSERT_RAT_INSERT_ACK [i]->read() and 269 in_INSERT_FREE_LIST_ACK [i]->read() )); 249 TEST(Tcontrol_t,out_INSERT_RENAME_ACK [i]->read(),(in_INSERT_INSERT_ACK [i]->read() and 250 in_INSERT_RAT_RENAME_ACK [i]->read() and 251 in_INSERT_RAT_INSERT_ACK [i]->read() and 252 in_INSERT_FREE_LIST_ACK [i]->read() and 253 in_INSERT_STAT_LIST_ACK [i]->read() )); 254 TEST(Tcontrol_t,out_INSERT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 255 in_INSERT_RAT_RENAME_ACK [i]->read() and 256 in_INSERT_RAT_INSERT_ACK [i]->read() and 257 in_INSERT_FREE_LIST_ACK [i]->read() and 258 in_INSERT_STAT_LIST_ACK [i]->read() )); 259 TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 260 in_INSERT_INSERT_ACK [i]->read() and 261 in_INSERT_RAT_RENAME_ACK [i]->read() and 262 in_INSERT_FREE_LIST_ACK [i]->read() and 263 in_INSERT_STAT_LIST_ACK [i]->read() )); 264 TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 265 in_INSERT_INSERT_ACK [i]->read() and 266 in_INSERT_RAT_RENAME_ACK [i]->read() and 267 in_INSERT_RAT_INSERT_ACK [i]->read() and 268 in_INSERT_STAT_LIST_ACK [i]->read() )); 269 TEST(Tcontrol_t,out_INSERT_FREE_LIST_GPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD[i]->read() and 270 (in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG[i]->read()!=0))); 271 TEST(Tcontrol_t,out_INSERT_FREE_LIST_SPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE[i]->read())); 272 TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and 273 in_INSERT_INSERT_ACK [i]->read() and 274 in_INSERT_RAT_RENAME_ACK [i]->read() and 275 in_INSERT_RAT_INSERT_ACK [i]->read() and 276 in_INSERT_FREE_LIST_ACK [i]->read() )); 270 277 } 271 278 … … 295 302 delete in_NRESET; 296 303 297 DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); 298 DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); 299 DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); 300 DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); 301 DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert); 302 DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert); 303 DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert); 304 DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); 305 DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); 306 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); 307 DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); 304 DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); 305 DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); 306 DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); 307 DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); 308 DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert); 309 DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert); 310 DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert); 311 DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); 312 DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); 313 DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert); 314 DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert); 315 DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); 316 DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); 308 317 309 318 DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h
r88 r98 73 73 public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_VAL ;//[nb_inst_insert] 74 74 public : SC_IN (Tcontrol_t) ** in_INSERT_FREE_LIST_ACK ;//[nb_inst_insert] 75 public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_GPR_VAL ;//[nb_inst_insert] 76 public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_SPR_VAL ;//[nb_inst_insert] 75 77 public : SC_OUT(Tcontrol_t) ** out_INSERT_STAT_LIST_VAL ;//[nb_inst_insert] 76 78 public : SC_IN (Tcontrol_t) ** in_INSERT_STAT_LIST_ACK ;//[nb_inst_insert] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp
r88 r98 61 61 ALLOC1_INTERFACE("insert",OUT, EAST, "insert's interface", _param->_nb_inst_insert); 62 62 63 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); 64 ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK ,"rename_ack" ,Tcontrol_t,1); 65 ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL ,"insert_val" ,Tcontrol_t,1); 66 ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK ,"insert_ack" ,Tcontrol_t,1); 67 ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL,"rat_insert_val",Tcontrol_t,1); 68 ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK,"rat_rename_ack",Tcontrol_t,1); 69 ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK,"rat_insert_ack",Tcontrol_t,1); 70 ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL ,"free_list_val" ,Tcontrol_t,1); 71 ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK ,"free_list_ack" ,Tcontrol_t,1); 72 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1); 73 ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1); 63 ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); 64 ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK ,"rename_ack" ,Tcontrol_t,1); 65 ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL ,"insert_val" ,Tcontrol_t,1); 66 ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK ,"insert_ack" ,Tcontrol_t,1); 67 ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL ,"rat_insert_val" ,Tcontrol_t,1); 68 ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK ,"rat_rename_ack" ,Tcontrol_t,1); 69 ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK ,"rat_insert_ack" ,Tcontrol_t,1); 70 ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL ,"free_list_val" ,Tcontrol_t,1); 71 ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK ,"free_list_ack" ,Tcontrol_t,1); 72 ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_GPR_VAL ,"free_list_gpr_val" ,Tcontrol_t,1); 73 ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_SPR_VAL ,"free_list_spr_val" ,Tcontrol_t,1); 74 ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1); 75 ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1); 74 76 75 77 ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,"DEPENDENCY_CHECKING_READ_RA" ,Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp
r88 r98 30 30 delete in_NRESET; 31 31 32 DELETE1_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert,1); 35 DELETE1_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert,1); 36 DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert,1); 37 DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert,1); 38 DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert,1); 39 DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1); 40 DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1); 41 DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1); 42 DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1); 32 DELETE1_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert,1); 35 DELETE1_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert,1); 36 DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert,1); 37 DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert,1); 38 DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert,1); 39 DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1); 40 DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1); 41 DELETE1_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert,1); 42 DELETE1_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert,1); 43 DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1); 44 DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1); 43 45 44 46 DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp
r88 r98 36 36 Tcontrol_t WRITE_RD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD [i]); 37 37 Tgeneral_address_t NUM_REG_RD_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG [i]); 38 Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]);39 Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]);38 Tgeneral_address_t NUM_REG_RD_PHY_OLD = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]):0; 39 Tgeneral_address_t NUM_REG_RD_PHY_NEW = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]):0; 40 40 Tcontrol_t WRITE_RE = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE [i]); 41 41 Tspecial_address_t NUM_REG_RE_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG [i]); 42 42 Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD [i]); 43 43 Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i]); 44 45 PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL [i], WRITE_RD and (NUM_REG_RD_LOG!=0)); 46 PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL [i], WRITE_RE ); 44 47 45 48 PORT_WRITE(out_INSERT_STAT_LIST_READ_RA [i], READ_RA ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
r88 r98 384 384 #endif 385 385 386 PORT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" ,387 dest,"in_RENAME_"+toString(i)+"_WRITE_RD");388 PORT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" ,389 dest,"in_RENAME_"+toString(i)+"_WRITE_RE");390 391 386 dest = _name+"_register_translation_unit_glue"; 392 387 COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_VAL" , … … 394 389 COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_ACK" , 395 390 dest, "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" ); 391 COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" , 392 dest,"out_INSERT_"+toString(i)+"_FREE_LIST_GPR_VAL"); 393 COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" , 394 dest,"out_INSERT_"+toString(i)+"_FREE_LIST_SPR_VAL"); 396 395 397 396 dest = _name+"_dependency_checking_unit"; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r97 r98 132 132 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); 133 133 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); 134 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ FLAG ,"out_BRANCH_COMPLETE_FLAG",Tcontrol_t ,_param->_nb_inst_branch_complete);134 ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); 135 135 ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ," in_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); 136 136 … … 268 268 // INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); 269 269 270 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_ issue);271 INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_ issue);270 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); 271 INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); 272 272 if (_param->_have_port_front_end_id) 273 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_ issue);273 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); 274 274 if (_param->_have_port_context_id) 275 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_ issue);275 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); 276 276 if (_param->_have_port_depth) 277 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_ issue);278 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_ issue);279 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ FLAG ,_param->_nb_inst_issue);280 INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_ issue);277 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 278 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 279 INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 280 INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 281 281 282 282 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_VAL ); … … 433 433 DELETE1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); 434 434 435 // 436 // 437 // 438 // 439 // 440 // 441 // 442 // 443 // 444 // 445 446 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_ issue);447 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_ issue);448 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_ issue);449 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_ issue);450 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_ issue);451 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_ issue);452 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ FLAG ,_param->_nb_inst_issue);453 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_ issue);435 //DELETE1_SC_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire); 436 //DELETE1_SC_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire); 437 //DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); 438 //DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); 439 //DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); 440 //DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); 441 //DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); 442 //DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); 443 //DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); 444 //DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); 445 446 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); 447 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); 448 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); 449 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); 450 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); 451 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); 452 DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); 453 DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 454 454 455 455 DELETE_SC_SIGNAL (out_COMMIT_EVENT_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
r88 r98 34 34 public : Tspr_t read (void ) 35 35 { 36 return x =0;36 return x; 37 37 }; 38 38 public : void write (Tspr_t x) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp
r88 r98 148 148 { 149 149 _spr [i][j][k] = new SPR * [NB_REG_GROUP[k]]; 150 150 151 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 152 _spr [i][j][k][l] = NULL; 153 151 154 switch (k) 152 155 { … … 218 221 default : 219 222 { 220 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)221 _spr [i][j][k][l] = NULL;222 223 } 223 224 } … … 232 233 for (uint32_t k=0; k<NB_GROUP; k++) 233 234 if (_param->_implement_group [i][j][k]) 234 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 235 if (_spr [i][j][k][l] == NULL) 236 _spr_access_mode [i][j]->invalid_register (k,l); 235 { 236 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 237 if (_spr [i][j][k][l] == NULL) 238 _spr_access_mode [i][j]->invalid_register (k,l); 239 } 240 else 241 { 242 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 243 _spr_access_mode [i][j]->invalid_register (k,l); 244 } 237 245 238 246 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp
r88 r98 77 77 for (uint32_t k=0; k<NB_GROUP; k++) 78 78 { 79 if (_param->_implement_group [i][j][k])79 if (_spr [i][j][k] != NULL) 80 80 { 81 81 for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) 82 if (_spr [i][j][k] != NULL)82 if (_spr [i][j][k][l] != NULL) 83 83 delete _spr [i][j][k][l]; 84 84 delete [] _spr [i][j][k]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp
r88 r98 22 22 { 23 23 log_begin(Special_Register_unit,FUNCTION); 24 24 log_function(Special_Register_unit,FUNCTION,_name.c_str()); 25 25 26 26 // =================================================================== … … 28 28 // =================================================================== 29 29 for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) 30 // if (PORT_READ(in_SPR_ACCESS_VAL [i]) and not PORT_READ(in_SPR_ACCESS_WEN [i])) 30 // not necessery if have not read enable 31 if (PORT_READ(in_SPR_ACCESS_VAL [i])) 31 32 { 33 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_ACCESS [%d]",i); 34 32 35 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; 33 36 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; … … 35 38 Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); 36 39 40 log_printf(TRACE,Special_Register_unit,FUNCTION," * front_end_id : %d",front_end_id); 41 log_printf(TRACE,Special_Register_unit,FUNCTION," * context_id : %d",context_id ); 42 log_printf(TRACE,Special_Register_unit,FUNCTION," * num_group : %d",num_group ); 43 log_printf(TRACE,Special_Register_unit,FUNCTION," * num_reg : %d",num_reg ); 44 45 #ifdef DEBUG_TEST 46 if (not _spr_access_mode [front_end_id][context_id]->exist(num_group,num_reg)) 47 msgWarning("Access at an invalid special register (group %d, register %d)\n",num_group,num_reg); 48 #endif 49 37 50 SR * sr = static_cast<SR*>(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); 38 51 … … 43 56 sm, 44 57 sumra); 45 46 PORT_WRITE(out_SPR_ACCESS_RDATA [i], (valid)?_spr[front_end_id][context_id][num_group][num_reg]->read():0); 47 PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid); 58 59 log_printf(TRACE,Special_Register_unit,FUNCTION," * SM : %d",sm); 60 log_printf(TRACE,Special_Register_unit,FUNCTION," * SUMRA : %d",sumra); 61 log_printf(TRACE,Special_Register_unit,FUNCTION," * valid : %d",valid); 62 63 // ISA OpenRISC : no action/exception if unauthorised spr access. Also, read 0. 64 // if (not PORT_READ(in_SPR_ACCESS_WEN [i])) 65 // { 66 Tspr_t rdata = (valid)?(_spr[front_end_id][context_id][num_group][num_reg]->read()):0; 67 68 log_printf(TRACE,Special_Register_unit,FUNCTION," * rdata : %.8x",rdata); 69 70 PORT_WRITE(out_SPR_ACCESS_RDATA [i], rdata); 71 // } 72 PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid); 48 73 } 49 74 50 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)51 end_cycle ();52 #endif53 54 75 log_end(Special_Register_unit,FUNCTION); 55 76 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp
r88 r98 22 22 { 23 23 log_begin(Special_Register_unit,FUNCTION); 24 log_function(Special_Register_unit,FUNCTION,_name.c_str()); 24 25 25 26 // =================================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp
r97 r98 22 22 { 23 23 log_begin(Special_Register_unit,FUNCTION); 24 log_function(Special_Register_unit,FUNCTION,_name.c_str()); 24 25 25 26 if (PORT_READ(in_NRESET) == 0) … … 38 39 throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l)); 39 40 #endif 40 log_printf(TRACE,Special_Register_unit,FUNCTION," Reset SPR [%d][%d][%d][%d]",i,j,k,l);41 log_printf(TRACE,Special_Register_unit,FUNCTION," * Reset SPR [%d][%d][%d][%d]",i,j,k,l); 41 42 _spr [i][j][k][l]->reset(); 42 43 } … … 52 53 if (PORT_READ(in_SPR_ACCESS_WEN [i])) 53 54 { 55 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_ACCESS [%d]",i); 56 54 57 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; 55 58 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; … … 57 60 Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); 58 61 62 log_printf(TRACE,Special_Register_unit,FUNCTION," * front_end_id : %d",front_end_id); 63 log_printf(TRACE,Special_Register_unit,FUNCTION," * context_id : %d",context_id ); 64 log_printf(TRACE,Special_Register_unit,FUNCTION," * num_group : %d",num_group ); 65 log_printf(TRACE,Special_Register_unit,FUNCTION," * num_reg : %d",num_reg ); 66 59 67 SR * sr = static_cast<SR*>(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); 60 68 61 69 Tcontrol_t sm = sr->sm ; 62 70 Tcontrol_t sumra = sr->sumra; 71 Tcontrol_t valid = _spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg), 72 sm, 73 sumra); 74 log_printf(TRACE,Special_Register_unit,FUNCTION," * SM : %d",sm); 75 log_printf(TRACE,Special_Register_unit,FUNCTION," * SUMRA : %d",sumra); 76 log_printf(TRACE,Special_Register_unit,FUNCTION," * valid : %d",valid); 63 77 64 if (_spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg), 65 sm, 66 sumra)) 67 _spr[front_end_id][context_id][num_group][num_reg]->write(PORT_READ(in_SPR_ACCESS_WDATA [i])); 78 if (valid) 79 { 80 Tspr_t wdata = PORT_READ(in_SPR_ACCESS_WDATA [i]); 81 82 log_printf(TRACE,Special_Register_unit,FUNCTION," * wdata : %.8x",wdata); 83 84 _spr[front_end_id][context_id][num_group][num_reg]->write(wdata); 85 } 68 86 69 87 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r97 r98 157 157 public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] 158 158 public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] 159 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_ FLAG;//[nb_inst_branch_complete]159 public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] 160 160 public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] 161 161 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r97 r98 166 166 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); 167 167 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 168 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ FLAG ,"FLAG",Tcontrol_t ,1 );168 ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); 169 169 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); 170 170 } … … 909 909 PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , 910 910 dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); 911 PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ FLAG",912 dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ FLAG");911 PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" , 912 dest,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" ); 913 913 PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", 914 914 dest, "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
r88 r98 105 105 // DELETE1_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register ); 106 106 107 DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_ issue,1);108 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_ issue,1);109 DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_ issue,_param->_size_front_end_id);110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_ issue,_param->_size_context_id);111 DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_ issue,_param->_size_depth);112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_ issue,_param->_size_general_data);113 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ FLAG ,_param->_nb_inst_issue,1);114 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_ issue,1);107 DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1 ); 108 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1 ); 109 DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete,_param->_size_front_end_id); 110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); 111 DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); 112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_general_data); 113 DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); 114 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); 115 115 116 116 DELETE_SIGNAL (out_COMMIT_EVENT_VAL , 1);
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