- Timestamp:
- Jan 8, 2009, 2:06:27 PM (15 years ago)
- Location:
- trunk
- Files:
-
- 15 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r98 r100 220 220 private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] 221 221 private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 222 223 private : Tevent_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] 222 224 223 225 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r88 r100 27 27 typedef enum 28 28 { 29 ROB_EMPTY , // 30 ROB_BRANCH_WAIT_END , // 31 ROB_BRANCH_COMPLETE , // 32 ROB_STORE_WAIT_HEAD_OK , // 33 // ROB_STORE_WAIT_HEAD_KO , // 34 ROB_STORE_HEAD_OK , // 35 ROB_STORE_HEAD_KO , // 36 ROB_OTHER_WAIT_END , // 37 ROB_MISS_WAIT_END , // 38 ROB_END_OK_SPECULATIVE , // 39 ROB_END_OK , // 40 ROB_END_KO_SPECULATIVE , // 41 ROB_END_KO , // 42 ROB_END_MISS , // 43 ROB_END_EXCEPTION_WAIT_HEAD , // 29 ROB_EMPTY , // 30 ROB_BRANCH_WAIT_END , // 31 ROB_BRANCH_COMPLETE , // 32 ROB_STORE_WAIT_HEAD_OK , // 33 // ROB_STORE_WAIT_HEAD_KO , // 34 ROB_STORE_HEAD_OK , // 35 ROB_STORE_HEAD_KO , // 36 ROB_OTHER_WAIT_END , // 37 ROB_MISS_WAIT_END , // 38 ROB_END_OK_SPECULATIVE , // 39 ROB_END_OK , // 40 ROB_END_KO_SPECULATIVE , // 41 ROB_END_KO , // 42 ROB_END_BRANCH_MISS_SPECULATIVE, // 43 ROB_END_BRANCH_MISS , // 44 ROB_END_MISS , // 45 ROB_END_EXCEPTION_WAIT_HEAD , // 44 46 ROB_END_EXCEPTION // 45 47 } rob_state_t; … … 79 81 public : Tspecial_address_t num_reg_re_phy_new ; 80 82 81 public : Tevent_state_t event_state ;82 83 public : Texception_t exception ; 83 84 public : Texception_t exception_use ; … … 161 162 switch (x) 162 163 { 163 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY : return "empty" ; break; 164 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "branch_wait_end" ; break; 165 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "branch_complete" ; break; 166 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "store_wait_head_ok" ; break; 167 // case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "store_wait_head_ko" ; break; 168 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "store_head_ok" ; break; 169 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "store_head_ko" ; break; 170 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "other_wait_end" ; break; 171 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "miss_wait_end" ; break; 172 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "end_ok_speculative" ; break; 173 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "end_ok" ; break; 174 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE : return "end_ko_speculative" ; break; 175 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO : return "end_ko" ; break; 176 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "end_exception_wait_head" ; break; 177 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "end_exception" ; break; 164 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY : return "ROB_EMPTY" ; break; 165 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "ROB_BRANCH_WAIT_END" ; break; 166 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "ROB_BRANCH_COMPLETE" ; break; 167 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "ROB_STORE_WAIT_HEAD_OK" ; break; 168 // case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "ROB_STORE_WAIT_HEAD_KO" ; break; 169 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "ROB_STORE_HEAD_OK" ; break; 170 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "ROB_STORE_HEAD_KO" ; break; 171 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "ROB_OTHER_WAIT_END" ; break; 172 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "ROB_MISS_WAIT_END" ; break; 173 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "ROB_END_OK_SPECULATIVE" ; break; 174 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "ROB_END_OK" ; break; 175 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE : return "ROB_END_KO_SPECULATIVE" ; break; 176 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO : return "ROB_END_KO" ; break; 177 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break; 178 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS : return "ROB_END_BRANCH_MISS" ; break; 179 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS : return "ROB_END_MISS" ; break; 180 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "ROB_END_EXCEPTION_WAIT_HEAD" ; break; 181 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "ROB_END_EXCEPTION" ; break; 182 178 183 default : return "" ; break; 179 184 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r98 r100 272 272 273 273 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 274 _rob = new std::list<entry_t*> [_param->_nb_bank];274 ALLOC1(_rob ,std::list<entry_t*>,_param->_nb_bank); 275 275 276 reg_BANK_PTR = new uint32_t [_param->_nb_bank];277 278 reg_NB_INST_COMMIT_ALL = new Tcounter_t * [_param->_nb_front_end];279 reg_NB_INST_COMMIT_MEM = new Tcounter_t * [_param->_nb_front_end];276 ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank); 277 278 ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 279 ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 280 280 281 for (uint32_t i=0; i<_param->_nb_front_end; i++) 282 { 283 reg_NB_INST_COMMIT_ALL [i] = new Tcounter_t [_param->_nb_context [i]]; 284 reg_NB_INST_COMMIT_MEM [i] = new Tcounter_t [_param->_nb_context [i]]; 285 } 281 ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); 286 282 } 287 283 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r98 r100 178 178 179 179 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 180 for (uint32_t i=0; i<_param->_nb_front_end; i++) 181 { 182 delete [] reg_NB_INST_COMMIT_ALL [i]; 183 delete [] reg_NB_INST_COMMIT_MEM [i]; 184 } 185 delete [] reg_NB_INST_COMMIT_ALL; 186 delete [] reg_NB_INST_COMMIT_MEM; 187 188 delete [] reg_BANK_PTR; 189 190 delete [] _rob; 180 DELETE1(_rob ,_param->_nb_bank); 181 DELETE1(reg_BANK_PTR ,_param->_nb_bank); 182 DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); 183 DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); 184 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 191 185 } 192 186 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
r88 r100 30 30 uint32_t bank_nb_access [_param->_nb_bank]; 31 31 Tcontrol_t commit_ack [_param->_nb_inst_commit]; 32 32 33 // Initialisation 33 34 for (uint32_t i=0; i<_param->_nb_bank; i++) … … 38 39 } 39 40 40 // commit interface 41 // commit interface -> scan all entry (Out of Order) 41 42 for (uint32_t i=0; i<_param->_nb_inst_commit; i++) 42 43 { 43 44 commit_ack [i] = false; 44 45 45 // Test if have instruction46 // Test if have valid instruction 46 47 if (PORT_READ(in_COMMIT_VAL [i])) 47 48 { 48 Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; 49 uint32_t num_bank = packet >> _param->_shift_num_bank; 49 // packet_id number can 50 Tpacket_t packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; 51 uint32_t num_bank = packet_id >> _param->_shift_num_bank; 50 52 uint32_t num_bank_access = bank_nb_access [num_bank]; 51 53 … … 60 62 internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i; 61 63 62 Tpacket_t packet_id = packet& _param->_mask_size_bank;64 Tpacket_t num_packet = packet_id & _param->_mask_size_bank; 63 65 64 66 // find the good entry !!! … … 67 69 it!=_rob[num_bank].end(); 68 70 it++) 69 if ((*it)->ptr == packet_id)71 if ((*it)->ptr == num_packet) 70 72 { 71 73 entry = (*it); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
r88 r100 54 54 std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert 55 55 std::list<generic::priority::select_t>::iterator it=select_insert ->begin(); 56 56 57 // Scan all bank ... 57 58 for (uint32_t i=0; i<_param->_nb_bank; i++) 58 59 { … … 64 65 // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); 65 66 67 // Scan all insert interface to find a valid transaction 66 68 while (it!=select_insert ->end()) 67 69 { … … 87 89 if (not bank_full [num_bank]) 88 90 { 89 // find 91 // find !!! 90 92 insert_ack [num_rename_unit][num_inst_insert] = true; 91 93 … … 112 114 } 113 115 116 // Write output 114 117 for (uint32_t i=0; i<_param->_nb_rename_unit; i++) 115 118 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r88 r100 48 48 retire_val [i][j] = false; 49 49 } 50 51 50 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 52 51 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 53 spr_write_val [i][j] = 0; 54 52 { 53 spr_write_val [i][j] = 0; 54 spr_write_sr_f_val [i][j] = 0; 55 spr_write_sr_cy_val [i][j] = 0; 56 spr_write_sr_ov_val [i][j] = 0; 57 58 } 55 59 // Scan Top of each bank 56 60 for (uint32_t i=0; i<_param->_nb_bank; i++) … … 64 68 uint32_t x = entry->rename_unit_id; 65 69 uint32_t y = num_inst_retire [x]; 66 70 71 // test if : 72 // * can retire (all previous instruction is retired) 73 // * all structure is ok (not busy) 67 74 if (can_retire [x] and // in-order 68 75 (y < _param->_nb_inst_retire [x]) and … … 71 78 rob_state_t state = entry->state; 72 79 73 if ((state == ROB_END_OK ) or 74 (state == ROB_END_KO ) or 75 (state == ROB_END_MISS)// or 80 if ((state == ROB_END_OK ) or 81 (state == ROB_END_KO ) or 82 (state == ROB_END_BRANCH_MISS) or 83 (state == ROB_END_MISS )// or 76 84 // (state == ROB_END_EXCEPTION) 77 85 ) … … 85 93 bool spr_write_ack = true; 86 94 95 // Write in SR the good flag 87 96 if ((state == ROB_END_OK ) and write_re) 97 // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE 88 98 { 89 99 spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); … … 138 148 PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); 139 149 // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); 140 PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], entry->event_state);150 PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], reg_EVENT_STATE[front_end_id][context_id]); 141 151 PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); 142 152 PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r98 r100 28 28 // =================================================================== 29 29 { 30 // Store instruction comming Out Of Order in Load Store Unit. 31 // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB 32 30 33 Tcontrol_t val = false; 31 34 … … 35 38 rob_state_t state = entry->state; 36 39 40 // Test state 37 41 val = ((state == ROB_STORE_HEAD_OK) or 38 42 (state == ROB_STORE_HEAD_KO)); … … 40 44 if (val) 41 45 { 46 // Reexecute store 42 47 if (_param->_have_port_context_id) 43 48 PORT_WRITE(out_REEXECUTE_CONTEXT_ID [0], entry->context_id ); … … 62 67 // =================================================================== 63 68 { 69 // Branchement must be send at the prediction unit 64 70 uint32_t nb_scan_bank = 0; 65 71 72 // for each port, find a valid branchement. 66 73 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 67 74 { … … 72 79 nb_scan_bank ++; 73 80 81 // translate bank number 74 82 uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; 75 83 … … 124 132 } 125 133 } 126 127 // public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ;128 // public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ;129 // public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ;130 // public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ;131 // public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ;132 // public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ;133 // public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ;134 // public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ;135 // public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ;136 // public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ;137 // public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EEAR ;138 134 139 135 // =================================================================== -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
r98 r100 57 57 _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle")); 58 58 _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); 59 60 _stat->create_expr ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle"); 61 _stat->create_expr ("CPI", "/ 1 IPC" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction"); 59 62 } 60 63 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r98 r100 26 26 if (PORT_READ(in_NRESET) == 0) 27 27 { 28 // Clear all bank 28 29 for (uint32_t i=0; i<_param->_nb_bank; i++) 29 30 { … … 32 33 } 33 34 35 // Reset pointer 34 36 reg_NUM_BANK_HEAD = 0; 35 37 reg_NUM_BANK_TAIL = 0; 36 38 39 // Reset counter 37 40 for (uint32_t i=0; i<_param->_nb_front_end; i++) 38 41 for (uint32_t j=0; j<_param->_nb_context [i]; j++) … … 40 43 reg_NB_INST_COMMIT_ALL [i][j] = 0; 41 44 reg_NB_INST_COMMIT_MEM [i][j] = 0; 45 46 reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; 42 47 } 43 48 49 // Reset priority algorithm 44 50 _priority_insert->reset(); 45 51 } 46 52 else 47 53 { 48 // next priority54 // Compute next priority 49 55 _priority_insert->transition(); 56 57 // =================================================================== 58 // =====[ GARBAGE COLLECTOR ]========================================= 59 // =================================================================== 60 for (uint32_t i=0; i<_param->_nb_front_end; i++) 61 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 62 switch (reg_EVENT_STATE [i][j]) 63 { 64 case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break; 65 case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break; 66 // case EVENT_STATE_NO_EVENT : 67 // case EVENT_STATE_WAITEND : 68 default : break; 69 } 50 70 51 71 // =================================================================== … … 55 75 if (internal_BANK_INSERT_VAL [i]) 56 76 { 77 // get rename unit source and instruction. 57 78 uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; 58 79 uint32_t y = internal_BANK_INSERT_NUM_INST [i]; … … 67 88 #endif 68 89 90 // get information 69 91 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; 70 92 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; 71 93 Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); 72 94 Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); 95 bool is_store = is_operation_memory_store(operation); 96 73 97 Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); 74 98 … … 78 102 log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); 79 103 log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); 80 104 105 // Create new entry. 81 106 entry_t * entry = new entry_t; 82 107 … … 92 117 entry->exception = exception; 93 118 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); 94 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_ operation_memory_store(operation));95 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_ operation_memory_store(operation));119 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store); 120 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store); 96 121 entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); 97 122 entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; … … 114 139 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 115 140 141 // Test if exception : 142 // * yes : no execute instruction, wait ROB Head 143 // * no : test type 144 // * BRANCH : l.j -> branch is ended 145 // other -> wait the execution end of branchment 146 // * MEMORY : store -> wait store is at head of ROB 147 // other -> wait end of instruction 148 // * OTHER 116 149 if (exception == EXCEPTION_NONE) 117 150 { … … 124 157 { 125 158 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} 126 case TYPE_MEMORY : {entry->state= ROB_STORE_WAIT_HEAD_OK; break;}159 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 127 160 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 128 161 } … … 130 163 else 131 164 { 165 // Have an exception : wait head of ROB 166 132 167 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 133 168 … … 135 170 } 136 171 172 // Push in rob 137 173 _rob[i].push_back(entry); 138 174 139 // Update nb_inst175 // Update counter and pointer 140 176 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; 141 177 if (type == TYPE_MEMORY) … … 160 196 if (internal_BANK_COMMIT_VAL [i][j]) 161 197 { 198 // An instruction is executed. Change state of this instruction 199 162 200 uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; 163 201 … … 171 209 #endif 172 210 173 // Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0;174 175 211 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); 176 // log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0);177 // log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id);178 179 // test pandex with ptr_write.180 // Tpacket_t index = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id);181 212 182 213 // find the good entry !!! 183 entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];184 185 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);186 //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);187 Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);188 189 rob_state_t state = entry->state;190 Tcontext_t front_end_id = entry->front_end_id;191 Tcontext_t context_id = entry->context_id;192 193 // change state 214 entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; 215 216 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); 217 //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); 218 Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); 219 220 rob_state_t state = entry->state; 221 Tcontext_t front_end_id = entry->front_end_id; 222 Tcontext_t context_id = entry->context_id; 223 224 // change state : test exception_use 194 225 // * test if exception : exception and mask 195 226 196 bool have_exception = false; 197 227 bool have_exception = false; 228 bool have_miss_speculation = false; 229 198 230 if (exception != EXCEPTION_NONE) 199 switch (entry->exception_use) 200 { 201 case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} 202 case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 203 (exception == EXCEPTION_DATA_TLB ) or 204 (exception == EXCEPTION_DATA_PAGE) or 205 (exception == EXCEPTION_ALIGNMENT)); break;}; 206 case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 207 (exception == EXCEPTION_DATA_TLB ) or 208 (exception == EXCEPTION_DATA_PAGE)); break;}; 209 case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 210 case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 211 case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 212 case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 213 case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 214 case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 215 case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 216 case EXCEPTION_USE_TRAP : {have_exception = false; break;}; 217 case EXCEPTION_USE_NONE : {have_exception = false; break;}; 218 case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;}; 219 case EXCEPTION_USE_SYSCALL : {have_exception = false; break;}; 220 default : 221 { 222 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); 223 break; 224 } 225 } 226 227 if (not have_exception) 228 { 229 switch (state) 230 { 231 case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;} 232 case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;} 233 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 234 default : 235 { 236 throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); 237 break; 238 } 239 } 240 // can have an exception, but this instruction is not sensible a this exception 241 exception = EXCEPTION_NONE; 242 } 243 else 244 { 245 #ifdef DEBUG_TEST 246 if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) 247 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n")); 248 #endif 249 250 switch (state) 251 { 252 case ROB_OTHER_WAIT_END : 253 case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;} 254 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;} 255 default : 256 { 257 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n")); 258 break; 259 } 260 } 261 } 231 { 232 // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) 233 have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); 234 235 switch (entry->exception_use) 236 { 237 // Have overflow exception if bit overflow enable is set. 238 case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} 239 case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 240 (exception == EXCEPTION_DATA_TLB ) or 241 (exception == EXCEPTION_DATA_PAGE) or 242 (exception == EXCEPTION_ALIGNMENT)); break;}; 243 case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or 244 (exception == EXCEPTION_DATA_TLB ) or 245 (exception == EXCEPTION_DATA_PAGE)); break;}; 246 case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 247 case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 248 case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 249 case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 250 case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 251 case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 252 case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 253 // Case already manage (decod stage -> in insert in ROB) 254 case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; 255 case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; 256 case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; 257 case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; 258 default : 259 { 260 throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); 261 break; 262 } 263 } 264 } 265 266 switch (state) 267 { 268 // Branch ... 269 case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} 270 // Store KO 271 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 272 // Store OK, Load and other instruction 273 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;} 274 default : 275 { 276 throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); 277 break; 278 } 279 } 262 280 263 281 // update Re Order Buffer … … 287 305 288 306 entry_t * entry = _rob [i].front(); 307 rob_state_t state = entry->state; 308 289 309 #ifdef STATISTICS 290 310 if (usage_is_set(_usage,USE_STATISTICS)) 291 311 { 292 rob_state_t state = entry->state;293 294 312 if (state == ROB_END_OK) 295 313 (*_stat_nb_inst_retire_ok [x]) ++; … … 302 320 Tcontext_t context_id = entry->context_id ; 303 321 Ttype_t type = entry->type ; 322 323 if (state == ROB_END_BRANCH_MISS) 324 { 325 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 326 327 // !!!!!!!!!!! Compute address 328 } 304 329 305 330 // Update nb_inst … … 307 332 if (type == TYPE_MEMORY) 308 333 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 309 334 335 if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0) 336 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END; 337 310 338 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; 311 339 … … 350 378 #endif 351 379 352 entry->state = ROB_END_OK_SPECULATIVE; 380 entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE; 381 // entry->state = ROB_END_OK_SPECULATIVE; 353 382 } 354 383 355 384 // =================================================================== 385 // =====[ UPDATE ]==================================================== 386 // =================================================================== 387 { 388 // Not yet implemented 389 } 390 391 // =================================================================== 356 392 // =====[ EVENT ]===================================================== 357 393 // =================================================================== 394 { 395 // Not yet implemented 396 } 358 397 359 398 // =================================================================== … … 400 439 switch (state) 401 440 { 402 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 403 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 404 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 405 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 406 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 407 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 408 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 409 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 410 411 // don't change 412 case ROB_STORE_HEAD_KO : {break;} 413 case ROB_MISS_WAIT_END : {break;} 414 case ROB_END_MISS : {break;} 415 416 // can't have miss speculation 417 case ROB_STORE_HEAD_OK : 418 case ROB_END_OK : 419 case ROB_END_KO : 420 case ROB_END_EXCEPTION : 421 default : 441 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 442 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 443 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 444 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 445 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 446 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 447 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 448 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 449 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 450 451 // don't change 452 case ROB_STORE_HEAD_KO : {break;} 453 case ROB_MISS_WAIT_END : {break;} 454 case ROB_END_MISS : {break;} 455 456 // can't have miss speculation 457 case ROB_STORE_HEAD_OK : 458 case ROB_END_OK : 459 case ROB_END_KO : 460 case ROB_END_BRANCH_MISS : 461 case ROB_END_EXCEPTION : 462 default : 422 463 { 423 464 throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); … … 434 475 switch (state) 435 476 { 436 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 437 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 477 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 478 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 479 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 438 480 default : {break;} 439 481 } … … 519 561 (*it)->num_reg_re_phy_new ); 520 562 521 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s",563 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x", 522 564 (*it)->exception , 523 565 (*it)->exception_use , 524 566 (*it)->flags , 525 567 (*it)->no_sequence , 526 (*it)->data_commit , 527 toString((*it)->event_state).c_str() 568 (*it)->data_commit 528 569 ); 529 570 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
r88 r100 113 113 sensitive << (*(in_RENAME_CONTEXT_ID [i])); 114 114 115 sensitive << (*(in_RENAME_NUM_REG_RA_LOG [i])) 115 sensitive << (*(in_RENAME_VAL [i])) // Not necessary 116 << (*(in_RENAME_NUM_REG_RA_LOG [i])) 116 117 << (*(in_RENAME_NUM_REG_RB_LOG [i])) 117 118 << (*(in_RENAME_NUM_REG_RC_LOG [i])) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp
r97 r100 29 29 if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access 30 30 { 31 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i); 32 31 33 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 32 34 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 33 35 34 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 35 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 36 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 37 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 38 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 36 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 37 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 39 38 40 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][num_reg_ra_log]); 41 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][num_reg_rb_log]); 42 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][num_reg_rc_log]); 43 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][num_reg_rd_log]); 44 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][num_reg_re_log]); 45 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"yo6"); 39 Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; 40 Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; 41 Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; 42 Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; 43 Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; 44 45 Tgeneral_address_t num_reg_ra_phy = rat_gpr[front_end_id][context_id][num_reg_ra_log]; 46 Tgeneral_address_t num_reg_rb_phy = rat_gpr[front_end_id][context_id][num_reg_rb_log]; 47 Tspecial_address_t num_reg_rc_phy = rat_spr[front_end_id][context_id][num_reg_rc_log]; 48 Tgeneral_address_t num_reg_rd_phy_old= rat_gpr[front_end_id][context_id][num_reg_rd_log]; 49 Tspecial_address_t num_reg_re_phy_old= rat_spr[front_end_id][context_id][num_reg_re_log]; 50 51 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); 52 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); 53 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); 54 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); 55 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); 56 57 58 PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); 59 PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); 60 PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); 61 PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); 62 PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); 46 63 } 47 64 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
r98 r100 37 37 38 38 for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) 39 rat_gpr [i][j][k] = gpr++; 39 { 40 rat_gpr [i][j][k] = gpr++; 41 // rat_gpr_update_table[i][j][k] = 0; 42 } 40 43 for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) 41 rat_spr [i][j][k] = spr++; 44 { 45 rat_spr [i][j][k] = spr++; 46 // rat_spr_update_table[i][j][k] = 0; 47 } 42 48 } 43 49 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp
r98 r100 95 95 if (PORT_READ(in_SPR_COMMIT_VAL [i][j])) // out_SPR_COMMIT_ACK [i][j] 96 96 { 97 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_COMMIT [%d][%d]",i,j); 98 log_printf(TRACE,Special_Register_unit,FUNCTION," * F : %d, %d",PORT_READ(in_SPR_COMMIT_SR_F_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_F [i][j])); 99 log_printf(TRACE,Special_Register_unit,FUNCTION," * CY : %d, %d",PORT_READ(in_SPR_COMMIT_SR_CY_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_CY [i][j])); 100 log_printf(TRACE,Special_Register_unit,FUNCTION," * OV : %d, %d",PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_OV [i][j])); 101 102 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); 97 103 SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); 98 104 … … 105 111 if (PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j])) 106 112 sr->ov = PORT_READ(in_SPR_COMMIT_SR_OV [i][j]); 113 114 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (after) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); 115 107 116 } 108 117 109 118 if (PORT_READ(in_SPR_EVENT_VAL [i][j])) // out_SPR_EVENT_ACK [i][j] 110 119 { 120 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_EVENT [%d][%d]",i,j); 121 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); 122 111 123 SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); 112 124 sr->dsx = PORT_READ(in_SPR_EVENT_SR_DSX [i][j]); … … 117 129 if (PORT_READ(in_SPR_EVENT_SR_TO_ESR [i][j])) 118 130 _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_ESR ]->write(sr->read()); 131 132 log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (after) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); 119 133 } 120 134 }
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