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Changeset 69 for PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES
- Timestamp:
- Sep 18, 2013, 1:39:39 PM (11 years ago)
- Location:
- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03
- Files:
-
- 10 edited
-
CoreTypes.vhd (modified) (3 diffs)
-
GENERIC_16_16.gise (modified) (1 diff)
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GENERIC_16_16.xise (modified) (4 diffs)
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OUTPUT_PORT_MODULE.vhd (modified) (3 diffs)
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iseconfig/GENERIC_16_16.projectmgr (modified) (8 diffs)
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iseconfig/testbench.xreport (modified) (1 diff)
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proto_send.vhd (modified) (1 diff)
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test_xbar_8x8.vhd (modified) (1 diff)
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test_xbar_8x8_beh.prj (modified) (1 diff)
-
testbench_summary.html (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd
r65 r69 23 23 CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556; 24 24 CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566; 25 CONSTANT CORE_Rank2port_BASE :NATURAL:=32; 25 CONSTANT CORE_SPAWN_ADR : natural := CORE_BASE_ADR+576; 26 CONSTANT CORE_Rank2port_BASE :NATURAL:=52; 26 27 CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base; 27 28 CONSTANT WIN0_ADR :natural :=4; … … 53 54 IsMain : std_logic; -- indique si la librairie est principal 54 55 Rank : natural range 0 to 16; --donne le rang du processus courant 56 Spawned: std_logic; --indique que ce module a été activé par la bibliothèque 55 57 end record; 56 58 … … 284 286 285 287 function image(L: std_logic) return String is 286 variable bit_image: String(1 to 1) := std_logic'image(L);288 variable bit_image: String(1 to 3) := std_logic'image(L); 287 289 begin 288 290 return(bit_image(1 to 1)); -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.gise
r22 r69 29 29 </files> 30 30 31 <transforms xmlns="http://www.xilinx.com/XMLSchema"/> 31 <transforms xmlns="http://www.xilinx.com/XMLSchema"> 32 <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1370435746"> 33 <status xil_pn:value="SuccessfullyRun"/> 34 <status xil_pn:value="ReadyToRun"/> 35 </transform> 36 <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1370435746"> 37 <status xil_pn:value="SuccessfullyRun"/> 38 <status xil_pn:value="ReadyToRun"/> 39 <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/> 40 <outfile xil_pn:name="Arbiter.vhd"/> 41 <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/> 42 <outfile xil_pn:name="CoreTypes.vhd"/> 43 <outfile xil_pn:name="Crossbar.vhd"/> 44 <outfile xil_pn:name="Crossbit.vhd"/> 45 <outfile xil_pn:name="FIFO_256_FWFT.vhd"/> 46 <outfile xil_pn:name="FIFO_DP.vhd"/> 47 <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/> 48 <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/> 49 <outfile xil_pn:name="Proto_receiv.vhd"/> 50 <outfile xil_pn:name="RAM_256.vhd"/> 51 <outfile xil_pn:name="SCHEDULER10_10.VHD"/> 52 <outfile xil_pn:name="SCHEDULER11_11.VHD"/> 53 <outfile xil_pn:name="SCHEDULER12_12.VHD"/> 54 <outfile xil_pn:name="SCHEDULER13_13.VHD"/> 55 <outfile xil_pn:name="SCHEDULER14_14.VHD"/> 56 <outfile xil_pn:name="SCHEDULER15_15.VHD"/> 57 <outfile xil_pn:name="SCHEDULER16_16.VHD"/> 58 <outfile xil_pn:name="SCHEDULER2_2.VHD"/> 59 <outfile xil_pn:name="SCHEDULER3_3.VHD"/> 60 <outfile xil_pn:name="SCHEDULER4_4.VHD"/> 61 <outfile xil_pn:name="SCHEDULER5_5.VHD"/> 62 <outfile xil_pn:name="SCHEDULER6_6.VHD"/> 63 <outfile xil_pn:name="SCHEDULER7_7.VHD"/> 64 <outfile xil_pn:name="SCHEDULER8_8.VHD"/> 65 <outfile xil_pn:name="SCHEDULER9_9.VHD"/> 66 <outfile xil_pn:name="SWITCH_GEN.vhd"/> 67 <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/> 68 <outfile xil_pn:name="Scheduler.vhd"/> 69 <outfile xil_pn:name="conv.vhd"/> 70 <outfile xil_pn:name="proto_send.vhd"/> 71 <outfile xil_pn:name="stimuli1.vhd"/> 72 <outfile xil_pn:name="test_xbar_8x8.vhd"/> 73 </transform> 74 <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1086089259624485161" xil_pn:start_ts="1370435946"> 75 <status xil_pn:value="SuccessfullyRun"/> 76 <status xil_pn:value="ReadyToRun"/> 77 </transform> 78 <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-661505819731779733" xil_pn:start_ts="1370435946"> 79 <status xil_pn:value="SuccessfullyRun"/> 80 <status xil_pn:value="ReadyToRun"/> 81 </transform> 82 <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="1089920306747347169" xil_pn:start_ts="1370435746"> 83 <status xil_pn:value="SuccessfullyRun"/> 84 <status xil_pn:value="ReadyToRun"/> 85 </transform> 86 <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1370435746"> 87 <status xil_pn:value="SuccessfullyRun"/> 88 <status xil_pn:value="ReadyToRun"/> 89 <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/> 90 <outfile xil_pn:name="Arbiter.vhd"/> 91 <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/> 92 <outfile xil_pn:name="CoreTypes.vhd"/> 93 <outfile xil_pn:name="Crossbar.vhd"/> 94 <outfile xil_pn:name="Crossbit.vhd"/> 95 <outfile xil_pn:name="FIFO_256_FWFT.vhd"/> 96 <outfile xil_pn:name="FIFO_DP.vhd"/> 97 <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/> 98 <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/> 99 <outfile xil_pn:name="Proto_receiv.vhd"/> 100 <outfile xil_pn:name="RAM_256.vhd"/> 101 <outfile xil_pn:name="SCHEDULER10_10.VHD"/> 102 <outfile xil_pn:name="SCHEDULER11_11.VHD"/> 103 <outfile xil_pn:name="SCHEDULER12_12.VHD"/> 104 <outfile xil_pn:name="SCHEDULER13_13.VHD"/> 105 <outfile xil_pn:name="SCHEDULER14_14.VHD"/> 106 <outfile xil_pn:name="SCHEDULER15_15.VHD"/> 107 <outfile xil_pn:name="SCHEDULER16_16.VHD"/> 108 <outfile xil_pn:name="SCHEDULER2_2.VHD"/> 109 <outfile xil_pn:name="SCHEDULER3_3.VHD"/> 110 <outfile xil_pn:name="SCHEDULER4_4.VHD"/> 111 <outfile xil_pn:name="SCHEDULER5_5.VHD"/> 112 <outfile xil_pn:name="SCHEDULER6_6.VHD"/> 113 <outfile xil_pn:name="SCHEDULER7_7.VHD"/> 114 <outfile xil_pn:name="SCHEDULER8_8.VHD"/> 115 <outfile xil_pn:name="SCHEDULER9_9.VHD"/> 116 <outfile xil_pn:name="SWITCH_GEN.vhd"/> 117 <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/> 118 <outfile xil_pn:name="Scheduler.vhd"/> 119 <outfile xil_pn:name="conv.vhd"/> 120 <outfile xil_pn:name="proto_send.vhd"/> 121 <outfile xil_pn:name="stimuli1.vhd"/> 122 <outfile xil_pn:name="test_xbar_8x8.vhd"/> 123 </transform> 124 <transform xil_pn:end_ts="1370435977" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4512714324515926764" xil_pn:start_ts="1370435946"> 125 <status xil_pn:value="FailedRun"/> 126 <status xil_pn:value="ReadyToRun"/> 127 </transform> 128 </transforms> 32 129 33 130 </generated_project> -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.xise
r22 r69 364 364 <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> 365 365 <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> 366 <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> 366 367 <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> 367 368 <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> … … 400 401 <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> 401 402 <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> 402 <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/test bench" xil_pn:valueState="non-default"/>403 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test bench" xil_pn:valueState="non-default"/>403 <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/test_xbar_8x8" xil_pn:valueState="non-default"/> 404 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/> 404 405 <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/> 405 406 <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> … … 421 422 <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> 422 423 <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> 423 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test bench" xil_pn:valueState="default"/>424 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/> 424 425 <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/> 425 426 <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> … … 482 483 <!-- The following properties are for internal use only. These should not be modified.--> 483 484 <!-- --> 484 <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|test bench|behavior" xil_pn:valueState="non-default"/>485 <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|test_xbar_8x8|behavior" xil_pn:valueState="non-default"/> 485 486 <property xil_pn:name="PROP_DesignName" xil_pn:value="GENERIC_16_16" xil_pn:valueState="non-default"/> 486 487 <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd
r22 r69 15 15 -- Dependencies: 16 16 -- 17 -- Revision: 17 -- Revision: 07-08-2013 18 18 -- Revision 0.01 - File Created 19 -- Additional Comments: 19 -- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis 20 -- longtemps 20 21 -- 21 22 ---------------------------------------------------------------------------------- 22 23 library IEEE; 23 24 use IEEE.STD_LOGIC_1164.ALL; 24 use IEEE.STD_LOGIC_ARITH.ALL; 25 use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 --use IEEE.STD_LOGIC_ARITH.ALL; 26 --use IEEE.STD_LOGIC_UNSIGNED.ALL; 27 USE ieee.numeric_std.ALL; 26 28 Library NocLib; 27 29 use NocLib.CoreTypes.all; … … 51 53 srst: IN std_logic; 52 54 wr_en: IN std_logic; 53 dout: OUTstd_logic_VECTOR(Word-1 downto 0);55 dout: out std_logic_VECTOR(Word-1 downto 0); 54 56 empty: OUT std_logic; 55 57 full: OUT std_logic); 56 58 end component; 57 59 --definition du type etat pour les fsm 58 signal empty_signal : std_logic; 60 type typ_outfsm is (Idle,waiting,dropping,reading); 61 type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end); 62 63 signal EtRec : typ_receiv; 64 signal Et_out_fsm : typ_outfsm; 65 signal fifo_empty : std_logic; 66 signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes 67 signal tlimit : natural:=0; --permet de compter les impulsions de temps 68 signal n : natural:=0; --utiliser pour la mae du tampon de sortie 69 signal rcv_start : std_logic; --début de la réception 70 signal rcv_ack : std_logic; -- acquittement de la réception 71 signal rcv_comp : std_logic; -- fin de la réception 72 signal spop,pop,rd_en,dat_avail : std_logic:='0'; 73 signal mem,fifo_out : std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel 59 74 begin 60 75 -- instantiation du FIFO_64 … … 63 78 clk => clk, 64 79 din => data_in, 65 rd_en => rd_ out_en,80 rd_en => rd_en, 66 81 srst => reset, 67 82 wr_en => wr_en, 68 dout => data_out,69 empty => empty_signal,83 dout => fifo_out, 84 empty => fifo_empty, 70 85 full => fifo_full); 71 86 72 data_avalaible <= not empty_signal; 87 88 outport_proc : process(clk,reset,fifo_empty) 89 begin 90 if rising_edge(clk) then 91 if reset='1' then 92 n<=0; 93 Et_out_fsm<=Idle; 94 else 95 case(Et_out_fsm) is 96 97 when Idle => --idle 98 if fifo_empty = '0' then 99 Et_Out_fsm<=waiting; 100 end if; 101 tlimit<=0; 102 sw<='0'; 103 when reading => 104 if rd_out_en='0' then 105 Et_out_fsm<=Idle; 106 end if; 107 sw<='0'; 108 when waiting => --counting 109 if rd_out_en='1' then 110 Et_out_fsm<=reading; 111 elsif tlimit=350 then 112 Et_out_fsm<=dropping; 113 tlimit<=0; 114 else 115 tlimit<=tlimit+1; 116 end if; 117 sw<='0'; 118 when dropping => --dropping packet 119 if n=0 then 120 rcv_start<='1'; 121 n<=1; 122 sw<='1'; 123 elsif n=1 then 124 if rcv_comp='1' then 125 rcv_ack<='1'; 126 rcv_start<='0'; 127 n<=2; 128 end if; 129 sw<='1'; 130 elsif n=2 then 131 sw<='0'; 132 Et_out_fsm<=Idle; 133 n<=0; 134 end if; 135 136 end case; 137 end if; 138 end if; 139 end process outport_proc; 140 data_out<=fifo_out; 141 mux_proc : process (sw,rd_out_en,pop,fifo_empty) 142 begin 143 if sw='1' then --mode drop 144 rd_en<=pop; 145 data_avalaible <='0'; --plus de données dans le tampon ! 146 else 147 rd_en<=rd_out_en; 148 data_avalaible <= not fifo_empty; 149 end if; 150 end process mux_proc; 151 proc_receiv : process (clk,reset) 152 variable dlen,i: natural range 0 to 255 :=0; 153 154 begin 155 if reset='1' then 156 etrec<=r_wait; 157 158 else 159 if rising_edge(clk) then -- le process s'exécute sur chaque front 160 -- montant de l'horloge 161 case etrec is 162 when r_wait => 163 164 i:=0; 165 if fifo_empty='0' and rcv_start='1' then 166 167 etrec<=r_head; 168 mem<=fifo_out; 169 170 end if; 171 when r_head => 172 mem<=fifo_out; --l'en-tête 173 174 etrec<=r_len; 175 when r_len => 176 dlen:=to_integer(unsigned(fifo_out)); 177 mem<=fifo_out; -- la longueur 178 179 if dlen>2 then 180 etrec<=r_data; 181 else 182 etrec<=r_end; 183 end if; 184 i:=1; 185 186 when r_data => 187 if fifo_empty='0' then 188 if i<dlen-2 then 189 i:=i+1; 190 mem<=fifo_out; 191 192 193 else 194 etrec<=r_pulse; 195 196 mem<=fifo_out; 197 end if; 198 -- time out à prévoir ici 199 end if; 200 when r_pulse => 201 etrec<=r_end; 202 203 when r_end => 204 if rcv_ack='1' then 205 etrec<=r_wait; 206 end if; 207 208 when others => 209 210 211 etrec<=r_wait; 212 end case; 213 end if; 214 end if; 215 end process; 216 217 pop<=spop; 218 219 rec_value : process (etrec) 220 begin 221 case etrec is 222 when r_wait => 223 spop<='0'; 224 rcv_comp<='0'; 225 when r_head => 226 227 spop<='1'; 228 rcv_comp<='0'; 229 230 when r_len => 231 spop<='1'; 232 when r_data => 233 spop<='1'; 234 when r_pulse => 235 spop<='0'; 236 rcv_comp<='1'; 237 when r_end => 238 spop<='0'; 239 rcv_comp<='1'; 240 when others => 241 spop<='0'; 242 rcv_comp<='0'; 243 end case; 244 end process; 73 245 74 246 end Behavioral_description; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/GENERIC_16_16.projectmgr
r22 r69 145 145 <SelectedItem>Scheduler11_11 - Scheduler - Behavioral (C:/Core MPI/SWITCH_GENERIC_16_16/Scheduler.vhd)</SelectedItem> 146 146 </SelectedItems> 147 <ScrollbarPosition orientation="vertical" >2 93</ScrollbarPosition>147 <ScrollbarPosition orientation="vertical" >283</ScrollbarPosition> 148 148 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> 149 149 <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000044e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000044e0000000100000000000000000000000100000000</ViewHeaderState> … … 166 166 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> 167 167 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> 168 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001 0d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000</ViewHeaderState>168 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState> 169 169 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> 170 170 <CurrentItem></CurrentItem> … … 276 276 <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode> 277 277 <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode> 278 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>279 278 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> 280 279 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode> … … 316 315 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode> 317 316 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode> 317 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral</ClosedNode> 318 318 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode> 319 319 <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode> … … 452 452 <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode> 453 453 <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode> 454 <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd </ClosedNode>454 <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral</ClosedNode> 455 455 <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode> 456 456 <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode> … … 518 518 </ClosedNodes> 519 519 <SelectedItems> 520 <SelectedItem>test bench - behavior (C:/Core MPI/CORE_MPI/sim_fifo.vhd)</SelectedItem>521 </SelectedItems> 522 <ScrollbarPosition orientation="vertical" >3 </ScrollbarPosition>520 <SelectedItem>test_xbar_8x8 - behavior (C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd)</SelectedItem> 521 </SelectedItems> 522 <ScrollbarPosition orientation="vertical" >306</ScrollbarPosition> 523 523 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> 524 524 <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014d000000020000000000000000000000000000000064ffffffff0000008100000000000000020000014d0000000100000000000000000000000100000000</ViewHeaderState> 525 525 <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> 526 <CurrentItem>test bench - behavior (C:/Core MPI/CORE_MPI/sim_fifo.vhd)</CurrentItem>526 <CurrentItem>test_xbar_8x8 - behavior (C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd)</CurrentItem> 527 527 </ItemView> 528 528 <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > … … 549 549 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> 550 550 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> 551 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001 0d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000</ViewHeaderState>551 <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState> 552 552 <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> 553 553 <CurrentItem>Simulate Behavioral Model</CurrentItem> … … 568 568 </ItemView> 569 569 <SourceProcessView>000000ff0000000000000002000000eb0000009c01000000050100000002</SourceProcessView> 570 <CurrentView> Implementation</CurrentView>570 <CurrentView>Behavioral Simulation</CurrentView> 571 571 <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" > 572 572 <ClosedNodes> -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/testbench.xreport
r22 r69 2 2 <report-views version="2.0" > 3 3 <header> 4 <DateModified>201 2-11-29T18:08:12</DateModified>4 <DateModified>2013-06-15T12:57:53</DateModified> 5 5 <ModuleName>testbench</ModuleName> 6 6 <SummaryTimeStamp>Unknown</SummaryTimeStamp> -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
r65 r69 21 21 use IEEE.STD_LOGIC_1164.ALL; 22 22 USE ieee.numeric_std.ALL; 23 use work.CoreTypes.all;23 use CoreTypes.all; 24 24 -- Uncomment the following library declaration if using 25 25 -- arithmetic functions with Signed or Unsigned values -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8.vhd
r22 r69 431 431 origport:=to_integer(unsigned(portout(destport)(3 downto 0))); 432 432 rdata_out_en(destport)<='1'; 433 if ptype=5 then 434 etrec<=r_Dlen; 433 if ptype=5 then -- 434 etrec<=r_Dlen;--identification de la signature d'en tête valide 435 435 else 436 436 etrec<=r_wait; -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8_beh.prj
r22 r69 1 1 vhdl work "CoreTypes.vhd" 2 vhdl work "RAM_256.vhd"3 2 vhdl work "Arbiter.vhd" 4 3 vhdl work "SCHEDULER9_9.VHD" -
PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/testbench_summary.html
r22 r69 8 8 <TD>GENERIC_16_16.xise</TD> 9 9 <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> 10 <TD> No Errors </TD> 10 11 </TR> 11 12 <TR ALIGN=LEFT> … … 75 76 76 77 77 <br><center><b>Date Generated:</b> 11/29/2012 - 18:08:12</center>78 <br><center><b>Date Generated:</b> 06/15/2013 - 12:57:53</center> 78 79 </BODY></HTML>
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