Changeset 76 for PROJECT_CORE_MPI


Ignore:
Timestamp:
Jan 17, 2014, 5:04:00 PM (10 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00
Files:
6 added
11 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd

    r74 r76  
    144144                                --Dcount<=0;
    145145                                if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
    146                                                 RunState<=Fillmem;
     146                                                RunState<=InitApp;
    147147                                 end if;
    148148                                 --Ram_busy<='0';
    … …  
    185185                                                 
    186186                                                 if bfill=4 then
    187                                                   RunState<=InitApp;
     187                                                  RunState<=WinCreate;
    188188                                                 else
    189189                                                        RunState<=nextfill;
    … …  
    212212                when InitApp =>
    213213                                --code pour Init
    214                                 dlen:=15;
     214                                dlen:=1;
    215215                                if ct=0 then
    216216                                -- synthesis translate_off
    217                                 write (l,string'("Dlen; ;INIT1 " &  integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
     217                                write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " &  integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
    218218                               
    219219                                report l.all;
    … …  
    251251                       
    252252                        if ct=0 then
    253                                 RunState<=WinCreate;
     253                                RunState<=FillMem;
    254254                                -- synthesis translate_off
    255                                 write (l,string'("Dlen; ;Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     255                                write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    256256                                report l.all;
    257257            writeline (f, l) ;
    … …  
    288288                        if ct=0 then
    289289                                -- synthesis translate_off
    290                                 write (l,string'("Dlen; ;WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
     290                                write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
    291291                                report l.all;
    292292            writeline (f, l) ; 
    … …  
    303303                                  end if;
    304304                                -- synthesis translate_off
    305                                 write (l,string'("Dlen; ;WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     305                                write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    306306                                report l.all;
    307307            writeline (f, l) ;
    … …  
    312312                        if ct=0 then
    313313                                -- synthesis translate_off
    314                                 write (l,string'("Dlen; ;WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
     314                                write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
    315315                                report l.all;
    316316            writeline (f, l) ; 
    … …  
    326326                                RunState<=PutData;
    327327                                -- synthesis translate_off
    328                                 write (l,string'("Dlen; ;WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     328                                write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    329329                                report l.all;
    330330            writeline (f, l) ;

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd

    r74 r76  
    144144                                --Dcount<=0;
    145145                                if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
    146                                                 RunState<=Fillmem;
     146                                                RunState<=InitApp;
    147147                                 end if;
    148148                                 --Ram_busy<='0';
    … …  
    185185                                                 
    186186                                                 if bfill=4 then
    187                                                   RunState<=InitApp;
     187                                                  RunState<=WinCreate;
    188188                                                 else
    189189                                                        RunState<=nextfill;
    … …  
    212212                when InitApp =>
    213213                                --code pour Init
    214                                 dlen:=15;
     214                                dlen:=10;
    215215                                if ct=0 then
    216216                                -- synthesis translate_off
    … …  
    251251                       
    252252                        if ct=0 then
    253                                 RunState<=WinCreate;
     253                                RunState<=Fillmem;
    254254                                -- synthesis translate_off
    255                                 write (l,string'("Dlen; ;Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     255                                write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    256256                                report l.all;
    257257            writeline (f, l) ;
    … …  
    288288                        if ct=0 then
    289289                                -- synthesis translate_off
    290                                 write (l,string'("Dlen; ;WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
     290                                write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
    291291                                report l.all;
    292292            writeline (f, l) ; 
    … …  
    299299                                RunState<=WinStart;
    300300                                -- synthesis translate_off
    301                                 write (l,string'("Dlen; ;WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     301                                write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    302302                                report l.all;
    303303            writeline (f, l) ;
    … …  
    308308                        if ct=0 then
    309309                                -- synthesis translate_off
    310                                 write (l,string'("Dlen; ;WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
     310                                write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
    311311                                report l.all;
    312312            writeline (f, l) ; 
    … …  
    322322                                RunState<=PutData;
    323323                                -- synthesis translate_off
    324                                 write (l,string'("Dlen; ;WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
     324                                write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
    325325                                report l.all;
    326326            writeline (f, l) ;

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise

    r74 r76  
    103103    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="DMA_ARBITER_xst.xrpt"/>
    104104    <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/>
     105    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="Ex5_FSM.fdo"/>
    105106    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FIFO_256_FWFT_isim_beh.exe"/>
    106107    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Hold_FSM_isim_beh.exe"/>
     108    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="IP_Timer.cmd_log"/>
     109    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="IP_Timer.fdo"/>
     110    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="IP_Timer.lso"/>
     111    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="IP_Timer.ngc"/>
     112    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="IP_Timer.ngr"/>
     113    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="IP_Timer.prj"/>
     114    <file xil_pn:fileType="FILE_SPL" xil_pn:name="IP_Timer.spl"/>
     115    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="IP_Timer.stx"/>
     116    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="IP_Timer.sym" xil_pn:origination="imported"/>
     117    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="IP_Timer.syr"/>
     118    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="IP_Timer.xst"/>
     119    <file xil_pn:fileType="FILE_HTML" xil_pn:name="IP_Timer_envsettings.html"/>
     120    <file xil_pn:fileType="FILE_HTML" xil_pn:name="IP_Timer_summary.html"/>
     121    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="IP_Timer_xst.xrpt"/>
    107122    <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/>
    108123    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_CORE_SCHEDULER.bld"/>
    … …  
    165180    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_map.ncd" xil_pn:subbranch="Map"/>
    166181    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/>
     182    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_map.xrpt"/>
    167183    <file xil_pn:fileType="FILE_LOG" xil_pn:name="MultiMPITest_map_fpga_editor.log"/>
     184    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_ngdbuild.xrpt"/>
    168185    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/>
    169186    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/>
    … …  
    194211    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="PE.unroutes" xil_pn:subbranch="Par"/>
    195212    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="PE.xst"/>
     213    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="PE_beh.prj"/>
    196214    <file xil_pn:fileType="FILE_HTML" xil_pn:name="PE_envsettings.html"/>
    197215    <file xil_pn:fileType="FILE_NCD" xil_pn:name="PE_guide.ncd" xil_pn:origination="imported"/>
    … …  
    306324
    307325  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    308     <transform xil_pn:end_ts="1389570072" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1389570072">
    309       <status xil_pn:value="SuccessfullyRun"/>
    310       <status xil_pn:value="ReadyToRun"/>
    311     </transform>
    312     <transform xil_pn:end_ts="1389743130" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1389743129">
     326    <transform xil_pn:end_ts="1389780673" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1389780673">
     327      <status xil_pn:value="SuccessfullyRun"/>
     328      <status xil_pn:value="ReadyToRun"/>
     329    </transform>
     330    <transform xil_pn:end_ts="1389973516" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1389973515">
    313331      <status xil_pn:value="SuccessfullyRun"/>
    314332      <status xil_pn:value="ReadyToRun"/>
    … …  
    355373      <outfile xil_pn:name="FIfo_mem.vhd"/>
    356374      <outfile xil_pn:name="FIfo_proc.vhd"/>
     375      <outfile xil_pn:name="HCL_Arch_conf.vhd"/>
     376      <outfile xil_pn:name="HT_4.vhd"/>
    357377      <outfile xil_pn:name="HT_process.vhd"/>
    358378      <outfile xil_pn:name="Hold_FSM.vhd"/>
     379      <outfile xil_pn:name="IP_Timer.vhd"/>
    359380      <outfile xil_pn:name="MPICORETEST.vhd"/>
    360381      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
    … …  
    376397      <outfile xil_pn:name="test_DMA.vhd"/>
    377398    </transform>
    378     <transform xil_pn:end_ts="1389570072" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1389570072">
    379       <status xil_pn:value="SuccessfullyRun"/>
    380       <status xil_pn:value="ReadyToRun"/>
    381     </transform>
    382     <transform xil_pn:end_ts="1389570074" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1389570072">
    383       <status xil_pn:value="SuccessfullyRun"/>
    384       <status xil_pn:value="ReadyToRun"/>
    385     </transform>
    386     <transform xil_pn:end_ts="1389726825" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7827306417472095804" xil_pn:start_ts="1389726825">
    387       <status xil_pn:value="SuccessfullyRun"/>
    388       <status xil_pn:value="ReadyToRun"/>
    389     </transform>
    390     <transform xil_pn:end_ts="1389743130" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1389743130">
     399    <transform xil_pn:end_ts="1389973586" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1389973586">
     400      <status xil_pn:value="SuccessfullyRun"/>
     401      <status xil_pn:value="ReadyToRun"/>
     402    </transform>
     403    <transform xil_pn:end_ts="1389973589" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1389973586">
     404      <status xil_pn:value="SuccessfullyRun"/>
     405      <status xil_pn:value="ReadyToRun"/>
     406    </transform>
     407    <transform xil_pn:end_ts="1389797219" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1389797219">
     408      <status xil_pn:value="SuccessfullyRun"/>
     409      <status xil_pn:value="ReadyToRun"/>
     410    </transform>
     411    <transform xil_pn:end_ts="1389973521" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1389973521">
    391412      <status xil_pn:value="SuccessfullyRun"/>
    392413      <status xil_pn:value="ReadyToRun"/>
    … …  
    433454      <outfile xil_pn:name="FIfo_mem.vhd"/>
    434455      <outfile xil_pn:name="FIfo_proc.vhd"/>
     456      <outfile xil_pn:name="HCL_Arch_conf.vhd"/>
     457      <outfile xil_pn:name="HT_4.vhd"/>
    435458      <outfile xil_pn:name="HT_process.vhd"/>
    436459      <outfile xil_pn:name="Hold_FSM.vhd"/>
     460      <outfile xil_pn:name="IP_Timer.vhd"/>
    437461      <outfile xil_pn:name="MPICORETEST.vhd"/>
    438462      <outfile xil_pn:name="MPI_CORE_SCHEDULER.vhd"/>
    … …  
    454478      <outfile xil_pn:name="test_DMA.vhd"/>
    455479    </transform>
    456     <transform xil_pn:end_ts="1389743164" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1389743130">
     480    <transform xil_pn:end_ts="1389973619" xil_pn:in_ck="-5178871848763058326" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1389973589">
    457481      <status xil_pn:value="SuccessfullyRun"/>
    458482      <status xil_pn:value="ReadyToRun"/>
    … …  
    461485      <outfile xil_pn:name="work"/>
    462486    </transform>
    463     <transform xil_pn:end_ts="1389558632" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1389558632">
    464       <status xil_pn:value="SuccessfullyRun"/>
    465       <status xil_pn:value="ReadyToRun"/>
    466     </transform>
    467     <transform xil_pn:end_ts="1389723757" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4817802592528555221" xil_pn:start_ts="1389723754">
    468       <status xil_pn:value="SuccessfullyRun"/>
    469       <status xil_pn:value="ReadyToRun"/>
    470     </transform>
    471     <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7827306417472095804" xil_pn:start_ts="1389723757">
    472       <status xil_pn:value="SuccessfullyRun"/>
    473       <status xil_pn:value="ReadyToRun"/>
    474     </transform>
    475     <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1389723757">
    476       <status xil_pn:value="SuccessfullyRun"/>
    477       <status xil_pn:value="ReadyToRun"/>
    478     </transform>
    479     <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1893960479894904659" xil_pn:start_ts="1389723757">
    480       <status xil_pn:value="SuccessfullyRun"/>
    481       <status xil_pn:value="ReadyToRun"/>
    482     </transform>
    483     <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1389723757">
    484       <status xil_pn:value="SuccessfullyRun"/>
    485       <status xil_pn:value="ReadyToRun"/>
    486     </transform>
    487     <transform xil_pn:end_ts="1389723757" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2122804370720789306" xil_pn:start_ts="1389723757">
    488       <status xil_pn:value="SuccessfullyRun"/>
    489       <status xil_pn:value="ReadyToRun"/>
    490     </transform>
    491     <transform xil_pn:end_ts="1389725470" xil_pn:in_ck="-8697612743778259046" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-7202030164265802586" xil_pn:start_ts="1389725338">
    492       <status xil_pn:value="SuccessfullyRun"/>
    493       <status xil_pn:value="WarningsGenerated"/>
    494       <status xil_pn:value="ReadyToRun"/>
    495       <status xil_pn:value="OutOfDateForInputs"/>
    496       <status xil_pn:value="InputChanged"/>
    497       <outfile xil_pn:name="CORE_MPI.lso"/>
    498       <outfile xil_pn:name="CORE_MPI.ngc"/>
    499       <outfile xil_pn:name="CORE_MPI.ngr"/>
    500       <outfile xil_pn:name="CORE_MPI.prj"/>
    501       <outfile xil_pn:name="CORE_MPI.stx"/>
    502       <outfile xil_pn:name="CORE_MPI.syr"/>
    503       <outfile xil_pn:name="CORE_MPI.xst"/>
    504       <outfile xil_pn:name="CORE_MPI_xst.xrpt"/>
    505       <outfile xil_pn:name="DMA_ARBITER.ngr"/>
    506       <outfile xil_pn:name="MPI_CORE_SCHEDULER.ngr"/>
    507       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
    508       <outfile xil_pn:name="load_instr.ngr"/>
    509       <outfile xil_pn:name="webtalk_pn.xml"/>
    510       <outfile xil_pn:name="xst"/>
    511     </transform>
    512     <transform xil_pn:end_ts="1389723997" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3683379310506444734" xil_pn:start_ts="1389723997">
    513       <status xil_pn:value="SuccessfullyRun"/>
    514       <status xil_pn:value="ReadyToRun"/>
    515     </transform>
    516     <transform xil_pn:end_ts="1389724003" xil_pn:in_ck="-1005953262871376632" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3081276958392942983" xil_pn:start_ts="1389723997">
    517       <status xil_pn:value="SuccessfullyRun"/>
    518       <status xil_pn:value="ReadyToRun"/>
    519       <status xil_pn:value="OutOfDateForInputs"/>
     487    <transform xil_pn:end_ts="1389786150" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1389786150">
     488      <status xil_pn:value="SuccessfullyRun"/>
     489      <status xil_pn:value="ReadyToRun"/>
     490    </transform>
     491    <transform xil_pn:end_ts="1389882619" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2338681308976167439" xil_pn:start_ts="1389882619">
     492      <status xil_pn:value="SuccessfullyRun"/>
     493      <status xil_pn:value="ReadyToRun"/>
     494      <status xil_pn:value="OutOfDateForProperties"/>
    520495      <status xil_pn:value="OutOfDateForPredecessor"/>
    521       <status xil_pn:value="InputChanged"/>
    522       <outfile xil_pn:name="CORE_MPI.bld"/>
    523       <outfile xil_pn:name="CORE_MPI.ngd"/>
    524       <outfile xil_pn:name="CORE_MPI_ngdbuild.xrpt"/>
    525       <outfile xil_pn:name="_ngo"/>
    526       <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    527     </transform>
    528     <transform xil_pn:end_ts="1389724025" xil_pn:in_ck="4512930838117587152" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4079613270754646221" xil_pn:start_ts="1389724003">
    529       <status xil_pn:value="FailedRun"/>
    530       <status xil_pn:value="ReadyToRun"/>
    531       <status xil_pn:value="OutOfDateForPredecessor"/>
    532       <outfile xil_pn:name="CORE_MPI_map.map"/>
    533       <outfile xil_pn:name="CORE_MPI_map.mrp"/>
    534       <outfile xil_pn:name="CORE_MPI_map.ngm"/>
    535       <outfile xil_pn:name="CORE_MPI_map.xrpt"/>
    536       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
    537496    </transform>
    538497  </transforms>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise

    r74 r76  
    314314    </file>
    315315    <file xil_pn:name="SetBit.vhd" xil_pn:type="FILE_VHDL">
     316      <association xil_pn:name="BehavioralSimulation"/>
     317      <association xil_pn:name="Implementation"/>
     318    </file>
     319    <file xil_pn:name="HT_4.vhd" xil_pn:type="FILE_VHDL">
     320      <association xil_pn:name="BehavioralSimulation"/>
     321      <association xil_pn:name="Implementation"/>
     322    </file>
     323    <file xil_pn:name="IP_Timer.vhd" xil_pn:type="FILE_VHDL">
     324      <association xil_pn:name="BehavioralSimulation"/>
     325      <association xil_pn:name="Implementation"/>
     326    </file>
     327    <file xil_pn:name="HCL_Arch_conf.vhd" xil_pn:type="FILE_VHDL">
    316328      <association xil_pn:name="BehavioralSimulation"/>
    317329      <association xil_pn:name="Implementation"/>
    … …  
    444456    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    445457    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    446     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CORE_MPI|Structural" xil_pn:valueState="non-default"/>
    447     <property xil_pn:name="Implementation Top File" xil_pn:value="CORE_MPI.vhd" xil_pn:valueState="non-default"/>
    448     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MultiMPITest/Xbar/hardmpi" xil_pn:valueState="non-default"/>
     458    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/>
     459    <property xil_pn:name="Implementation Top File" xil_pn:value="MultiMPITest.vhd" xil_pn:valueState="non-default"/>
     460    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MultiMPITest" xil_pn:valueState="non-default"/>
    449461    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    450462    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    497509    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    498510    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
    499     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    500     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     511    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
     512    <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
    501513    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
    502514    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    522534    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    523535    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    524     <property xil_pn:name="Output File Name" xil_pn:value="CORE_MPI" xil_pn:valueState="default"/>
     536    <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    525537    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    526538    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
    … …  
    538550    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    539551    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    540     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CORE_MPI_map.vhd" xil_pn:valueState="default"/>
    541     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CORE_MPI_timesim.vhd" xil_pn:valueState="default"/>
    542     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CORE_MPI_synthesis.vhd" xil_pn:valueState="default"/>
    543     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CORE_MPI_translate.vhd" xil_pn:valueState="default"/>
     552    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/>
     553    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/>
     554    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/>
     555    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/>
    544556    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
    545557    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    … …  
    567579    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    568580    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    569     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="CORE_MPI" xil_pn:valueState="default"/>
     581    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/>
    570582    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    571583    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf

    r74 r76  
    22#Created by Constraints Editor (xc6slx45-csg324-3) - 2012/12/19
    33NET "clkm" TNM_NET = clkm;
    4 TIMESPEC TS_clkm = PERIOD "clkm" 15 ns HIGH 50%;
     4TIMESPEC TS_clkm = PERIOD "clkm" 18 ns HIGH 50%;
    55PIN "reset_IBUF_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
    66NET "reset" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
    7 
     7NET "clk"   LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
    88# onBoard Leds
    99 NET "result<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15,       Sch name = LD0
    … …  
    1515 NET "result<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
    1616 NET "result<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2,                 Sch name = M1/LD7
    17 
     17#

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd

    r74 r76  
    2929use NocLib.CoreTypes.all;
    3030use work.Packet_type.all;
    31 
     31use work.Hcl_Arch_conf.all;
    3232USE ieee.numeric_std.ALL;
    3333 
    … …  
    9090 
    9191BEGIN
    92  Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC)
     92 Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE)
    9393                PORT MAP (
    9494          MPI_Node_in => MPI_Node_in,
    … …  
    9696        );
    9797
    98 PE1: PE generic map (DestId=>0)
    99 Port Map (
    100 Instruction => MPi_Node_in(1).Instruction,
    101            Instruction_en => MPi_Node_in(1).Instruction_en,
    102                           Core_PushOut => MPi_Node_out(1).PushOut,
    103            clk =>clkm,
    104            reset =>reset,
    105                           CE => '1',
    106            Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
    107            Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
    108            Core_RAM_WE => MPI_Node_out(1).ram_we,
    109            Core_RAM_EN => MPI_Node_out(1).ram_en,
    110           -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
    111            Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
    112            Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
    113            Core_Hold_req => MPI_Node_out(1).hold_req,
    114            Core_Hold_Ack => MPI_Node_in(1).hold_ack
    115 );
    116 
    117 PE2: PE         Generic map (DestId=>1)
    118                         Port Map (
    119                                 Instruction => MPi_Node_in(2).Instruction,
    120            Instruction_en => MPi_Node_in(2).Instruction_en,
    121                           Core_PushOut => MPi_Node_out(2).PushOut,
    122            clk =>clkm,
    123            reset =>reset,
    124                           CE => '1',
    125            Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
    126            Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
    127            Core_RAM_WE => MPI_Node_out(2).ram_we,
    128            Core_RAM_EN => MPI_Node_out(2).ram_en,
    129            --Core_RAM_ENB => MPI_Node_out(2).ram_en,
    130            Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
    131            Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
    132            Core_Hold_req => MPI_Node_out(2).hold_req,
    133            Core_Hold_Ack => MPI_Node_in(2).hold_ack
    134 );
     98--PE1: PE generic map (DestId=>0)
     99--Port Map (
     100--Instruction => MPi_Node_in(1).Instruction,
     101--           Instruction_en => MPi_Node_in(1).Instruction_en,
     102--                        Core_PushOut => MPi_Node_out(1).PushOut,
     103--           clk =>clkm,
     104--           reset =>reset,
     105--                        CE => '1',
     106--           Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
     107--           Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
     108--           Core_RAM_WE => MPI_Node_out(1).ram_we,
     109--           Core_RAM_EN => MPI_Node_out(1).ram_en,
     110--          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
     111--           Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
     112--           Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
     113--           Core_Hold_req => MPI_Node_out(1).hold_req,
     114--           Core_Hold_Ack => MPI_Node_in(1).hold_ack
     115--);
     116--
     117--PE2: PE       Generic map (DestId=>1)
     118--                      Port Map (
     119--                              Instruction => MPi_Node_in(2).Instruction,
     120--           Instruction_en => MPi_Node_in(2).Instruction_en,
     121--                        Core_PushOut => MPi_Node_out(2).PushOut,
     122--           clk =>clkm,
     123--           reset =>reset,
     124--                        CE => '1',
     125--           Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
     126--           Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
     127--           Core_RAM_WE => MPI_Node_out(2).ram_we,
     128--           Core_RAM_EN => MPI_Node_out(2).ram_en,
     129--           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
     130--           Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
     131--           Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
     132--           Core_Hold_req => MPI_Node_out(2).hold_req,
     133--           Core_Hold_Ack => MPI_Node_in(2).hold_ack
     134--);
    135135--PE3: PE generic map (DestId=>2)
    136136--Port Map (
    … …  
    170170--           Core_Hold_Ack => MPI_Node_in(4).hold_ack
    171171--);
    172 MPI_Node_in(1).reset<=reset;   
    173 MPI_Node_in(1).clk<=clkm;
    174 MPI_Node_in(2).reset<=reset;   
    175 MPI_Node_in(2).clk<=clkm;
     172--MPI_Node_in(1).reset<=reset; 
     173--MPI_Node_in(1).clk<=clkm;
     174--MPI_Node_in(2).reset<=reset; 
     175--MPI_Node_in(2).clk<=clkm;
    176176--MPI_Node_in(3).reset<=reset; 
    177177--MPI_Node_in(3).clk<=clkm;
    … …  
    179179--MPI_Node_in(4).clk<=clkm;
    180180Result<=MPi_Node_out(1).PushOut;
    181 PE_Dyn:for i in 3 to 4 generate
    182 PE_i: PE        Generic map (DestId=>i-1)
     181PE_s:for i in 1 to STATIC_HT generate
     182S: PE   Generic map (DestId=>i-1)
     183                        Port Map (
     184                                Instruction => MPi_Node_in(i).Instruction,
     185           Instruction_en => MPi_Node_in(i).Instruction_en,
     186                          Core_PushOut => MPi_Node_out(i).PushOut,
     187           clk =>clkm,
     188           reset =>reset,
     189                          CE => '1',
     190           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
     191           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
     192           Core_RAM_WE => MPI_Node_out(i).ram_we,
     193           Core_RAM_EN => MPI_Node_out(i).ram_en,
     194           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
     195           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
     196           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
     197           Core_Hold_req => MPI_Node_out(i).hold_req,
     198           Core_Hold_Ack => MPI_Node_in(i).hold_ack
     199);
     200MPI_Node_in(i).reset<=reset;   
     201MPI_Node_in(i).clk<=clkm;
     202end generate PE_s;
     203dyn_HT: if dyn_allowed='1' generate
     204PE_D:for i in STATIC_HT+1 to NOC_SIZE generate
     205D: PE   Generic map (DestId=>i-1)
    183206                        Port Map (
    184207                                Instruction => MPi_Node_in(i).Instruction,
    … …  
    200223MPI_Node_in(i).reset<=reset;   
    201224MPI_Node_in(i).clk<=clkm;
    202 end generate PE_Dyn;
     225end generate PE_D;
     226end generate dyn_HT;
    203227END;

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html

    r74 r76  
    33<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    44<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
    5 <TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (01/14/2014 - 19:51:11)</B></TD></TR>
     5<TD ALIGN=CENTER COLSPAN='4'><B>FIFO Project Status (01/16/2014 - 15:56:56)</B></TD></TR>
    66<TR ALIGN=LEFT>
    77<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
    … …  
    1414<TD>MultiMPITest</TD>
    1515<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
    16 <TD>Synthesized</TD>
     16<TD>Mapped</TD>
    1717</TR>
    1818<TR ALIGN=LEFT>
    … …  
    6767<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
    6868<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
    69 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue 14. Jan 19:05:30 2014</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    70 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue 14. Jan 19:05:50 2014</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    71 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue 14. Jan 19:07:24 2014</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     69<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed 15. Jan 15:00:16 2014</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
     70<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed 15. Jan 15:06:05 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>36 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
     71<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed 15. Jan 15:07:45 2014</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Error'>3 Errors (2 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (3 new)</A></TD></TR>
    7272<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Mon 13. Jan 19:36:05 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>1659 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
    73 <TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    7473<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    7574<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Mon 13. Jan 19:37:30 2014</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
    … …  
    8079<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
    8180<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 8. Aug 16:31:11 2013</TD></TR>
     81<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 19. Dec 17:30:44 2012</TD></TR>
     82<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\netgen/par/MultiMPITest_timesim.nlf'>Post-Place and Route Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 14. Jan 07:44:23 2014</TD></TR>
    8283<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Jun 23:56:05 2013</TD></TR>
    8384<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Jun 23:56:14 2013</TD></TR>
    … …  
    8586
    8687
    87 <br><center><b>Date Generated:</b> 01/14/2014 - 20:09:39</center>
     88<br><center><b>Date Generated:</b> 01/16/2014 - 19:06:43</center>
    8889</BODY></HTML>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd

    r74 r76  
    7878                          );
    7979end COMPONENT HT_process;
     80 
    8081COMPONENT Hold_FSM is
    8182       
    … …  
    144145  mem_i =>sram.i,
    145146   mem_o =>sram.o       );
    146 
     147 
    147148--================================================================
    148149        --MUX de la RAM

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SWITCH_GEN.ucf

    r66 r76  
    22#Created by Constraints Editor (xc6slx45-csg324-3) - 2013/01/04
    33NET "clk" TNM_NET = clk;
    4 TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%;
     4TIMESPEC TS_clk = PERIOD "clk" 18 ns HIGH 50%;

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r74 r76  
    1717         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral</ClosedNode>
    1818         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral</ClosedNode>
     19         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral</ClosedNode>
     20         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    1921         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    2022         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    … …  
    187189         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE3 - PE - Behavioral</ClosedNode>
    188190         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode>
     191         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_PKG</ClosedNode>
     192         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    189193         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    190194         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
    … …  
    243247         <ClosedNode>/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/conversions</ClosedNode>
    244248         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
     249         <ClosedNode>/Unassigned User Library Modules</ClosedNode>
    245250         <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral</ClosedNode>
    246251         <ClosedNode>/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
    … …  
    378383         <ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
    379384         <ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
    380          <ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
    381          <ClosedNode>User Constraints</ClosedNode>
    382       </ClosedNodes>
    383       <SelectedItems>
    384          <SelectedItem>View/Edit Routed Design (FPGA Editor)</SelectedItem>
    385       </SelectedItems>
    386       <ScrollbarPosition orientation="vertical" >17</ScrollbarPosition>
     385      </ClosedNodes>
     386      <SelectedItems>
     387         <SelectedItem>Synthesize - XST</SelectedItem>
     388      </SelectedItems>
     389      <ScrollbarPosition orientation="vertical" >2</ScrollbarPosition>
    387390      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    388391      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000014b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
    389392      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    390       <CurrentItem>View/Edit Routed Design (FPGA Editor)</CurrentItem>
     393      <CurrentItem>Synthesize - XST</CurrentItem>
    391394   </ItemView>
    392395   <ItemView guiview="File" >
    … …  
    395398      </ClosedNodes>
    396399      <SelectedItems>
    397          <SelectedItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</SelectedItem>
    398       </SelectedItems>
    399       <ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
     400         <SelectedItem>C:\Core MPI\CORE_MPI\MultiMPITest.ucf</SelectedItem>
     401      </SelectedItems>
     402      <ScrollbarPosition orientation="vertical" >52</ScrollbarPosition>
    400403      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    401404      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
    402405      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    403       <CurrentItem>C:\Core MPI\CORE_MPI\EX4_FSM.vhd</CurrentItem>
     406      <CurrentItem>C:\Core MPI\CORE_MPI\MultiMPITest.ucf</CurrentItem>
    404407   </ItemView>
    405408   <ItemView guiview="Library" >
    … …  
    412415      <ScrollbarPosition orientation="vertical" >50</ScrollbarPosition>
    413416      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    414       <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000014b000000010001000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000</ViewHeaderState>
     417      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
    415418      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    416419      <CurrentItem>C:\Core MPI\CORE_MPI\MultiMPITest.vhd</CurrentItem>
    … …  
    419422      <ClosedNodes>
    420423         <ClosedNodesVersion>1</ClosedNodesVersion>
    421          <ClosedNode>Design Utilities</ClosedNode>
    422       </ClosedNodes>
    423       <SelectedItems>
    424          <SelectedItem></SelectedItem>
     424         <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
     425      </ClosedNodes>
     426      <SelectedItems>
     427         <SelectedItem>Design Utilities</SelectedItem>
    425428      </SelectedItems>
    426429      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    428431      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    429432      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    430       <CurrentItem></CurrentItem>
     433      <CurrentItem>Design Utilities</CurrentItem>
    431434   </ItemView>
    432435   <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
    … …  
    442445         <ClosedNode>/FIFO - TOP_HIER C:|Core MPI|CORE_MPI|FIfo_mem.vhd</ClosedNode>
    443446         <ClosedNode>/Image_Pkg C:|Core MPI|CORE_MPI|image_pkg.vhd</ClosedNode>
    444          <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural</ClosedNode>
    445447         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral</ClosedNode>
    446448         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral</ClosedNode>
    447449         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral</ClosedNode>
     450         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral</ClosedNode>
    448451         <ClosedNode>/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral</ClosedNode>
    449452         <ClosedNode>/MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd</ClosedNode>
    … …  
    537540      </ClosedNodes>
    538541      <SelectedItems>
    539          <SelectedItem>mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd)</SelectedItem>
    540       </SelectedItems>
    541       <ScrollbarPosition orientation="vertical" >8</ScrollbarPosition>
    542       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    543       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000</ViewHeaderState>
    544       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    545       <CurrentItem>mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd)</CurrentItem>
     542         <SelectedItem>Unassigned User Library Modules</SelectedItem>
     543      </SelectedItems>
     544      <ScrollbarPosition orientation="vertical" >2</ScrollbarPosition>
     545      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     546      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000</ViewHeaderState>
     547      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     548      <CurrentItem>Unassigned User Library Modules</CurrentItem>
    546549   </ItemView>
    547550   <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
    … …  
    551554      </ClosedNodes>
    552555      <SelectedItems>
    553          <SelectedItem/>
     556         <SelectedItem>Update All Schematic Files</SelectedItem>
    554557      </SelectedItems>
    555558      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    557560      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    558561      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    559       <CurrentItem/>
     562      <CurrentItem>Update All Schematic Files</CurrentItem>
    560563   </ItemView>
    561564   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
    … …  
    564567      </ClosedNodes>
    565568      <SelectedItems>
    566          <SelectedItem>ModelSim Simulator</SelectedItem>
     569         <SelectedItem></SelectedItem>
    567570      </SelectedItems>
    568571      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    … …  
    570573      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
    571574      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    572       <CurrentItem>ModelSim Simulator</CurrentItem>
     575      <CurrentItem></CurrentItem>
    573576   </ItemView>
    574577   <SourceProcessView>000000ff0000000000000002000000d1000000d101000000050100000002</SourceProcessView>
    575    <CurrentView>Behavioral Simulation</CurrentView>
     578   <CurrentView>Implementation</CurrentView>
    576579   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
    577580      <ClosedNodes>
    … …  
    762765         <ClosedNodesVersion>1</ClosedNodesVersion>
    763766      </ClosedNodes>
    764       <SelectedItems/>
    765       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
    766       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
    767       <ViewHeaderState orientation="horizontal" />
    768       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
    769       <CurrentItem/>
     767      <SelectedItems>
     768         <SelectedItem></SelectedItem>
     769      </SelectedItems>
     770      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     771      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     772      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     773      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     774      <CurrentItem></CurrentItem>
     775   </ItemView>
     776   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
     777      <ClosedNodes>
     778         <ClosedNodesVersion>1</ClosedNodesVersion>
     779      </ClosedNodes>
     780      <SelectedItems>
     781         <SelectedItem></SelectedItem>
     782      </SelectedItems>
     783      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     784      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     785      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     786      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     787      <CurrentItem></CurrentItem>
     788   </ItemView>
     789   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
     790      <ClosedNodes>
     791         <ClosedNodesVersion>1</ClosedNodesVersion>
     792      </ClosedNodes>
     793      <SelectedItems>
     794         <SelectedItem></SelectedItem>
     795      </SelectedItems>
     796      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
     797      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
     798      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
     799      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
     800      <CurrentItem></CurrentItem>
    770801   </ItemView>
    771802</Project>

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport

    r74 r76  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2014-01-14T19:54:07</DateModified>
    5   <ModuleName>CORE_MPI</ModuleName>
    6   <SummaryTimeStamp>2014-01-14T19:51:12</SummaryTimeStamp>
     4  <DateModified>2014-01-15T10:32:39</DateModified>
     5  <ModuleName>MultiMPITest</ModuleName>
     6  <SummaryTimeStamp>2014-01-15T10:32:39</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2014-01-14T19:22:02</DateInitialized>
     9  <DateInitialized>2014-01-15T10:26:54</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
    1111 </header>
    1212 <body>
    1313  <viewgroup label="Design Overview" >
    14    <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="false" type="FPGASummary" file="CORE_MPI_summary.html" label="Summary" ExpandClockNets="false" ExpandWarnings="true" >
     14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" ExpandConstraints="false" type="FPGASummary" file="MultiMPITest_summary.html" label="Summary" ExpandClockNets="false" ExpandWarnings="true" >
    1515    <toc-item title="Design Overview" target="Design Overview" />
    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
    2525    <table-item tableState="ExpandedTable" tableKey="DetailedReports" />
    2626   </view>
    27    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CORE_MPI_envsettings.html" label="System Settings" />
    28    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CORE_MPI_map.xrpt" showConstraints="0" label="IOB Properties" />
    29    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CORE_MPI_map.xrpt" label="Control Set Information" />
    30    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CORE_MPI_map.xrpt" label="Module Level Utilization" />
    31    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CORE_MPI.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
    32    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Pinout Report" />
    33    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CORE_MPI_par.xrpt" showConstraints="0" label="Clock Report" />
    34    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CORE_MPI.twx" label="Static Timing" />
    35    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/fit/report.htm" label="CPLD Fitter Report" />
    36    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CORE_MPI_html/tim/report.htm" label="CPLD Timing Report" />
     27   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="MultiMPITest_envsettings.html" label="System Settings" />
     28   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="MultiMPITest_map.xrpt" showConstraints="0" label="IOB Properties" />
     29   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="MultiMPITest_map.xrpt" label="Control Set Information" />
     30   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="MultiMPITest_map.xrpt" label="Module Level Utilization" />
     31   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="MultiMPITest.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
     32   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="MultiMPITest_par.xrpt" showConstraints="0" label="Pinout Report" />
     33   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="MultiMPITest_par.xrpt" showConstraints="0" label="Clock Report" />
     34   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="MultiMPITest.twx" label="Static Timing" />
     35   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/fit/report.htm" label="CPLD Fitter Report" />
     36   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="MultiMPITest_html/tim/report.htm" label="CPLD Timing Report" />
    3737  </viewgroup>
    3838  <viewgroup label="XPS Errors and Warnings" >
    … …  
    4747   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
    4848   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
    49    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CORE_MPI.log" label="System Log File" />
     49   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="MultiMPITest.log" label="System Log File" />
    5050  </viewgroup>
    5151  <viewgroup label="Errors and Warnings" >
    … …  
    6363  </viewgroup>
    6464  <viewgroup label="Detailed Reports" >
    65    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CORE_MPI.syr" label="Synthesis Report" >
     65   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="MultiMPITest.syr" label="Synthesis Report" >
    6666    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
    6767    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
    … …  
    8989    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
    9090   </view>
    91    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.srr" label="Synplify Report" />
    92    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.prec_log" label="Precision Report" />
    93    <view inputState="Synthesized" program="ngdbuild" type="Report" file="CORE_MPI.bld" label="Translation Report" >
     91   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.srr" label="Synplify Report" />
     92   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.prec_log" label="Precision Report" />
     93   <view inputState="Synthesized" program="ngdbuild" type="Report" file="MultiMPITest.bld" label="Translation Report" >
    9494    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    9595    <toc-item title="Command Line" target="Command Line:" />
    … …  
    9797    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
    9898   </view>
    99    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI_map.mrp" label="Map Report" >
     99   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest_map.mrp" label="Map Report" >
    100100    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    101101    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    113113    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
    114114   </view>
    115    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.par" label="Place and Route Report" >
     115   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.par" label="Place and Route Report" >
    116116    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    117117    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
    … …  
    122122    <toc-item title="Final Summary" target="Peak Memory Usage:" />
    123123   </view>
    124    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.twr" label="Post-PAR Static Timing Report" >
     124   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.twr" label="Post-PAR Static Timing Report" >
    125125    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    126126    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    133133    <toc-item title="Trace Settings" target="Trace Settings:" />
    134134   </view>
    135    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.rpt" label="CPLD Fitter Report (Text)" >
     135   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.rpt" label="CPLD Fitter Report (Text)" >
    136136    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    137137    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    139139    <toc-item title="Global Resources" target="** Global Control Resources **" />
    140140   </view>
    141    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CORE_MPI.tim" label="CPLD Timing Report (Text)" >
     141   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="MultiMPITest.tim" label="CPLD Timing Report (Text)" >
    142142    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    143143    <toc-item title="Performance Summary" target="Performance Summary:" />
    144144   </view>
    145    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CORE_MPI.pwr" label="Power Report" >
     145   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="MultiMPITest.pwr" label="Power Report" >
    146146    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    147147    <toc-item title="Power summary" target="Power summary" />
    148148    <toc-item title="Thermal summary" target="Thermal summary" />
    149149   </view>
    150    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CORE_MPI.bgn" label="Bitgen Report" >
     150   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="MultiMPITest.bgn" label="Bitgen Report" >
    151151    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    152152    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    156156  <viewgroup label="Secondary Reports" >
    157157   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    158    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CORE_MPI_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    159     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    160    </view>
    161    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CORE_MPI_translate.nlf" label="Post-Translate Simulation Model Report" >
    162     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    163    </view>
    164    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    165    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI_map.map" label="Map Log File" >
     158   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/MultiMPITest_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     159    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     160   </view>
     161   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/MultiMPITest_translate.nlf" label="Post-Translate Simulation Model Report" >
     162    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     163   </view>
     164   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     165   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest_map.map" label="Map Log File" >
    166166    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    167167    <toc-item title="Design Information" target="Design Information" />
    … …  
    169169   </view>
    170170   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    171    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.twr" label="Post-Map Static Timing Report" >
     171   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.twr" label="Post-Map Static Timing Report" >
    172172    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    173173    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    180180    <toc-item title="Trace Settings" target="Trace Settings:" />
    181181   </view>
    182    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CORE_MPI_map.nlf" label="Post-Map Simulation Model Report" />
    183    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_map.psr" label="Physical Synthesis Report" >
    184     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    185    </view>
    186    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CORE_MPI_pad.txt" label="Pad Report" >
    187     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    188    </view>
    189    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CORE_MPI.unroutes" label="Unroutes Report" >
    190     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    191    </view>
    192    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    193     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    194    </view>
    195    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.grf" label="Guide Results Report" />
    196    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.dly" label="Asynchronous Delay Report" />
    197    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.clk_rgn" label="Clock Region Report" />
    198    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.tsi" label="Post-Place and Route Constraints Interaction Report" >
    199     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    200    </view>
    201    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    202    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CORE_MPI_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    203    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CORE_MPI_sta.nlf" label="Primetime Netlist Report" >
    204     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    205    </view>
    206    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.ibs" label="IBIS Model" >
     182   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/MultiMPITest_map.nlf" label="Post-Map Simulation Model Report" />
     183   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_map.psr" label="Physical Synthesis Report" >
     184    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     185   </view>
     186   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="MultiMPITest_pad.txt" label="Pad Report" >
     187    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     188   </view>
     189   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="MultiMPITest.unroutes" label="Unroutes Report" >
     190    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     191   </view>
     192   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     193    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     194   </view>
     195   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.grf" label="Guide Results Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.dly" label="Asynchronous Delay Report" />
     197   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.clk_rgn" label="Clock Region Report" />
     198   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.tsi" label="Post-Place and Route Constraints Interaction Report" >
     199    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     200   </view>
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     202   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/MultiMPITest_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     203   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="MultiMPITest_sta.nlf" label="Primetime Netlist Report" >
     204    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     205   </view>
     206   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.ibs" label="IBIS Model" >
    207207    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    208208    <toc-item title="Component" target="Component " />
    209209   </view>
    210    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lck" label="Back-annotate Pin Report" >
     210   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lck" label="Back-annotate Pin Report" >
    211211    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    212212    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    213213   </view>
    214    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CORE_MPI.lpc" label="Locked Pin Constraints" >
     214   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="MultiMPITest.lpc" label="Locked Pin Constraints" >
    215215    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    216216    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    217217   </view>
    218    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CORE_MPI_timesim.nlf" label="Post-Fit Simulation Model Report" />
     218   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/MultiMPITest_timesim.nlf" label="Post-Fit Simulation Model Report" />
    219219   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    220220   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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