source: trunk/modules/vci_cc_vcache_wrapper2_v1

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Diff Rev Age Author Log Message
(edit) @101   14 years gao Delete the evaluation codes for speedup simulation
(edit) @96   14 years gao Redo ins TLB access bit update when it miss in dcache
(edit) @88   14 years gao Correction of itlb access bit set and dtlb dirty bit set
(edit) @84   14 years bouyer ICACHE_SW_FLUSH/ICACHE_CACHE_FLUSH: when walking the tlb/cache looking …
(edit) @80   14 years gao Modified the coherence check for TLB entry updating
(edit) @79   14 years gao Correction of dirty bit and access bit in data cache
(edit) @73   14 years bouyer Fix several issues regarding management of the …
(edit) @72   14 years bouyer 2 fixes: - do not test r_dcache_in_[id]tlb[] just after setting the …
(edit) @71   14 years bouyer When updating PTE bits, don't write back to the dcache locally, the …
(edit) @70   14 years bouyer Check/update the dirty bit on SC too
(edit) @69   14 years bouyer Fix cut'n'paste error
(edit) @68   14 years bouyer A SC cause the dcache entry to be updated by the memcache, and the tlb …
(edit) @62   14 years gao Debug infos deleted
(edit) @56   15 years guthmull SC don't generate invalidations and cleanup any more, add treatment of …
(edit) @55   15 years guthmull Fix a bug in SC, add start cycle debug
(edit) @53   15 years gao debug
(edit) @51   15 years gao Activity counter update
(edit) @50   15 years gao Activity counter update
(edit) @48   15 years gao Activity counter update
(edit) @37   15 years gao Bug correction
(edit) @20   15 years nipo Update DSX metadata
(edit) @13   15 years bouyer Fix build with systemcass (add .read() on register access)
(edit) @12   15 years gao bug correction
(add) @2   15 years nipo Import TSAR modules in TSAR's own svn
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