source: anr/section-1.tex @ 239

% les objectifs globaux, 
The market of digital systems is about 4,600 M\$ today and is estimated to
5,600 M\$ in 2012. However the ever growing applications complexity involves
integration of heterogeneous technologies and requires the design of
complex Multi-Processors System on Chip (MPSoC).
\\
\mustbecompleted{FIXME :: A relire, j'ai modifie le paragraphe suivant en motivant plus}
During the last decade, the design of ASICs (Application Specific
Integrated Circuits) appeared to be more and more reserved to high volume markets, because
the design and fabrication costs of such components exploded, due to increasing NRE (Non
Recurring-Engineering) costs.
Fortunately, FPGA (Field Programmable Gate Array) components, such as the
Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
implement a complete MPSoC with multiple processors and several dedicated
coprocessors for a few Keuros per device. Many applications are initially captured 
algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest 
in tools that can provide an implementation path directly from HLLs to hardware. 
Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
Co-design, High-Level Synthesis...) are now mature and allow the automation of
a system-level design flow. Unfortunately, ESL tool development to date has primarily focused 
on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). 
However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design 
methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting 
designs written in C/C++ language and implementing the function straight into FPGA. 
We believe that coupling FPGA technologies and ESL methodologies
will allow both SMEs (Small and Medium Enterprise) and
major companies to design innovative devices and to enter new, low and
medium volume markets.
\parlf
The objective of COACH is to provide an integrated design flow, based on the
SoCLib infrastructure~\cite{soclib}, and optimized for the design of
multi-processors digital systems targeting FPGA devices.
Such digital systems are generally integrated
into one or several chips, and there are two types of applications:
They can be embedded (autonomous) applications
such as personal digital assistants (PDA), ambiant computing components,
or wireless sensor networks (WSN).
They can also be extension boards connected to a PC to accelerate a specific computation,
as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
\parlf
%verrous scientifiques et techniques
The COACH environment will integrate several hardware and software technologies:
\begin{description}
\item[Design Space Exploration:]
    The COACH environment will support design space exploration to help the
    system designer to select and parameterize the target architecture, and to
    define the proper hardware/software partitioning of the application.
    For each point in the design space, metrics such as throughput, latency, power
    consumption, silicon area, memory allocation and data locality will be provided.
    These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
    and high-level estimation methodologies.
        \mustbecompleted{FIXME :: Question que l'on peut se poser sur DSE : quelle est la nouveaté la dedans ?
        Doit on parler ici de modele de programmation, de mapping... qui permettent un DSE?}
        
\item[Hardware Accelerators Synthesis (HAS):]
    COACH will allow the automatic generation of hardware accelerators when required.
    Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
    (ASIP) design environment and source-level transformation tools (loop transformations
    and memory optimisation) will be provided.
    This will allow further exploration of the micro-architectural design space.
    HLS tools are sensitive to the coding style of the input specification and the domain
    they target (control vs. data dominated).
    The HLS tools of COACH will support a common language and coding style to avoid
    re-engineering by the designer.
\item[Platform based design:] 
    COACH will handle both \altera and \xilinx FPGA devices.
    COACH will define architectural templates that can be customized by adding
    dedicated coprocessors and ASIPs and by fixing template parameters such as
    the number of embedded processors, the number of sizes of embedded memory banks
    or the embedded the operating system.
    However, the specification of the application will be independant of both the
    architectural template and the target FPGA device.
    Basically, the following three architectural templates will be provided:
    \begin{enumerate}
    \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
      VCI/OCP communication infrastructure.
    \item An \altera architectural template based on the \altera IP core library, the
      AVALON system bus and the NIOS processor.
    \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
      system bus and the Microblaze processor.
    \end{enumerate}
\item[Hardware/Software communication middleware:]
    COACH will implement an homogeneous HW/SW communication infrastructure and
    communication APIs (Application Programming Interface), that will be used for 
    communications between software tasks running on embedded processors and 
    dedicated hardware coprocessors.
\end{description}
The COACH design flow will be dedicated to system designers, and will as
much as possible hide the hardware characteristics to the end-user.
%From the end user point of view, the specification of the application will be
%independant from both the architectural template and from the selected FPGA
%family.
\parlf
% le programme de travail
%The COACH project targets fundamental issues related to design methodologies for 
%digital systems by providing estimation, exploration and design tools targeting both 
%performance and power optimization at all the abstraction levels of the flow (system, 
%architecture, algorithm and logic).
To reach this ambitious goal, the project will rely on the experience and the
complementariness of partners in the following domains:
Operating system and communication middleware (\tima, \upmc),
MPSoC architectures (\tima, \ubs, \upmc),
ASIP architectures (\irisa),
High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip).
\\
The COACH project does not start from scratch.
It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).
It also leverages on  several existing technologies:
on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
on the ROMA~\cite{roma} project for ASIP,
on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
and on the \xilinx and \altera IP core libraries.
Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration
bitstreams.
\parlf
The COACH proposal has been prepared during one year by a technical working group
involving the 5 academic partners (one monthly meeting from january 2009 to february
2010). The objective was to analyse the issues of integrating
and enhancing the existing tools and tecnnologies into a unique framework.
Most of the general software architecture of the proposed design flow (including the
exchange format specification) has been define by this working group.
Because the SoCLib platform is the \mustbecompleted{FIXME Fundation, root, basis a la place de base???} base of this project, it may be described as an
extension of the SoCLib platform.
%The main development steps of the COACH project are: 
%\begin{enumerate}
%   \item Definition of the end user inputs:
%    The coarse grain parallelism of the application will be described as a communicating
%    task graph, each task being described in C language.
%    Similarly the architectural templates with their parameters and the design constraints
%    will be specified.
%  \item Definition of an internal format for representing task.
%  \item Development of the GCC pluggin for generating the internal format of a
%    C task.
%  \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write
%    the internal format. This will allow to swap from one tool to another one, and to
%    chain them if necessary.
%  \item Modification of the DSX tool (Design Space eXplorer) of the SocLib
%    platform to generate the bitstream for the various FPGA families and architectural
%    templates.
%  \item Development of new tools such as ASIP compiler, HPC design environment and
%    dynamic reconfiguration of FPGA devices.
%\end{enumerate}
\parlf
Two major FPGA companies are involved in the project : \xilinx will contribute
as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
providing documentation and development boards. These two companies are strongly motivated
to help the COACH project to generate efficient bitsreams for both FPGA families.
The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
real use cases to benchmark the COACH design environment and to analyze the designer productivity 
improvements. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
sont fournisseur de techno et non de uses cases no ???}
\parlf
Following the general policy of the SoCLib platform, the COACH project will be an open
infrastructure, available in the framework of the SoCLib server.
The architectural templates, and the COACH software tools will be distributed under the
GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
IP core library) will be freely available for non commercial use. For industrial exploitation
the technology providers are ready to propose commercial licenses, directly to the end user,
or through a third party.