[12] | 1 | % les objectifs scientifiques/techniques du projet. |
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[269] | 2 | The design steps are presented figure~\ref{coach-flow}. |
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[275] | 3 | \ADDED{ |
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| 4 | The end-user input is |
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| 5 | either a HPC application (an application running on a PC that must be accelarate), |
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| 6 | or an embedded application (a standalone application), |
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[280] | 7 | or a sub-system application of a larger design. |
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| 8 | The figure shows that the design flow of embedded and sub-system applications does not differ |
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| 9 | except in the generation step and that the design flow of HPC application just adds a |
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| 10 | preliminary step. |
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| 11 | } |
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[12] | 12 | \begin{figure}[hbtp]\leavevmode\center |
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[280] | 13 | \includegraphics[width=1.0\linewidth]{flow2} |
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[182] | 14 | \caption{\label{coach-flow} COACH design flow} |
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[12] | 15 | \end{figure} |
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| 16 | \begin{description} |
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[104] | 17 | \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application |
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[269] | 18 | which remains on the PC and the SoC application which is mapped on the FPGA. |
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| 19 | COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) |
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| 20 | which will allow performance evaluation. |
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[104] | 21 | \item[SoC design:] In this phase, |
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[269] | 22 | COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. |
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| 23 | The user input will consist of a process network describing the coarse grain parallelism |
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[275] | 24 | of the application, an instance of an architectural template |
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| 25 | and a mapping of processes on the architectural template components. |
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[269] | 26 | COACH will offer different targets to map the processes: |
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| 27 | software (the process runs as a software task on a SoC processor), |
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| 28 | ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), |
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| 29 | and hardware (the process is implemented as a synthesized hardware coprocessor). |
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[280] | 30 | \begin{SUPPRESSEDENV} |
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[275] | 31 | \item[Application compilation:] |
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| 32 | Once the SoC architecture is validated through performances analysis, |
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| 33 | COACH will generate automatically an executable containing the host application and |
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[269] | 34 | the FPGA bitstream. This bitstream contains |
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| 35 | both the hardware architecture and the SoC application software. |
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| 36 | The user will be able to launch the application by |
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[33] | 37 | loading the bitstream on an FPGA and running the executable on PC. |
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[275] | 38 | \end{SUPPRESSEDENV}\begin{ADDEDENV} |
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[280] | 39 | \item[Generation:] |
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[275] | 40 | Once the SoC architecture is validated through performances analysis, |
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| 41 | COACH generates its bitstream in the case of HPC or embedded application, |
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[277] | 42 | or its IP-XACT description for its integration in the case of a sub-system application. |
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[275] | 43 | Both descriptions contain the hardware architecture and the application software. |
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| 44 | Furthermore in the HPC case, an executable containing the host application is |
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| 45 | also generated and the user will be able to launch the application by loading |
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| 46 | the bitstream on an FPGA and running the executable on PC. |
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| 47 | \end{ADDEDENV} |
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[12] | 48 | \end{description} |
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| 49 | |
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| 50 | % l'avancee scientifique attendue. Preciser l'originalite et le caractere |
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| 51 | % ambitieux du projet. |
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[104] | 52 | %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} |
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[12] | 53 | |
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[182] | 54 | %The main scientific contribution of the project is to unify various synthesis techniques |
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| 55 | %(same input and output formats) allowing the user to swap without engineering effort |
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| 56 | %from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. |
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| 57 | %Another advantage of this framework is to provide different abstraction levels from |
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| 58 | %a single description. |
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| 59 | %Finally, this description is device family independent and its hardware implementation |
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| 60 | %is automatically generated. |
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| 61 | |
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[12] | 62 | % Detailler les verrous scientifiques et techniques a lever par la realisation du projet. |
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[269] | 63 | Hardware/Software co-design is a very complex task. To simplify it, COACH will address the |
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| 64 | following scientific and technological barriers: |
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| 65 | \begin{description} |
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| 66 | \item[\textit{Design Space Exploration by Virtual Prototyping}]: |
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[280] | 67 | The COACH environment will allow to easily map a parallel application (formally described as |
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| 68 | an abstract network of process and communication channels) |
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| 69 | COACH will permit the system designer to explore the design space, and to define the best |
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| 70 | hardware/software partitioning of the application. |
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[272] | 71 | \item[\textit{Integration of system level modeling and HLS tools}]: |
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[280] | 72 | COACH will support the automated generation of hardware accelerators when required |
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| 73 | by using High-Level Synthesis (HLS) tools. These HLS tools will be |
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| 74 | fully integrated into a complete system-level design environment. |
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| 75 | Moreover, COACH will support both data and control dominated applications, |
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| 76 | and the HLS tools of COACH will support a common language and coding style |
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| 77 | to avoid re-engineering by the designer. |
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| 78 | COACH will provide a tool which will automatically explore the micro-architectural |
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| 79 | design space of coprocessor. |
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[269] | 80 | \item[\textit{High-level code transformation}]: |
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[280] | 81 | COACH will allow to optimize the memory usage, to enhance the parallelism through |
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| 82 | loop transformations and parallelization. The challenge is to identify the coarse |
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| 83 | grained parallelism and to generate, |
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| 84 | from a sequential algorithm, application containing multiple communicating |
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| 85 | tasks. COACH will adapt techniques which were developed in the 1990 for |
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| 86 | the construction of distributed programs. However, in the context of HLS, there are |
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| 87 | several original problems to be solved, related to the FIFO communication channels and with |
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| 88 | memory optimization. |
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| 89 | COACH will support code transformation by providing a source to source C2C tool. |
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[272] | 90 | \item[\textit{Unified Hardware/Software communication middleware}]: |
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[280] | 91 | COACH will rely on he SoCLib experience to implement an unified hardware/software communication |
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| 92 | infrastructure and communication APIs (Application Programming Interface), to support |
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| 93 | communications between software tasks running on embedded processors and dedicated |
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| 94 | hardware coprocessors. The main issue here is to support easy migration |
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| 95 | from a software implementation to an hardware implementation. |
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[269] | 96 | \item[\textit{Processor customization}]: |
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[280] | 97 | ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. |
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| 98 | COACH will allow system designers to explore the various level of interactions between |
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| 99 | the original CPU micro-architecture and its extension. It will also allow to retarget |
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| 100 | the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis |
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| 101 | in a complete System-level design framework. |
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[269] | 102 | \end{description} |
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[235] | 103 | |
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[12] | 104 | %Presenter les resultats escomptes en proposant si possible des criteres de reussite |
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| 105 | %et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en |
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| 106 | %fin de projet. |
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| 107 | The main result is the framework. It is composed concretely of: |
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[99] | 108 | a communication middleware for HPC, |
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| 109 | 5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, |
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[280] | 110 | Memory optimization HLS and ASIP), |
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[99] | 111 | 3 architectural templates that are synthesizable and that can be prototyped, |
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[12] | 112 | one design space exploration tool, |
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[280] | 113 | 1 operating systems (DNA/OS). |
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[12] | 114 | \\ |
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[280] | 115 | The framework functionalities will be demonstrated with the demonstrators |
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[99] | 116 | (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 |
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[235] | 117 | page~\ref{subtask-tutorial}). |
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