[23] | 1 | \begin{taskinfo} |
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| 2 | \let\UPMC\leader |
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| 3 | \let\IRISA\enable |
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[49] | 4 | \let\TIMA\enable |
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[113] | 5 | \let\XILINX\enable |
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[114] | 6 | \let\UBS\enable |
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[23] | 7 | \end{taskinfo} |
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| 8 | % |
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| 9 | \begin{objectif} |
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[39] | 10 | This task deals with the prototyping and the generation of FPGA-SoC digital systems. |
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[36] | 11 | Its is described on figure~\ref{archi-csg}. |
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[187] | 12 | Its objective is to allow the system designer to explore the design space by |
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[237] | 13 | quickly prototyping and then to automatically generate the FPGA-SoC systems. |
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[278] | 14 | This task consists of: |
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[23] | 15 | \begin{itemize} |
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[278] | 16 | \item The development of the synthesizable models required for the connection of |
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| 17 | the coprocessors on the platform bus (2 bridges). |
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[187] | 18 | \item The configuration and the development of drivers of the operating systems (Board Support Package, HAL), |
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| 19 | \item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system |
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[126] | 20 | including its bitstream and software executable code, |
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[23] | 21 | \end{itemize} |
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[278] | 22 | A first release will be delivered at $T0+12$ to allow the demonstrators to start working. |
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| 23 | This release will include the standard communication schemes based on SoCLib MWMR component |
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[134] | 24 | and support the neutral architectural template for prototyping and hardware generation. |
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[23] | 25 | \end{objectif} |
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| 26 | % |
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[52] | 27 | \begin{workpackage} |
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[278] | 28 | \subtask{Bridge implementation} |
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| 29 | This \ST deals with the development of the synthesizable models required for the connection of |
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| 30 | the coprocessors on the platform bus). |
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[23] | 31 | \begin{livrable} |
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[278] | 32 | \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} |
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| 33 | \setMacroInAuxFile{hpcPlbBridge} |
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| 34 | The synthesizable VHDL description of a PLB/VCI bridge. |
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| 35 | \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0} |
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| 36 | \setMacroInAuxFile{hpcAvalonBridge} |
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| 37 | The synthesizable VHDL description of an AVALON/VCI bridge. |
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[23] | 38 | \end{livrable} |
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[278] | 39 | \subtask{OS setup} This \ST consists of the configuration of the SocLib DNA operating |
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| 40 | system and the development of drivers for the hardware architectural templates. |
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[134] | 41 | For the \altera and \xilinx architectural templates, the OSs must also be ported on |
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[36] | 42 | the NIOS2 and MICROBLAZE processors. |
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[23] | 43 | \begin{livrable} |
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[278] | 44 | %IVG \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} |
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| 45 | %IVG The drivers required for the first CSG milestone (deliverable \csgCoachArch). |
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| 46 | %IVG \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers} |
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| 47 | %IVG The drivers required for the second CSG milestone ({\csgPrototypingOnly}). |
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| 48 | %IVG \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2} |
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| 49 | %IVG Final release of the MUTEKH OS drivers. |
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| 50 | %IVG \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0} |
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| 51 | %IVG Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. |
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[52] | 52 | \itemV{6}{8}{x}{\Stima}{DNA OS} |
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[278] | 53 | The drivers required for the first CSG milestone. |
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[52] | 54 | \itemV{8}{18}{x}{\Stima}{DNA 0S} |
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[278] | 55 | The drivers required for the second CSG milestone. |
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[216] | 56 | \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2} |
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[187] | 57 | Final release of the DNA OS drivers. |
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[216] | 58 | \itemL{6}{18}{x}{\Stima}{Porting of DNA OS}{3:1:0} |
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[108] | 59 | Porting of DNA OS on the NIOS2 and MICROBLAZE processors. |
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[23] | 60 | \end{livrable} |
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[278] | 61 | % |
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| 62 | \subtask{Implementation of CSG} This \ST corresponds to the COACH System Generator (CSG) software. |
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| 63 | \begin{livrable} |
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| 64 | \itemV{0}{12}{x}{\Supmc}{CSG tool} |
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| 65 | The first software release of the CSG tool that will allow demonstrators to start |
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| 66 | working by using the neutral architectural template only for SystemC. |
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| 67 | \itemV{12}{18}{x}{\Supmc}{CSG} |
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| 68 | The second release of CSG integrates the VHDL driver for the neutral |
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| 69 | architectural template, and an integration of an HLS tools |
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| 70 | but only for SystemC prototyping. |
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| 71 | \itemV{18}{24}{x}{\Supmc}{CSG} |
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| 72 | This release extends CSG to FPGA-SoC generation for the \xilinx and \altera architectural template. |
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| 73 | \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5} \setMacroInAuxFile{csgImplementation} |
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| 74 | Final release of CSG enhanced by the demonstrator's feedback. |
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| 75 | \end{livrable} |
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[23] | 76 | \end{workpackage} |
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